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Truth table and delay assumptions

For two input signals the C-element is defined by the equation y n = x 1 x 2 + ( x 1 + x 2 ) y n − 1 {\displaystyle y_{n}=x_{1}x_{2}+(x_{1}+x_{2})y_{n-1}} , which corresponds to the following truth table:

x 1 {\displaystyle x_{1}}	x 2 {\displaystyle x_{2}}	y n {\displaystyle y_{n}}
0	0	0
0	1	y n − 1 {\displaystyle y_{n-1}}
1	0	y n − 1 {\displaystyle y_{n-1}}
1	1	1

This table can be turned into a circuit using the Karnaugh map. However, the obtained implementation is naive, since nothing is said about delay assumptions. To understand under what conditions the obtained circuit is workable, it is necessary to do additional analysis, which reveals that

• delay1 is a propagation delay from node 1 via environment to node 3,
• delay2 is a propagation delay from node 1 via internal feedback to node 3,
• delay1 must be greater than delay2.

Thus, the naive implementation is correct only for slow environment.¹⁴

Implementations of the C-element

Depending on the requirements to the switching speed and power consumption, the C-element can be realized as a coarse- or fine-grain circuit. Also, one should distinguish between single-output and dual-rail¹⁵ realizations of C-element. A dual-rail C-element can be realized on 2-input NANDs (NORs) only.¹⁶ A single-output realization is workable if and only if:¹⁷

1. The circuit, where each input of a C-element is connected through a separate inverter to its output, is semimodular relatively to the state, where all the inverters are excited.
2. This state is live for the output gate of C-element.

Static and semistatic implementations

In his report¹⁸ Muller proposed to realize C-element as a majority gate with feedback. However, to avoid hazards linked with skews of internal delays, the majority gate must have as small number of transistors as possible.¹⁹²⁰ Generally, C-elements with different timing assumptions²¹ can be built on AND-OR-Invert (AOI)²²²³ or its dual, OR-AND-Invert (OAI) gate²⁴²⁵ and inverter. Yet another option patented by Varshavsky et al.^{26 27} is to shunt the input signals when they are not equal each other. Being very simple, these realizations dissipate more power due to the short-circuits. Connecting an additional majority gate to the inverted output of C-element, we obtain inclusive OR (EDLINCOR) function:²⁸²⁹ z n = x 1 x 2 + ( x 1 + x 2 ) y n ¯ {\displaystyle z_{n}=x_{1}x_{2}+(x_{1}+x_{2}){\overline {y_{n}}}} . Some simple asynchronous circuits like pulse distributors³⁰ can be built solely on majority gates.

Semistatic C-element stores its previous state using two cross-coupled inverters, similar to an SRAM cell. One of the inverters is weaker than the rest of the circuit, so it can be overpowered by the pull-up and pull-down networks. If both inputs are 0, then the pull-up network changes the latch's state, and the C-element outputs a 0. If both inputs are 1, then the pull-down network changes the latch's state, making the C-element output a 1. Otherwise, the input of the latch is not connected to either V dd {\displaystyle V_{\text{dd}}} or ground, and so the weak inverter dominates and the latch outputs its previous state. There are also versions of semistatic C-element built on devices with negative differential resistance (NDR).³¹³² NDR is usually defined for small signal, so it is difficult to expect that such a C-element will operate in full range of voltages or currents.[original research?]

Gate-level implementations

There is a number of different single-output circuits of C-element built on logic gates.³³³⁴ In particular, the so-called Maevsky's implementation ³⁵³⁶³⁷ is a semimodular, but non-distributive (OR-causal) circuit loosely based on.³⁸ The NAND3 gate in this circuit can be replaced by two NAND2 gates. Note that Maevsky's C-element is actually a Join element, whose input signals cannot switch twice.³⁹ Yet another circuit with OR-causality, which operates as a Join element.⁴⁰ A realization of C-element on two-input gates only has been proposed by Tsirlin ⁴¹ and then synthesized by Starodoubtsev et al. using Taxogram language⁴² This circuit coincides with that attributed to Bartky ,⁴³⁴⁴ and can operate without the input latch. Note that both the Maevsky and Tsirlin circuits are based actually on so-called David cell.⁴⁵ Its fast transistor-level implementation is used in the semistatic C-element proposed.⁴⁶ Yet another semistatic circuit using pass transistors (actually MUX 2:1) has been proposed.⁴⁷ Yet another version of the C-element built on two SR-latches has been synthesized by Murphy⁴⁸ using Petrify tool. However, this circuit includes inverter connected to one of the inputs. This inverter should have small delay. However, there are realizations of RS latches that already have one inverted input, for example.⁴⁹ Some speed-independent approaches⁵⁰⁵¹ assume that zero-delay input inverters are available on all gates, which is a violation of true speed-independence but is fairly safe in practice. Other examples of using this assumption also exist.⁵²

Non-transistor implementations

Other technologies suitable for realizing asynchronous primitives including C-element, are: carbon nanotubes, single-electron tunneling devices,⁵³ quantum dots,⁵⁴ and molecular nanotechnology.⁵⁵

Generalization for multiple-valued logic

The definition of C-element can be generalized for multiple-valued logic,⁵⁶⁵⁷⁵⁸ or even for continuous signals:

 if  x 1 = x 2 = . . . = x m ,  then  y n = any ( x 1 , x 2 , . . . , x m ) ,  else  y n = y n − 1 . {\displaystyle {\text{ if }}x_{1}=x_{2}=...=x_{m},{\text{ then }}y_{n}={\text{any}}(x_{1},x_{2},...,x_{m}),{\text{ else }}y_{n}=y_{n-1}.}

For example, the truth table for a balanced ternary C-element with two inputs is

x 1 {\displaystyle x_{1}}	x 2 {\displaystyle x_{2}}	y n {\displaystyle y_{n}}
−1	−1	−1
−1	0	y n − 1 {\displaystyle y_{n-1}}
−1	1	y n − 1 {\displaystyle y_{n-1}}
0	−1	y n − 1 {\displaystyle y_{n-1}}
0	0	0
0	1	y n − 1 {\displaystyle y_{n-1}}
1	−1	y n − 1 {\displaystyle y_{n-1}}
1	0	y n − 1 {\displaystyle y_{n-1}}
1	1	1

Since the majority gate is a particular case of threshold gate, any of known realizations of threshold gate⁵⁹ can in principle be used for building a C-element. In the multiple-valued case, however, connecting the output of majority gate to one or several inputs may have no desirable effect. For example, using the ternary majority function defined as⁶⁰

y = { + 1 if   x 1 + x 2 + x 3 ⩾ + 1 , 0 if   x 1 + x 2 + x 3 = 0 , − 1 if   x 1 + x 2 + x 3 ⩽ − 1 {\displaystyle y={\begin{cases}+1&{\text{if}}\ x_{1}+x_{2}+x_{3}\geqslant +1,\\0&{\text{if}}\ x_{1}+x_{2}+x_{3}=0,\\-1&{\text{if}}\ x_{1}+x_{2}+x_{3}\leqslant -1\end{cases}}}

does not lead to the ternary C-element specified by the truth table, if the sum x 1 + x 2 + x 3 {\displaystyle x_{1}+x_{2}+x_{3}} is not split into pairs. However, even without such a splitting two ternary majority functions are suitable for building a ternary inclusive OR gate.

External links

• Workcraft tool: Synthesis and verification of C-element

References

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