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Espresso (processor)
32-bit CPU for the Wii U

Espresso is the codename of the 32-bit central processing unit (CPU) used in Nintendo's Wii U video game console. It was designed by IBM, and was produced using a 45 nm silicon-on-insulator process. The Espresso chip resides together with a GPU from AMD on an MCM manufactured by Renesas. It was revealed at E3 2011 in June 2011 and released in November 2012.

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Design

IBM and Nintendo have revealed that the Espresso processor is a PowerPC-based microprocessor with three cores on a single chip to reduce power consumption and increase speed. The CPU and the graphics processor are placed on a single substrate as a multi-chip module (MCM) to reduce complexity, increase the communication speed between the chips, further reduce power consumption, and reduce cost and space required. The two chips were assembled to the complete MCM by Renesas in Japan.1 Espresso itself was manufactured by IBM in its 300 mm plant in East Fishkill, New York, using 45 nm SOI-technology2 and embedded DRAM (eDRAM) for caches.

While unverified by Nintendo, hackers, teardowns, and unofficial informants have since revealed more information about the Espresso, such as its name,3 size45 and speed.67 The microarchitecture seems to be quite similar to its predecessors the Broadway and Gekko, i.e. PowerPC 750 based, but enhanced with larger and faster caches and multiprocessor support.

Rumors that the Wii U CPU was derived from IBM's high-end POWER7 server processor proved false, as it would potentially increase the manufacturing and retail cost of the system, and require a larger form factor. Espresso shares some technology with POWER7, such as eDRAM and general instruction set similarities, but those are superficial similarities.89101112

Specifications

The following specifications have not been officially confirmed by either Nintendo or IBM. They have been obtained by reverse engineering by hacker Hector Martin, alias marcan.13

  • Broadway-based core architecture14
  • Three cores at 1.243125 GHz
  • Symmetric multiprocessing with MESI/MERSI support15
  • Each core can output up to 4 instructions per clock using superscalar parallelism.
  • 32-bit integer unit
  • 64-bit floating-point (or 2× 32-bit SIMD, often found under the denomination "paired singles")
  • A total of 3 MB of Level 2 cache in an unusual configuration.16
    • Core 0: 512 KB, core 1: 2 MB, core 2: 512 KB
  • 4 stage pipeline 17
  • 7 stage pipeline - FP18
  • 6 Execution Units per core (18 EUs total)19
  • Die size: 4.74 mm × 5.85 mm = 27.73 mm2

Further reading

References

  1. "Wii U : The Console : Changes in Television". Iwata Asks. Nintendo. Archived from the original on 2022-06-09. https://web.archive.org/web/20220609231841/https://iwataasks.nintendo.com/interviews/#/wiiu/console/0/0 ↩

  2. "NEW WII U™ ON SOI". Archived from the original on 2016-03-25. https://web.archive.org/web/20160325055520/http://www.advancedsubstratenews.com/2011/07/new-wii-u%E2%84%A2-on-soi/ ↩

  3. "World Exclusive: Wii U Final Specs". 11 September 2012. http://www.vgleaks.com/world-exclusive-wii-u-final-specs/ ↩

  4. "Nintendo Wii U Teardown". AnandTech. http://www.anandtech.com/show/6465/nintendo-wii-u-teardown ↩

  5. "Nintendo Wii U Teardown". iFixit. 19 November 2012. http://www.ifixit.com/Teardown/Nintendo+Wii+U+Teardown/11796 ↩

  6. "Wii U has 1.24GHz CPU, 550MHz graphics core". Eurogamer.net. 29 November 2012. http://www.eurogamer.net/articles/digitalfoundry-wii-hacker-reveals-wii-u-cpu-secrets ↩

  7. "Wii U CPU, GPU Details Uncovered". 29 November 2012. http://www.ign.com/articles/2012/11/29/wii-u-cpu-gpu-details-uncovered ↩

  8. "IBM puts Watson's brains in Nintendo Wii U". https://www.engadget.com/2011/06/07/ibm-puts-watsons-brains-in-nintendo-wii-u/ ↩

  9. "IBM teases on Wii U CPU specs". Eurogamer.net. 8 June 2011. http://www.eurogamer.net/articles/digitalfoundry-ibm-teases-on-wii-u-cpu ↩

  10. "Rumored Wii U Specs Raising Eyebrows... for the Wrong Reasons". https://www.pcmag.com/article2/0,2817,2397198,00.asp ↩

  11. "IBM reconfirms the Wii U/Watson connection". 27 August 2012. http://www.gonintendo.com/?mode=viewstory&id=184227 ↩

  12. "IBM Confirms WII U Utilizes Power-Based CPU, Not Power 7". 25 September 2012. http://hothardware.com/News/IBM-Confirms-WII-U-Utilizes-PowerBased-CPU-Not-Power-7 ↩

  13. Joel Hruska (November 29, 2012). "Hackers Discover Wii U's Processor Design and Clock Speed". HotHardware. Retrieved January 21, 2014. http://hothardware.com/News/Hackers-Discover-Wii-Us-Clock-Speed-Processor-Design/ ↩

  14. Martín, Héctor [@marcan42] (2012-12-09). "@DFaker no, it's just a 750. PPC750 can issue 3/cycle and retire 2/cycle. @dampflokfreund yes, three Broadways and more cache" (Tweet). Archived from the original on 2013-10-05 – via Twitter. https://web.archive.org/web/20131005034521/https://twitter.com/marcan42/status/277823057844903938 ↩

  15. Martín, Héctor [@marcan42] (2013-11-23). "Hah! My Twitter arguing must be so sad that I just got this screenshot in my inbox (anon sender): https://marcansoft.com/transf/espresso_intro.png … @EyeOfCore" (Tweet). Archived from the original on 2013-12-03 – via Twitter. (links to PNG of a page from the IBM Espresso RISC Processor Developer's User Manual) https://web.archive.org/web/20131203061611/https://twitter.com/marcan42/status/404310017882726400 ↩

  16. Martín, Héctor [@marcan42] (2013-01-30). "@theevilmuppet L1 is the same, L2 is different (this is the claimed eDRAM). 512K/2M/512K L2 cache per core (core 1 has more cache)" (Tweet). Archived from the original on 2013-10-08 – via Twitter. https://web.archive.org/web/20131008041027/https://twitter.com/marcan42/status/296605342568153089 ↩

  17. "IBM PowerPC 750CL Microprocessor Revision Level DD2.x Datasheet" (PDF). https://fail0verflow.com/media/files/ppc_750cl.pdf ↩

  18. "IBM PowerPC 750CL Microprocessor Revision Level DD2.x Datasheet" (PDF). https://fail0verflow.com/media/files/ppc_750cl.pdf ↩

  19. "IBM PowerPC 750CL Microprocessor Revision Level DD2.x Datasheet" (PDF). https://fail0verflow.com/media/files/ppc_750cl.pdf ↩