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Instruction set architecture

Computing devices have instruction sets, which are their lowest, most primitive languages. Common instructions are those which cause two numbers to be added, multiplied or combined in other ways, as well as instructions that direct the processor where to look in memory for its next instruction. There are many other types of instructions.

Assemblers and compilers that translate computer programs into streams of instructions – bit streams - that the device can understand and carry out (execute). As an instruction stream executes, the integrity of system function is supported by the use of instruction privilege levels. Privileged instructions have access to more resources in the device, including memory. Hexagon supports privilege levels.

Originally, Hexagon instructions operated on integer numbers but not floating point numbers,⁴ but in v5 floating point support was added.⁵

The processing unit which handles execution of instructions is capable of in-order dispatching up to 4 instructions (the packet) to 4 Execution Units every clock.⁶⁷

Micro-architecture

Micro-architecture is the physical structure of a chip or chip component that makes it possible for a device to carry out the instructions. A given instruction set can be implemented by a variety of micro-architectures. The buses – data transfer channels – for Hexagon devices are 32 bits wide. That is, 32 bits of data can be moved from one part of the chip to another in a single step. The Hexagon micro-architecture is multi-threaded,⁸ which means that it can simultaneously process more than one stream of instructions, enhancing data processing speed. Hexagon supports very long instruction words,⁹¹⁰ which are groupings of four instructions that can be executed “in parallel.” Parallel execution means that multiple instructions can run simultaneously without one instruction having to complete before the next one starts. The Hexagon micro-architecture supports single instruction, multiple data operations,¹¹ which means that when a Hexagon device receives an instruction, it can carry out the operation on more than one piece of data at the same time.

According to 2012 estimation, Qualcomm shipped 1.2 billion DSP cores inside its system on a chip (SoCs) (average 2.3 DSP core per SoC) in 2011, and 1.5 billion cores were planned for 2012, making the QDSP6 the most shipped architecture of DSP¹² (CEVA had around 1 billion of DSP cores shipped in 2011 with 90% of IP-licensable DSP market¹³).

The Hexagon architecture is designed to deliver performance with low power over a variety of applications. It has features such as hardware assisted multithreading, privilege levels, Very Long Instruction Word (VLIW), Single Instruction Multiple Data (SIMD),¹⁴¹⁵ and instructions geared toward efficient signal processing. Hardware multithreading is implemented as barrel temporal multithreading - threads are switched in round-robin fashion each cycle, so the 600 MHz physical core is presented as three logical 200 MHz cores before V5.¹⁶¹⁷ Hexagon V5 switched to dynamic multithreading (DMT) with thread switch on L2 misses, interrupt waiting or on special instructions.¹⁸¹⁹

At Hot Chips 2013 Qualcomm announced details of their Hexagon 680 DSP. Qualcomm announced Hexagon Vector Extensions (HVX). HVX is designed to allow significant compute workloads for advanced imaging and computer vision to be processed on the DSP instead of the CPU.²⁰ In March 2015 Qualcomm announced their Snapdragon Neural Processing Engine SDK which allow AI acceleration using the CPU, GPU and Hexagon DSP.²¹

Qualcomm's Snapdragon 855 contains their 4th generation on-device AI engine, which includes the Hexagon 690 DSP and Hexagon Tensor Accelerator (HTA) for AI acceleration.²² Snapdragon 865 contains the 5th generation on-device AI engine based on the Hexagon 698 DSP capable of 15 trillion operations per second (TOPS).²³ Snapdragon 888 contains the 6th generation on-device AI engine based on the Hexagon 780 DSP capable of 26 TOPS.²⁴ Snapdragon 8 contains the 7th generation on-device AI engine based on the Hexagon DSP capable of 52 TOPS and up to 104 TOPS in some cases.²⁵

Software support

Operating systems

The port of Linux for Hexagon runs under a hypervisor layer ("Hexagon Virtual Machine"²⁶) and was merged with the 3.2 release of the kernel.²⁷²⁸ The original hypervisor is closed-source, and in April 2013 a minimal open-source hypervisor implementation for QDSP6 V2 and V3, the "Hexagon MiniVM" was released by Qualcomm under a BSD-style license.²⁹³⁰

Compilers

Support for Hexagon was added in 3.1 release of LLVM by Tony Linthicum.³¹ Hexagon/HVX V66 ISA support was added in 8.0.0 release of LLVM.³² There is also a non-FSF maintained branch of GCC and binutils.³³

Adoption of the SIP block

Qualcomm Hexagon DSPs have been available in Qualcomm Snapdragon SoC since 2006.³⁴³⁵ In Snapdragon S4 (MSM8960 and newer) there are three QDSP cores, two in the Modem subsystem and one Hexagon core in the Multimedia subsystem. Modem cores are programmed by Qualcomm only, and only Multimedia core is allowed to be programmed by user.

They are also used in some femtocell processors of Qualcomm, including FSM98xx, FSM99xx and FSM90xx.³⁶

Third-party integration

In March 2016, it was announced that semiconductor company Conexant's AudioSmart audio processing software was being integrated into Qualcomm's Hexagon.³⁷

In May 2018 wolfSSL added support for using Qualcomm Hexagon.³⁸ This is support for running wolfSSL crypto operations on the DSP. In addition to use of crypto operations a specialized operation load management library was later added.

Versions

There are six versions of QDSP6 architecture released: V1 (2006), V2 (2007–2008), V3 (2009), V4 (2010–2011), QDSP6 V5 (2013, in Snapdragon 800),³⁹ and QDSP6 V6 (2016, in Snapdragon 820)⁴⁰ V4 has 20 DMIPS per milliwatt, operating at 500 MHz.⁴¹⁴²

Clock speed of Hexagon varies in 400–2000 MHz for QDSP6 and in 256–350 MHz for previous generation of the architecture, the QDSP5.⁴³

Availability in Snapdragon products

Both Hexagon (QDSP6) and pre-Hexagon (QDSP5) cores are used in modern Qualcomm SoCs, QDSP5 mostly in low-end products. Modem QDSPs (often pre-Hexagon) are not shown in the table.

QDSP5 usage:

QDSP6 (Hexagon) usage:

Hardware codec supported

The different video codecs supported by the Snapdragon SoCs.

D - decode; E - encode

FHD = FullHD = 1080p = 1920x1080px

HD = 720p which can be 1366x768px or 1280x720px

Snapdragon 200 series

The different video codecs supported by the Snapdragon 200 series.

Snapdragon 400 series

The different video codecs supported by the Snapdragon 400 series.

Snapdragon 600 series

The different video codecs supported by the Snapdragon 600 series.

Snapdragon 700 series

The different video codecs supported by the Snapdragon 700 series.

Snapdragon 800 series

The different video codecs supported by the Snapdragon 800 series.

Code sample

This is a single instruction packet from the inner loop of a FFT:¹⁴⁴¹⁴⁵

This packet is claimed by Qualcomm to be equal to 29 classic RISC operations; it includes vector add (4x 16-bit), complex multiply operation and hardware loop support. All instructions of the packet are done in the same cycle.

See also

• Qualcomm Snapdragon
• List of Qualcomm Snapdragon processors
• Nvidia NVDEC
• Nvidia NVENC
• Texas Instruments TMS320
• CEVA, Inc.
• Super Harvard Architecture Single-Chip Computer
• Digital signal processing
• Cryptography
• Instruction set architecture
• Microarchitecture
• Very long instruction word
• SIMD
• Multi-threading
• System on a chip
• Hypervisor
• Codec
• Fast Fourier transform
• Cellular network
• Conexant

External links

• Qualcomm's Hexagon home page
• Upcoming DSP architectures, Arnd Bergmann // LWN
• Introduction to Qualcomm’s QDSP Access Program // Qualcomm, 2011
• Qualcomm Hexagon DSP: An architecture optimized for mobile multimedia and communications // Lucian Codrescu (Qualcomm), Hot Chips 25, Palo Alto, CA, August 2013.
• Qualcomm Extends Hexagon DSP: Hexagon v5 Adds Floating-Point Math, Dynamic Multithreading // Linley Gwennap, Microprocessor Report, August 2013.

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