• Images
• Videos
• Documents
• Books
• Articles

Related Image Collections Add Image

Profiles

1 Image

We don't have any YouTube videos related to Xeon Phi yet.

You can add one yourself here.

We don't have any PDF documents related to Xeon Phi yet.

You can add one yourself here.

We don't have any Books related to Xeon Phi yet.

You can add one yourself here.

Archived Web Articles Add Article

Intel christens its 'Many Integrated Core' products Xeon Phi, eyes exascale milestone

Jun 18 2012

History

Background

The Larrabee microarchitecture (in development since 2006¹²) introduced very wide (512-bit) SIMD units to an x86 architecture based processor design, extended to a cache-coherent multiprocessor system connected via a ring bus to memory; each core was capable of four-way multithreading. Due to the design being intended for GPU as well as general purpose computing, the Larrabee chips also included specialised hardware for texture sampling.¹³¹⁴ The project to produce a retail GPU product directly from the Larrabee research project was terminated in May 2010.¹⁵

Another contemporary Intel research project implementing x86 architecture on a many-multicore processor was the 'Single-chip Cloud Computer' (prototype introduced 2009¹⁶), a design mimicking a cloud computing computer datacentre on a single chip with multiple independent cores: the prototype design included 48 cores per chip with hardware support for selective frequency and voltage control of cores to maximize energy efficiency, and incorporated a mesh network for inter-chip messaging. The design lacked cache-coherent cores and focused on principles that would allow the design to scale to many more cores.¹⁷

The Teraflops Research Chip (prototype unveiled 2007¹⁸) is an experimental 80-core chip with two floating-point units per core, implementing a 96-bit VLIW architecture instead of the x86 architecture.¹⁹ The project investigated intercore communication methods, per-chip power management, and achieved 1.01 TFLOPS at 3.16 GHz consuming 62 W of power.²⁰²¹

Knights Ferry

Intel's Many Integrated Core (MIC) prototype board, named Knights Ferry, incorporating a processor codenamed Aubrey Isle was announced 31 May 2010. The product was stated to be a derivative of the Larrabee project and other Intel research including the Single-chip Cloud Computer.²²²³

The development product was offered as a PCIe card with 32 in-order cores at up to 1.2 GHz with four threads per core, 2 GB GDDR5 memory,²⁴ and 8 MB coherent L2 cache (256 KB per core with 32 KB L1 cache), and a power requirement of ≈300 W,²⁵ built at a 45 nm process.²⁶ In the Aubrey Isle core a 1,024-bit ring bus (512-bit bi-directional) connects processors to main memory.²⁷ Single-board performance has exceeded 750 GFLOPS.²⁸ The prototype boards only support single-precision floating-point instructions.²⁹

Initial developers included CERN, Korea Institute of Science and Technology Information (KISTI) and Leibniz Supercomputing Centre. Hardware vendors for prototype boards included IBM, SGI, HP, Dell and others.³⁰

Knights Corner

The Knights Corner product line is made at a 22 nm process size, using Intel's Tri-gate technology with more than 50 cores per chip, and is Intel's first many-cores commercial product.³¹³²

In June 2011, SGI announced a partnership with Intel to use the MIC architecture in its high-performance computing products.³³ In September 2011, it was announced that the Texas Advanced Computing Center (TACC) will use Knights Corner cards in their 10-petaFLOPS "Stampede" supercomputer, providing 8 petaFLOPS of compute power.³⁴ According to "Stampede: A Comprehensive Petascale Computing Environment" the "second-generation Intel (Knights Landing) MICs will be added when they become available, increasing Stampede's aggregate peak performance to at least 15 PetaFLOPS."³⁵

On 15 November 2011, Intel showed an early silicon version of a Knights Corner processor.³⁶³⁷

On 5 June 2012, Intel released open source software and documentation regarding Knights Corner.³⁸

On 18 June 2012, Intel announced at the 2012 Hamburg International Supercomputing Conference that Xeon Phi will be the brand name used for all products based on their Many Integrated Core architecture.^{39404142434445} In June 2012, Cray announced it would be offering 22 nm 'Knight's Corner' chips (branded as 'Xeon Phi') as a co-processor in its 'Cascade' systems.⁴⁶⁴⁷

In June 2012, ScaleMP announced a virtualization update allowing Xeon Phi as a transparent processor extension, allowing legacy MMX/SSE code to run without code changes.⁴⁸ An important component of the Intel Xeon Phi coprocessor's core is its vector processing unit (VPU).⁴⁹ The VPU features a novel 512-bit SIMD instruction set, officially known as Intel Initial Many Core Instructions (Intel IMCI). Thus, the VPU can execute 16 single-precision (SP) or 8 double-precision (DP) operations per cycle. The VPU also supports Fused Multiply-Add (FMA) instructions and hence can execute 32 SP or 16 DP floating point operations per cycle. It also provides support for integers. The VPU also features an Extended Math Unit (EMU) that can execute operations such as reciprocal, square root, and logarithm, thereby allowing these operations to be executed in a vector fashion with high bandwidth. The EMU operates by calculating polynomial approximations of these functions.

On 12 November 2012, Intel announced two Xeon Phi coprocessor families using the 22 nm process size: the Xeon Phi 3100 and the Xeon Phi 5110P.⁵⁰⁵¹⁵² The Xeon Phi 3100 will be capable of more than 1 teraFLOPS of double-precision floating-point instructions with 240 GB/s memory bandwidth at 300 W.⁵³⁵⁴⁵⁵ The Xeon Phi 5110P will be capable of 1.01 teraFLOPS of double-precision floating-point instructions with 320 GB/s memory bandwidth at 225 W.⁵⁶⁵⁷⁵⁸ The Xeon Phi 7120P will be capable of 1.2 teraFLOPS of double-precision floating-point instructions with 352 GB/s memory bandwidth at 300 W.

On 17 June 2013, the Tianhe-2 supercomputer was announced⁵⁹ by TOP500 as the world's fastest. Tianhe-2 used Intel Ivy Bridge Xeon and Xeon Phi processors to achieve 33.86 petaFLOPS. It was the fastest on the list for two and a half years, lastly in November 2015.⁶⁰

Design and programming

The cores of Knights Corner are based on a modified version of P54C design, used in the original Pentium.⁶¹ The basis of the Intel MIC architecture is to leverage x86 legacy by creating an x86-compatible multiprocessor architecture that can use existing parallelization software tools.⁶² Programming tools include OpenMP,⁶³ OpenCL,⁶⁴ Cilk/Cilk Plus and specialised versions of Intel's Fortran, C++⁶⁵ and math libraries.⁶⁶

Design elements inherited from the Larrabee project include x86 ISA, 4-way SMT per core, 512-bit SIMD units, 32 KB L1 instruction cache, 32 KB L1 data cache, coherent L2 cache (512 KB per core⁶⁷), and ultra-wide ring bus connecting processors and memory.

The Knights Corner 512-bit SIMD instructions share many intrinsic functions with AVX-512 extension . The instruction set documentation is available from Intel under the extension name of KNC.^68697071

Knights Landing

Code name for the second-generation MIC architecture product from Intel.⁸⁶ Intel officially first revealed details of its second-generation Intel Xeon Phi products on 17 June 2013.⁸⁷ Intel said that the next generation of Intel MIC Architecture-based products will be available in two forms, as a coprocessor or a host processor (CPU), and be manufactured using Intel's 14 nm process technology. Knights Landing products will include integrated on-package memory for significantly higher memory bandwidth.

Knights Landing contains up to 72 Airmont (Atom) cores with four threads per core,⁸⁸⁸⁹ using LGA 3647 socket⁹⁰ supporting up to 384 GB of "far" DDR4 2133 RAM and 8–16 GB of stacked "near" 3D MCDRAM, a version of the Hybrid Memory Cube. Each core has two 512-bit vector units and supports AVX-512 SIMD instructions, specifically the Intel AVX-512 Foundational Instructions (AVX-512F) with Intel AVX-512 Conflict Detection Instructions (AVX-512CD), Intel AVX-512 Exponential and Reciprocal Instructions (AVX-512ER), and Intel AVX-512 Prefetch Instructions (AVX-512PF). Support for IMCI has been removed in favor of AVX-512.⁹¹

The National Energy Research Scientific Computing Center announced that Phase 2 of its newest supercomputing system "Cori" would use Knights Landing Xeon Phi coprocessors.⁹²

On 20 June 2016, Intel launched the Intel Xeon Phi product family x200 based on the Knights Landing architecture, stressing its applicability to not just traditional simulation workloads, but also to machine learning.⁹³⁹⁴ The model lineup announced at launch included only Xeon Phi of bootable form-factor, but two versions of it: standard processors and processors with integrated Intel Omni-Path architecture fabric.⁹⁵ The latter is denoted by the suffix F in the model number. Integrated fabric is expected to provide better latency at a lower cost than discrete high-performance network cards.⁹⁶

On 14 November 2016, the 48th list of TOP500 contained two systems using Knights Landing in the Top 10.⁹⁷

The PCIe based co-processor variant of Knight's Landing was never offered to the general market and was discontinued by August 2017.⁹⁸ This included the 7220A, 7240P and 7220P coprocessor cards.

Intel announced they were discontinuing Knights Landing in summer 2018.⁹⁹

Models

All models can boost to their peak speeds, adding 200 MHz to their base frequency when running just one or two cores. When running from three to the maximum number of cores, the chips can only boost 100 MHz above the base frequency. All chips run high-AVX code at a frequency reduced by 200 MHz.¹⁰⁰

Knights Mill

Knights Mill is Intel's codename for a Xeon Phi product specialized in deep learning,¹¹³ initially released in December 2017.¹¹⁴ Nearly identical in specifications to Knights Landing, Knights Mill includes optimizations for better utilization of AVX-512 instructions. Single-precision and variable-precision floating-point performance increased, at the expense of double-precision floating-point performance.

Models

Knights Hill

Knights Hill was the codename for the third-generation MIC architecture, for which Intel announced the first details at SC14.¹¹⁵ It was to be manufactured in a 10 nm process.¹¹⁶

Knights Hill was expected to be used in the United States Department of Energy Aurora supercomputer, to be deployed at Argonne National Laboratory.¹¹⁷¹¹⁸ However, Aurora was delayed in favor of using an "advanced architecture" with a focus on machine learning.¹¹⁹¹²⁰

In 2017, Intel announced that Knights Hill had been canceled in favor of another architecture built from the ground up to enable Exascale computing in the future. This new architecture was expected for 2020–2021,¹²¹¹²² however this was also cancelled due to the discontinuation of the Xeon Phi.

Programming

One performance and programmability study reported that achieving high performance with Xeon Phi still needs help from programmers and that merely relying on compilers with traditional programming models is insufficient.¹²³ Other studies in various domains, such as life sciences¹²⁴ and deep learning,¹²⁵ have shown that exploiting the thread- and SIMD-parallelism of Xeon Phi achieves significant speed-ups.

Competitors

• Nvidia Tesla, a direct competitor in the HPC market¹²⁶
• AMD Radeon Pro and AMD Radeon Instinct direct competitors in the HPC market

See also

• Texas Advanced Computing Center – "Stampede" supercomputer incorporates Xeon Phi chips.¹²⁷ Stampede is capable of 10 petaFLOPS.¹²⁸
• AVX-512
• Cell (microprocessor)
• Intel Tera-Scale
• Massively parallel
• Xeon

External links

• Intel pages: Intel Xeon Phi Processors
• Chips and Cheese, December 8, 2022, Knight's Landing: Atom with AVX-512

References

1. Radek (18 June 2012). "Chip Shot: Intel Names the Technology to Revolutionize the Future of HPC - Intel Xeon Phi Product Family". Intel. Retrieved 12 December 2012. https://newsroom.intel.com/community/intel_newsroom/blog/2012/06/18/intel-names-the-technology-to-revolutionize-the-future-of-hpc--intel-xeon-phi-product-family ↩

2. robert-reed (4 February 2013). "Best Known Methods for Using OpenMP on Intel Many Integrated Core (Intel MIC) Architecture". software.intel.com. https://software.intel.com/en-us/articles/best-known-methods-for-using-openmp-on-intel-many-integrated-core-intel-mic-architecture ↩

3. Jeffers, James; Reinders, James (1 March 2013). Intel Xeon Phi Coprocessor High Performance Programming. Morgan Kaufmann. ISBN 978-0124104143. 978-0124104143 ↩

4. Hruska, Joel (8 May 2019). "Intel Quietly Kills Off Xeon Phi". ExtremeTech. https://www.extremetech.com/extreme/290963-intel-quietly-kills-off-xeon-phi ↩

5. "Intel scraps graphics chip based on Larrabee". Reuters. 6 December 2009. https://www.reuters.com/article/us-intel/intel-scraps-graphics-chip-based-on-larrabee-idUSTRE5B51QR20091206?type=technologyNews ↩

6. Sodani, Avinash; et al. (2016). "Knights Landing: Second-Generation Intel Xeon Phi Product". IEEE Micro. 36 (2): 34–46. doi:10.1109/MM.2016.25. S2CID 28837176. /wiki/IEEE_Micro ↩

7. "TOP500 - June 2013". TOP500. Retrieved 18 June 2013. https://www.top500.org/lists/2013/06/ ↩

8. "June 2023 | TOP500 Supercomputer Sites". www.top500.org. https://www.top500.org/lists/top500/list/2023/06/ ↩

9. "Intel Powers the World's Fastest Supercomputer, Reveals New and Future High Performance Computing Technologies". Retrieved 21 June 2013. https://newsroom.intel.com/community/intel_newsroom/blog/2013/06/17/intel-powers-the-worlds-fastest-supercomputer-reveals-new-and-future-high-performance-computing-technologies ↩

10. W1zzard (24 July 2018). "Intel is Giving up on Xeon Phi - Eight More Models Declared End-Of-Life". TechPowerUp.{{cite web}}: CS1 maint: numeric names: authors list (link) https://www.techpowerup.com/246237/intel-is-giving-up-on-xeon-phi-eight-more-models-declared-end-of-life ↩

11. Marc Sauter (20 June 2016). "Knights Landing: Intel veröffentlicht Xeon Phi mit bis zu 7 Teraflops - Golem.de". www.golem.de (in German). https://www.golem.de/news/knights-landing-intel-veroeffentlicht-xeon-phi-mit-bis-zu-7-teraflops-1606-121642.html ↩

12. Charlie Demerjian (3 July 2006), "New from Intel: It's Mini-Cores!", theinquirer.net, The Inquirer, archived from the original on 29 August 2009 https://web.archive.org/web/20090829084338/http://www.theinquirer.net/inquirer/news/1029138/new-from-intel-its-mini-cores ↩

13. Seiler, L.; Cavin, D.; Espasa, E.; Grochowski, T.; Juan, M.; Hanrahan, P.; Carmean, S.; Sprangle, A.; Forsyth, J.; Abrash, R.; Dubey, R.; Junkins, E.; Lake, T.; Sugerman, P. (August 2008). "Larrabee: A Many-Core x86 Architecture for Visual Computing" (PDF). ACM Transactions on Graphics. Proceedings of ACM SIGGRAPH 2008. 27 (3): 18:11. doi:10.1145/1360612.1360617. ISSN 0730-0301. S2CID 52799248. Archived from the original (PDF) on 10 September 2015. Retrieved 6 August 2008. https://web.archive.org/web/20150910141236/https://software.intel.com/sites/default/files/m/9/4/9/larrabee_manycore.pdf ↩

14. Tom Forsyth, SIMD Programming with Larrabee (PDF), Intel https://www.stanford.edu/class/ee380/Abstracts/100106-slides.pdf ↩

15. Ryan Smith (25 May 2010), "Intel Kills Larrabee GPU, Will Not Bring a Discrete Graphics Product to Market\", www.anandtech.com, AnandTech https://www.anandtech.com/show/3738/intel-kills-larrabee-gpu-will-not-bring-a-discrete-graphics-product-to-market ↩

16. Tony Bradley (3 December 2009), "Intel 48-Core "Single-Chip Cloud Computer" Improves Power Efficiency", pcworld.com, PCWorld https://www.pcworld.com/article/183653/intel_48core_singlechip_cloud_computer_improves_power_efficiency.html ↩

17. "Intel Research : Single-Chip Cloud Computer", techresearch.intel.com, Intel http://techresearch.intel.com/ProjectDetails.aspx?Id=1 ↩

18. Ben Ames (11 February 2007), "Intel Tests Chip Design With 80-Core Processor", pcworld.com, IDG News, archived from the original on 17 January 2012, retrieved 14 November 2018 https://web.archive.org/web/20120117194144/https://www.pcworld.com/article/128924/intel_tests_chip_design_with_80core_processor.html ↩

19. "Intel Details 80-Core Teraflops Research Chip - X-bit labs". xbitlabs.com. Archived from the original on 5 February 2015. Retrieved 27 August 2015. https://web.archive.org/web/20150205070552/http://www.xbitlabs.com/news/cpu/display/20070212224710.html ↩

20. "Intel's Teraflops Research Chip" (PDF), download.intel.com, Intel, archived from the original (PDF) on 16 May 2021 https://web.archive.org/web/20210516003332/https://download.intel.com/pressroom/kits/Teraflops/Teraflops_Research_Chip_Overview.pdf ↩

21. Anton Shilov (12 February 2007), "Intel Details 80-Core Teraflops Research Chip", xbitlabs.com, Xbit laboratories, archived from the original on 5 February 2015 https://web.archive.org/web/20150205070552/http://www.xbitlabs.com/news/cpu/display/20070212224710.html ↩

22. Rupert Goodwins (1 June 2010), "Intel unveils many-core Knights platform for HPC", zdnet.co.uk, ZDNet http://www.zdnet.co.uk/news/desktop-hardware/2010/06/01/intel-unveils-many-core-knights-platform-for-hpc-40089093/ ↩

23. "Intel News Release : Intel Unveils New Product Plans for High-Performance Computing", intel.com, Intel, 31 May 2010 https://www.intel.com/pressroom/archive/releases/2010/20100531comp.htm ↩

24. Mike Giles (24 June 2010), "Runners and riders in GPU steeplechase" (PDF), people.maths.ox.ac.uk, pp. 8–10 http://people.maths.ox.ac.uk/gilesm/talks/nag_tpc10.pdf ↩

25. Mike Giles (24 June 2010), "Runners and riders in GPU steeplechase" (PDF), people.maths.ox.ac.uk, pp. 8–10 http://people.maths.ox.ac.uk/gilesm/talks/nag_tpc10.pdf ↩

26. Gareth Halfacree (20 June 2011), "Intel pushes for HPC space with Knights Corner", thinq.co.uk, Net Communities Limited, UK http://www.thinq.co.uk/2011/6/20/intel-pushes-hpc-space-knights-corner/ ↩

27. "Intel Many Integrated Core Architecture" (PDF), many-core.group.cam.ac.uk, Intel, December 2010, archived from the original (PDF) on 2 April 2012 https://web.archive.org/web/20120402211714/http://www.many-core.group.cam.ac.uk/ukgpucc2/talks/Elgar.pdf ↩

28. Gareth Halfacree (20 June 2011), "Intel pushes for HPC space with Knights Corner", thinq.co.uk, Net Communities Limited, UK http://www.thinq.co.uk/2011/6/20/intel-pushes-hpc-space-knights-corner/ ↩

29. Rick Merritt (20 June 2011), "OEMs show systems with Intel MIC chips", EE Times https://www.eetimes.com/electronics-news/4217092/OEMs-show-systems-with-Intel-MIC-chips ↩

30. Tom R. Halfhill (18 July 2011), "Intel Shows MIC Progress", linleygroup.com, The Linley Group http://www.linleygroup.com/newsletters/newsletter_detail.php?num=4729 ↩

31. Rupert Goodwins (1 June 2010), "Intel unveils many-core Knights platform for HPC", zdnet.co.uk, ZDNet http://www.zdnet.co.uk/news/desktop-hardware/2010/06/01/intel-unveils-many-core-knights-platform-for-hpc-40089093/ ↩

32. Gareth Halfacree (20 June 2011), "Intel pushes for HPC space with Knights Corner", thinq.co.uk, Net Communities Limited, UK http://www.thinq.co.uk/2011/6/20/intel-pushes-hpc-space-knights-corner/ ↩

33. Andrea Petrou (20 June 2011), "SGI wants Intel for super supercomputer", news.techeye.net, archived from the original on 16 September 2011 https://web.archive.org/web/20110916013050/http://news.techeye.net/hardware/sgi-wants-intel-for-super-supercomputer ↩

34. ""Stampede's" Comprehensive Capabilities to Bolster U.S. Open Science Computational Resources" (Press release). Texas Advanced Computing Center. 22 September 2011. Archived from the original on 5 August 2012. Retrieved 23 September 2011. https://web.archive.org/web/20120805125957/http://www.tacc.utexas.edu/news/press-releases/2011/stampede ↩

35. "Stampede: A Comprehensive Petascale Computing Environment" (PDF). IEEE Cluster 2011 Special Topic. Archived from the original (PDF) on 26 September 2012. Retrieved 16 November 2011. https://www.webcitation.org/6AyMCTibp?url=http://www.ieeecluster.org/2011/images/program/Stampede_Abstracts.pdf ↩

36. Yam, Marcus (16 November 2011), "Intel's Knights Corner: 50+ Core 22nm Co-processor", tomshardware.com, Tom's Hardware, retrieved 16 November 2011 https://www.tomshardware.com/news/intel-knights-corner-mic-co-processor,14002.html ↩

37. Sylvie Barak (16 November 2011), "Intel unveils 1 TFLOP/s Knights Corner", EE Times, retrieved 16 November 2011 https://www.eetimes.com/electronics-news/4230654/Intel-unveils-1-TFLOP-s-Knight-s-Corner ↩

38. James Reinders (5 June 2012), Knights Corner: Open source software stack, Intel https://software.intel.com/en-us/blogs/2012/06/05/knights-corner-open-source-software-stack ↩

39. Radek (18 June 2012). "Chip Shot: Intel Names the Technology to Revolutionize the Future of HPC - Intel Xeon Phi Product Family". Intel. Retrieved 12 December 2012. https://newsroom.intel.com/community/intel_newsroom/blog/2012/06/18/intel-names-the-technology-to-revolutionize-the-future-of-hpc--intel-xeon-phi-product-family ↩

40. Prickett Morgan, Timothy (18 June 2012), "Intel slaps Xeon Phi brand on MIC coprocessors", 222.theregister.co.uk https://www.theregister.co.uk/2012/06/18/intel_mic_xeon_phi_cray/ ↩

41. Intel Corporation (18 June 2012), "Latest Intel Xeon Processors E5 Product Family Achieves Fastest Adoption of New Technology on Top500 List", marketwatch.com, archived from the original on 20 June 2012, retrieved 18 June 2012, Intel Xeon Phi is the new brand name for all future Intel Many Integrated Core Architecture based products targeted at HPC, enterprise, datacenters and workstations. The first Intel Xeon Phi product family member is scheduled for volume production by the end of 2012 https://web.archive.org/web/20120620222352/http://www.marketwatch.com/story/latest-intelr-xeonr-processors-e5-product-family-achieves-fastest-adoption-of-new-technology-on-top500-list-2012-06-18 ↩

42. Raj Hazra (18 June 2012). "Intel Xeon Phi coprocessors accelerate the pace of discovery and innovation". Intel. Retrieved 12 December 2012. https://blogs.intel.com/technology/2012/06/intel-xeon-phi-coprocessors-accelerate-discovery-and-innovation/ ↩

43. Rick Merritt (18 June 2012). "Cray will use Intel MIC, branded Xeon Phi". EETimes. Retrieved 12 December 2012. https://www.eetimes.com/electronics-news/4375500/Cray-will-use-Intel-MIC--branded-Xeon-Phi ↩

44. Terrence O'Brien (18 June 2012). "Intel christens its 'Many Integrated Core' products Xeon Phi, eyes exascale milestone". Engadget. Retrieved 12 December 2012. https://www.engadget.com/2012/06/18/intel-christens-its-mic-products-xeon-phi/ ↩

45. Jeffrey Burt (18 June 2012). "Intel Wraps Xeon Phi Branding Around MIC Coprocessors". eWeek. Retrieved 7 March 2022. https://www.eweek.com/networking/intel-wraps-xeon-phi-branding-around-mic-coprocessors/ ↩

46. Merritt, Rick (8 June 2012), "Cray will use Intel MIC, branded Xeon Phi", eetimes.com https://www.eetimes.com/electronics-news/4375500/Cray-will-use-Intel-MIC--branded-Xeon-Phi ↩

47. Latif, Lawrence (19 June 2012), "Cray to support Intel's Xeon Phi in Cascade clusters", theinquirer.net, archived from the original on 22 June 2012 https://web.archive.org/web/20120622064502/http://www.theinquirer.net/inquirer/news/2184891/cray-support-intels-xeon-phi-cascade-clusters ↩

48. "ScaleMP vSMP Foundation to Support Intel Xeon Phi" (Press release). ScaleMP. 20 June 2012. Archived from the original on 20 May 2013. https://web.archive.org/web/20130520072517/http://www.scalemp.com/media-hub-item/scalemp-vsmp-foundation-to-support-intel-xeon-phi/ ↩

49. George Chrysos (12 November 2012). "Intel Xeon Phi X100 Family Coprocessor - the Architecture". software.intel.com. https://software.intel.com/en-us/articles/intel-xeon-phi-coprocessor-codename-knights-corner ↩

50. IntelPR (12 November 2012). "Intel Delivers New Architecture for Discovery with Intel Xeon Phi Coprocessors". Intel. Retrieved 12 December 2012. https://newsroom.intel.com/community/intel_newsroom/blog/2012/11/12/intel-delivers-new-architecture-for-discovery-with-intel-xeon-phi-coprocessors ↩

51. Agam Shah (12 November 2012). "Intel ships 60-core Xeon Phi processor". Computerworld. Archived from the original on 12 March 2013. Retrieved 12 December 2012. https://web.archive.org/web/20130312145710/http://www.computerworld.com/s/article/9233498/Intel_ships_60_core_Xeon_Phi_processor ↩

52. Johan De Gelas (14 November 2012). "The Xeon Phi at work at TACC". AnandTech. Retrieved 12 December 2012. https://www.anandtech.com/show/6451/the-xeon-phi-at-work-at-tacc ↩

53. IntelPR (12 November 2012). "Intel Delivers New Architecture for Discovery with Intel Xeon Phi Coprocessors". Intel. Retrieved 12 December 2012. https://newsroom.intel.com/community/intel_newsroom/blog/2012/11/12/intel-delivers-new-architecture-for-discovery-with-intel-xeon-phi-coprocessors ↩

54. Agam Shah (12 November 2012). "Intel ships 60-core Xeon Phi processor". Computerworld. Archived from the original on 12 March 2013. Retrieved 12 December 2012. https://web.archive.org/web/20130312145710/http://www.computerworld.com/s/article/9233498/Intel_ships_60_core_Xeon_Phi_processor ↩

55. Johan De Gelas (14 November 2012). "The Xeon Phi at work at TACC". AnandTech. Retrieved 12 December 2012. https://www.anandtech.com/show/6451/the-xeon-phi-at-work-at-tacc ↩

56. IntelPR (12 November 2012). "Intel Delivers New Architecture for Discovery with Intel Xeon Phi Coprocessors". Intel. Retrieved 12 December 2012. https://newsroom.intel.com/community/intel_newsroom/blog/2012/11/12/intel-delivers-new-architecture-for-discovery-with-intel-xeon-phi-coprocessors ↩

57. Agam Shah (12 November 2012). "Intel ships 60-core Xeon Phi processor". Computerworld. Archived from the original on 12 March 2013. Retrieved 12 December 2012. https://web.archive.org/web/20130312145710/http://www.computerworld.com/s/article/9233498/Intel_ships_60_core_Xeon_Phi_processor ↩

58. Johan De Gelas (14 November 2012). "The Xeon Phi at work at TACC". AnandTech. Retrieved 12 December 2012. https://www.anandtech.com/show/6451/the-xeon-phi-at-work-at-tacc ↩

59. "TOP500 - June 2013". TOP500. Retrieved 18 June 2013. https://www.top500.org/lists/2013/06/ ↩

60. "Tianhe-2 (MilkyWay-2)". Top500.org. 14 November 2015. Retrieved 6 May 2016. https://top500.org/system/177999 ↩

61. Hruska, Joel (30 July 2012). "Intel's 50-core champion: In-depth on Xeon Phi". ExtremeTech. Ziff Davis, Inc. Retrieved 2 December 2012. https://www.extremetech.com/extreme/133541-intels-64-core-champion-in-depth-on-xeon-phi ↩

62. Gareth Halfacree (20 June 2011), "Intel pushes for HPC space with Knights Corner", thinq.co.uk, Net Communities Limited, UK http://www.thinq.co.uk/2011/6/20/intel-pushes-hpc-space-knights-corner/ ↩

63. Barker, J; Bowden, J (2013). "Manycore Parallelism through OpenMP". OpenMP in the Era of Low Power Devices and Accelerators. IWOMP. Lecture Notes in Computer Science, vol 8122. Vol. 8122. Springer. pp. 45–57. doi:10.1007/978-3-642-40698-0_4. ISBN 978-3-642-40697-3. 978-3-642-40697-3 ↩

64. Rick Merritt (20 June 2011), "OEMs show systems with Intel MIC chips", EE Times https://www.eetimes.com/electronics-news/4217092/OEMs-show-systems-with-Intel-MIC-chips ↩

65. Dokulil, Jiri; Bajrovic, Enes; Benkner, Siegfried; Pllana, Sabri; Sandrieser, Martin; Bachmayer, Beverly (23 November 2012), Efficient Hybrid Execution of C++ Applications using Intel Xeon Phi Coprocessor, arXiv:1211.5530, Bibcode:2012arXiv1211.5530D /wiki/ArXiv_(identifier) ↩

66. "News Fact Sheet: Intel Many Integrated Core (Intel MIC) Architecture ISC'11 Demos and Performance Description" (PDF), newsroom.intel.com, Intel, 20 June 2011, archived from the original (PDF) on 24 March 2012 https://web.archive.org/web/20120324101552/https://newsroom.intel.com/servlet/JiveServlet/download/2152-4-5220/ISC_Intel_MIC_factsheet.pdf ↩

67. Tesla vs. Xeon Phi vs. Radeon. A Compiler Writer's Perspective // The Portland Group (PGI), CUG 2013 Proceedings https://cug.org/proceedings/cug2013_proceedings/includes/files/pap199.pdf ↩

68. "Intel Many Integrated Core Architecture (Intel MIC Architecture) - RESOURCES (including downloads)". Intel. Retrieved 6 January 2014. https://software.intel.com/en-us/forums/showthread.php?t=105443 ↩

69. "Intel Xeon Phi Coprocessor Instruction Set Architecture Reference Manual" (PDF). Intel. 7 September 2012. Retrieved 6 January 2014. https://software.intel.com/sites/default/files/forum/278102/327364001en.pdf ↩

70. "Intel Developer Zone: Intel Xeon Phi Coprocessor". Intel. Archived from the original on 1 February 2014. Retrieved 6 January 2014. https://web.archive.org/web/20140201085819/https://software.intel.com/mic-developer ↩

71. "Intel® Intrinsics Guide". software.intel.com. Retrieved 4 August 2020. https://software.intel.com/sites/landingpage/IntrinsicsGuide/#techs=KNC ↩

72. "Intel SE3110X Xeon Phi 3110X Knights Corner 6GB Coprocessor-No Cooling -SabrePC.com -SabrePC.com". www.sabrepc.com. Archived from the original on 22 February 2017. Retrieved 22 February 2017. https://web.archive.org/web/20170222200102/https://www.sabrepc.com/intel-se3110x-xeon-phi-3110x-knights-corner-coprocessor.html ↩

73. "Intel Xeon Phi Coprocessor 3120A (6GB, 1.100 GHz, 57 core) Product Specifications". Intel ARK (Product Specs). Retrieved 22 February 2017. https://ark.intel.com/products/75797/Intel-Xeon-Phi-Coprocessor-3120A-6GB-1_100-GHz-57-core ↩

74. "Intel Xeon Phi Coprocessor 3120P (6GB, 1.100 GHz, 57 core) Product Specifications". Intel ARK (Product Specs). Retrieved 22 February 2017. https://ark.intel.com/products/75798/Intel-Xeon-Phi-Coprocessor-3120P-6GB-1_100-GHz-57-core ↩

75. "Intel Xeon Phi 31S1P - BC31S1P". www.cpu-world.com. Retrieved 21 April 2024. https://www.cpu-world.com/CPUs/Xeon_Phi/Intel-Xeon%20Phi%2031S1P.html ↩

76. "Intel Xeon Phi Coprocessor 5110P (8GB, 1.053 GHz, 60 core) Product Specifications". Intel ARK (Product Specs). Retrieved 22 February 2017. https://ark.intel.com/products/71992/Intel-Xeon-Phi-Coprocessor-5110P-8GB-1_053-GHz-60-core ↩

77. "Intel Xeon Phi Coprocessor 5120D (8GB, 1.053 GHz, 60 core) Product Specifications". Intel ARK (Product Specs). Retrieved 22 February 2017. https://ark.intel.com/products/75801/Intel-Xeon-Phi-Coprocessor-5120D-8GB-1_053-GHz-60-core ↩

78. "Intel Xeon Phi SE10P". www.cpu-world.com. Retrieved 21 April 2024. https://www.cpu-world.com/CPUs/Xeon_Phi/Intel-Xeon%20Phi%20SE10P.html ↩

79. "Intel Xeon Phi SE10X". www.cpu-world.com. Retrieved 21 April 2024. https://www.cpu-world.com/CPUs/Xeon_Phi/Intel-Xeon%20Phi%20SE10X.html ↩

80. "Intel SC7110P Xeon Phi 7110P Knights Corner Coprocessor -SabrePC.com -SabrePC.com". www.sabrepc.com. Retrieved 22 February 2017. https://www.sabrepc.com/intel-sc7110p-xeon-phi-7110p-knights-corner-coprocessor.html ↩

81. "Intel SC7110X Xeon Phi 7110X Knights Corner Coprocessor -SabrePC.com -SabrePC.com". www.sabrepc.com. Retrieved 22 February 2017. https://www.sabrepc.com/intel-sc7110x-xeon-phi-7110x-knights-corner-coprocessor.html ↩

82. "Intel Xeon Phi Coprocessor 7120A (16GB, 1.238 GHz, 61 core) Product Specifications". Intel ARK (Product Specs). Retrieved 22 February 2017. https://ark.intel.com/products/80555/Intel-Xeon-Phi-Coprocessor-7120A-16GB-1_238-GHz-61-core ↩

83. "Intel Xeon Phi Coprocessor 7120D (16GB, 1.238 GHz, 61 core) Product Specifications". Intel ARK (Product Specs). Retrieved 22 February 2017. https://ark.intel.com/products/80310/Intel-Xeon-Phi-Coprocessor-7120D-16GB-1_238-GHz-61-core ↩

84. "Intel Xeon Phi Coprocessor 7120P (16GB, 1.238 GHz, 61 core) Product Specifications". Intel ARK (Product Specs). Retrieved 22 February 2017. https://ark.intel.com/products/75799/Intel-Xeon-Phi-Coprocessor-7120P-16GB-1_238-GHz-61-core ↩

85. "Intel Xeon Phi Coprocessor 7120X (16GB, 1.238 GHz, 61 core) Product Specifications". Intel ARK (Product Specs). Retrieved 22 February 2017. https://ark.intel.com/products/75800/Intel-Xeon-Phi-Coprocessor-7120X-16GB-1_238-GHz-61-core ↩

86. "Stampede: A Comprehensive Petascale Computing Environment" (PDF). IEEE Cluster 2011 Special Topic. Archived from the original (PDF) on 26 September 2012. Retrieved 16 November 2011. https://www.webcitation.org/6AyMCTibp?url=http://www.ieeecluster.org/2011/images/program/Stampede_Abstracts.pdf ↩

87. "Intel Powers the World's Fastest Supercomputer, Reveals New and Future High Performance Computing Technologies". Retrieved 21 June 2013. https://newsroom.intel.com/community/intel_newsroom/blog/2013/06/17/intel-powers-the-worlds-fastest-supercomputer-reveals-new-and-future-high-performance-computing-technologies ↩

88. "Intel Xeon Phi 'Knights Landing' Features Integrated Memory With 500 GB/s Bandwidth and DDR4 Memory Support - Architecture Detailed". WCCFtech. 25 November 2013. Retrieved 27 August 2015. https://wccftech.com/intel-xeon-phi-knights-landing-features-integrated-memory-500-gbs-bandwidth-ddr4-memory-support-architecture-detailed/ ↩

89. Sebastian Anthony (26 November 2013), Intel unveils 72-core x86 Knights Landing CPU for exascale supercomputing, ExtremeTech https://www.extremetech.com/extreme/171678-intel-unveils-72-core-x86-knights-landing-cpu-for-exascale-supercomputing ↩

90. Tom's Hardware: Intel Xeon Phi Knights Landing Now Shipping; Omni Path Update, Too. 20 June 2016 https://www.tomshardware.com/news/intel-xeon-phi-knights-landing,32121.html ↩

91. James Reinders (23 July 2013), AVX-512 Instructions, Intel https://software.intel.com/en-us/blogs/2013/avx-512-instructions ↩

92. "Cori". www.nersc.gov. Archived from the original on 17 May 2019. Retrieved 14 November 2018. https://web.archive.org/web/20190517164940/https://www.nersc.gov/users/computational-systems/cori/ ↩

93. "2016 ISC High Performance: Intel's Rajeeb Hazra Delivers Keynote Address". Vimeo. https://vimeo.com/intelpr/review/171590720/0bb679ec36 ↩

94. Pradeep Dubey (20 June 2016). "How Intel Xeon Phi Processors Benefit Machine Learning/Deep Learning Apps and Frameworks". software.intel.com. https://software.intel.com/en-us/blogs/2016/06/20/how-xeon-phi-processors-benefit-machine-and-deep-learning-apps-frameworks ↩

95. "Introducing the Intel Xeon Phi Processor – Your Path to Deeper Insight". Intel. Archived from the original on 27 January 2017. https://web.archive.org/web/20170127023125/https://www.intel.com/content/www/us/en/processors/xeon/xeon-phi-detail.html ↩

96. "2016 ISC High Performance: Intel's Rajeeb Hazra Delivers Keynote Address". Vimeo. https://vimeo.com/intelpr/review/171590720/0bb679ec36 ↩

97. "Highlights - November 2016 | TOP500". top500.org. https://top500.org/lists/top500/2016/11/highlights/ ↩

98. Larabel, Michael (24 August 2017). "Intel Quietly Drops Xeon Phi 7200 Coprocessors". Phoronix. Retrieved 25 August 2017. https://www.phoronix.com/scan.php?page=news_item&px=No-More-Xeon-Phi-7200-Cards ↩

99. "Product Change Notification 116378 - 00" (PDF). Intel.com. Retrieved 25 July 2018. https://qdms.intel.com/dm/i.aspx/9C54A9A7-BF37-4496-B268-BD2746EA54D3/PCN116378-00.pdf ↩

100. "Intel Xeon Phi processor: Your Path to Deeper Insight" (PDF). Intel.com. Archived from the original (PDF) on 26 February 2017. Retrieved 25 February 2017. https://web.archive.org/web/20170226034124/https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/xeon-phi-processor-product-brief.pdf ↩

101. "Intel Xeon Phi 7220A - SC7220A / SC7220AEB". https://www.cpu-world.com/CPUs/Xeon_Phi/Intel-Xeon%20Phi%207220A.html ↩

102. "Intel Xeon Phi 7220P - SC7220P". https://www.cpu-world.com/CPUs/Xeon_Phi/Intel-Xeon%20Phi%207220P.html ↩

103. "Intel Xeon Phi 7240P - SC7240P". https://www.cpu-world.com/CPUs/Xeon_Phi/Intel-Xeon%20Phi%207240P.html ↩

104. "Intel Xeon Phi Processor 7210 (16GB, 1.30 GHz, 64 core) Product Specifications". Intel ARK (Product Specs). Retrieved 22 February 2017. https://ark.intel.com/products/94033/Intel-Xeon-Phi-Processor-7210-16GB-1_30-GHz-64-core ↩

105. "Intel Xeon Phi Processor 7210F (16GB, 1.30 GHz, 64 core) Product Specifications". Intel ARK (Product Specs). Retrieved 22 February 2017. https://ark.intel.com/products/94709/Intel-Xeon-Phi-Processor-7210F-16GB-1_30-GHz-64-core ↩

106. "Intel Xeon Phi Processor 7230 (16GB, 1.30 GHz, 64 core) Product Specifications". Intel ARK (Product Specs). Retrieved 22 February 2017. https://ark.intel.com/products/94034/Intel-Xeon-Phi-Processor-7230-16GB-1_30-GHz-64-core ↩

107. "Intel Xeon Phi Processor 7230F (16GB, 1.30 GHz, 64 core) Product Specifications". Intel ARK (Product Specs). Retrieved 22 February 2017. https://ark.intel.com/products/95828/Intel-Xeon-Phi-Processor-7230F-16GB-1_30-GHz-64-core ↩

108. "Intel Xeon Phi Processor 7250 (16GB, 1.40 GHz, 68 core) Product Specifications". Intel ARK (Product Specs). Retrieved 22 February 2017. https://ark.intel.com/products/94035/Intel-Xeon-Phi-Processor-7250-16GB-1_40-GHz-68-core ↩

109. "Intel Xeon Phi Processors". Intel. Retrieved 25 February 2017. https://www.intel.com/content/www/us/en/products/processors/xeon-phi/xeon-phi-processors.html ↩

110. "Intel Xeon Phi Processor 7250F (16GB, 1.40 GHz, 68 core) Product Specifications". Intel ARK (Product Specs). Retrieved 22 February 2017. https://ark.intel.com/products/95829/Intel-Xeon-Phi-Processor-7250F-16GB-1_40-GHz-68-core ↩

111. "Intel Xeon Phi Processor 7290 (16GB, 1.50 GHz, 72 core) Product Specifications". Intel ARK (Product Specs). Retrieved 22 February 2017. https://ark.intel.com/products/95830/Intel-Xeon-Phi-Processor-7290-16GB-1_50-GHz-72-core ↩

112. "Intel Xeon Phi Processor 7290F (16GB, 1.50 GHz, 72 core) Product Specifications". Intel ARK (Product Specs). Retrieved 22 February 2017. https://ark.intel.com/products/95831/Intel-Xeon-Phi-Processor-7290F-16GB-1_50-GHz-72-core ↩

113. Smith, Ryan (17 August 2016). "Intel Announces Knight's Mill: A Xeon Phi for Deep Learning". Anandtech. Retrieved 17 August 2016. https://www.anandtech.com/show/10575/intel-announces-knights-mill-a-xeon-phi-for-deep-learning ↩

114. Cutress, Ian (19 December 2017). "Intel Lists Knights Mill Xeon Phi on ARK: Up to 72 cores at 320W with QFMA and VNNI". Anandtech. Retrieved 19 December 2017. https://www.anandtech.com/show/12172/intel-lists-knights-mill-xeon-phi-on-ark-up-to-72-cores-at-320w-with-qfma-and-vnni ↩

115. SC14: Supercomputing '14; International Conference for High Performance Computing, Networking, Storage and Analysis in year 2014 ↩

116. Eric Gardner (25 November 2014), What public disclosures has Intel made about Knights Landing?, Intel Corporation, archived from the original on 23 February 2015 https://web.archive.org/web/20150223090350/https://software.intel.com/en-us/articles/what-disclosures-has-intel-made-about-knights-landing/ ↩

117. ALCF staff (9 April 2015), Introducing Aurora https://www.alcf.anl.gov/articles/introducing-aurora ↩

118. ALCF staff (9 April 2015), Aurora https://aurora.alcf.anl.gov/ ↩

119. Hemsoth, Nicole (23 May 2017). "Some Surprises in the 2018 DoE Budget for Supercomputing". Next Platform. Retrieved 13 November 2017. https://www.nextplatform.com/2017/05/23/surprises-2018-doe-budget-supercomputing/ ↩

120. Brueckner, Rich (16 June 2017). "Is Aurora Morphing into an Exascale AI Supercomputer?". Inside HPC. Retrieved 13 November 2017. https://insidehpc.com/2017/06/told-aurora-morphing-novel-architecture-ai-supercomputer/ ↩

121. Damkroger, Trish (13 November 2017). "Unleashing high performance computing today and tomorrow". Intel IT Peer Network. https://itpeernetwork.intel.com/unleashing-high-performance-computing/ ↩

122. Kampman, Jeff (13 November 2017). "Intel quietly kills off next-gen Knights Hill Xeon Phi chips". Tech Report. Retrieved 13 November 2017. https://techreport.com/news/32829/intel-quietly-kills-off-next-gen-knights-hill-xeon-phi-chips ↩

123. Fang, Jianbin; Sips, Henk; Zhang, Lilun; Xu, Chuanfu; Yonggang, Che; Varbanescu, Ana Lucia (2014). Test-Driving Intel Xeon Phi (PDF). 2014 ACM/SPEC International Conference on Performance Engineering. Archived from the original (PDF) on 11 November 2017. Retrieved 30 December 2013. https://web.archive.org/web/20171111044329/https://research.spec.org/icpe_proceedings/2014/p137.pdf ↩

124. Memeti, Suejb; Pllana, Sabri; Benkner, Siegfried; Pllana, Sabri; Sandrieser, Martin; Bachmayer, Beverly (29 June 2015), Accelerating DNA Sequence Analysis using Intel Xeon Phi, arXiv:1506.08612, Bibcode:2015arXiv150608612M /wiki/ArXiv_(identifier) ↩

125. Viebke, Andre; Pllana, Sabri; Benkner, Siegfried; Pllana, Sabri; Sandrieser, Martin; Bachmayer, Beverly (30 June 2015), The Potential of the Intel Xeon Phi for Supervised Deep Learning, arXiv:1506.09067, Bibcode:2015arXiv150609067V /wiki/ArXiv_(identifier) ↩

126. Jon Stokes (20 June 2011). "Intel takes wraps off 50-core supercomputing processor plans". Ars Technica. https://arstechnica.com/business/news/2011/06/intel-takes-wraps-off-of-50-core-supercomputing-coprocessor-plans.ars ↩

127. Johan De Gelas (11 September 2012). "Intel's Xeon Phi in 10 Petaflops supercomputer". AnandTech. Retrieved 12 December 2012. https://www.anandtech.com/show/6265/intels-xeon-phi-in-10-petaflops-supercomputer ↩

128. Johan De Gelas (11 September 2012). "Intel's Xeon Phi in 10 Petaflops supercomputer". AnandTech. Retrieved 12 December 2012. https://www.anandtech.com/show/6265/intels-xeon-phi-in-10-petaflops-supercomputer ↩