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Memory hierarchy
Computer architecture that classifies memory/storage into a hierarchy based on response time

In computer architecture, the memory hierarchy separates computer storage into a hierarchy based on response time. Since response time, complexity, and capacity are related, the levels may also be distinguished by their performance and controlling technologies. Memory hierarchy affects performance in computer architectural design, algorithm predictions, and lower level programming constructs involving locality of reference.

Designing for high performance requires considering the restrictions of the memory hierarchy, i.e. the size and capabilities of each component. Each of the various components can be viewed as part of a hierarchy of memories (m1, m2, ..., mn) in which each member mi is typically smaller and faster than the next highest member mi+1 of the hierarchy. To limit waiting by higher levels, a lower level will respond by filling a buffer and then signaling for activating the transfer.

There are four major storage levels.

  • Internal – processor registers and cache.
  • Main – the system RAM and controller cards.
  • On-line mass storage – secondary storage.
  • Off-line bulk storage – tertiary and off-line storage.

This is a general memory hierarchy structuring. Many other structures are useful. For example, a paging algorithm may be considered as a level for virtual memory when designing a computer architecture, and one can include a level of nearline storage between online and offline storage.

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Properties of the technologies in the memory hierarchy

  • Adding complexity slows the memory hierarchy.3
  • CMOx memory technology stretches the flash space in the memory hierarchy4
  • One of the main ways to increase system performance is minimising how far down the memory hierarchy one has to go to manipulate data.5
  • Latency and bandwidth are two metrics associated with caches. Neither of them is uniform, but is specific to a particular component of the memory hierarchy.6
  • Predicting where in the memory hierarchy the data resides is difficult.7
  • The location in the memory hierarchy dictates the time required for the prefetch to occur.8

Examples

The number of levels in the memory hierarchy and the performance at each level has increased over time. The type of memory or storage components also change historically.9 For example, the memory hierarchy of an Intel Haswell Mobile10 processor circa 2013 is:

  • Processor registers – the fastest possible access (usually 1 CPU cycle). A few thousand bytes in size.
  • Cache
    • Level 0 (L0), micro-operations cache – 6,144 bytes (6 KiB[original research])11 in size
    • Level 1 (L1) instruction cache – 128 KiB[original research] in size
    • Level 1 (L1) data cache – 128 KiB[original research] in size. Best access speed is around 700 GB/s.12
    • Level 2 (L2) instruction and data (shared) – 1 MiB[original research] in size. Best access speed is around 200 GB/s.13
    • Level 3 (L3) shared cache – 6 MiB[original research] in size. Best access speed is around 100 GB/s.14
    • Level 4 (L4) shared cache – 128 MiB[original research] in size. Best access speed is around 40 GB/s.15
  • Main memory (primary storage) – GiB[original research] in size. Best access speed is around 10 GB/s.16 In the case of a NUMA machine, access times may not be uniform.
  • Mass storage (secondary storage) – terabytes in size. As of 2017[update], best access speed is from a consumer solid state drive is about 2000 MB/s.17
  • Nearline storage (tertiary storage) – up to exabytes in size. As of 2013[update], best access speed is about 160 MB/s.18
  • Offline storage

The lower levels of the hierarchy – from mass storage downwards – are also known as tiered storage. The formal distinction between online, nearline, and offline storage is:19

  • Online storage is immediately available for I/O.
  • Nearline storage is not immediately available, but can be made online quickly without human intervention.
  • Offline storage is not immediately available, and requires some human intervention to bring online.

For example, always-on spinning disks are online, while spinning disks that spin down, such as massive arrays of idle disk (MAID), are nearline. Removable media such as tape cartridges that can be automatically loaded, as in a tape library, are nearline, while cartridges that must be manually loaded are offline.

Most modern CPUs are so fast that, for most program workloads, the bottleneck is the locality of reference of memory accesses and the efficiency of the caching and memory transfer between different levels of the hierarchy. As a result, the CPU spends much of its time idling, waiting for memory I/O to complete. This is sometimes called the space cost, as a larger memory object is more likely to overflow a small and fast level and require use of a larger, slower level. The resulting load on memory use is known as pressure (respectively register pressure, cache pressure, and (main) memory pressure). Terms for data being missing from a higher level and needing to be fetched from a lower level are, respectively: register spilling (due to register pressure: register to cache), cache miss (cache to main memory), and (hard) page fault (real main memory to virtual memory, i.e. mass storage, commonly referred to as disk regardless of the actual mass storage technology used).

Modern programming languages mainly assume two levels of memory, main (working) memory and mass storage, though in assembly language and inline assemblers in languages such as C, registers can be directly accessed. Taking optimal advantage of the memory hierarchy requires the cooperation of programmers, hardware, and compilers (as well as underlying support from the operating system):

  • Programmers are responsible for moving data between disk and memory through file I/O.
  • Hardware is responsible for moving data between memory and caches.
  • Optimizing compilers are responsible for generating code that, when executed, will cause the hardware to use caches and registers efficiently.

Many programmers assume one level of memory. This works fine until the application hits a performance wall. Then the memory hierarchy will be assessed during code refactoring.

See also

References

  1. Toy, Wing; Zee, Benjamin (1986). Computer Hardware/Software Architecture. Prentice Hall. p. 30. ISBN 0-13-163502-6. 0-13-163502-6 ↩

  2. Toy, Wing; Zee, Benjamin (1986). Computer Hardware/Software Architecture. Prentice Hall. p. 30. ISBN 0-13-163502-6. 0-13-163502-6 ↩

  3. Write-combining /wiki/Write-combining ↩

  4. "Memory Hierarchy". Unitity Semiconductor Corporation. Archived from the original on 5 August 2009. Retrieved 16 September 2009. https://web.archive.org/web/20090805170055/http://www.unitysemi.com/applications-memory-hierarchy.html ↩

  5. Pádraig Brady. "Multi-Core". Retrieved 16 September 2009. http://www.pixelbeat.org/docs/memory_hierarchy/ ↩

  6. van der Pas, Ruud (2002). "Memory Hierarchy in Cache-Based Systems" (PDF). Santa Clara, California: Sun Microsystems: 26. 817-0742-10. {{cite journal}}: Cite journal requires |journal= (help) http://www.sun.com/blueprints/1102/817-0742.pdf ↩

  7. van der Pas, Ruud (2002). "Memory Hierarchy in Cache-Based Systems" (PDF). Santa Clara, California: Sun Microsystems: 26. 817-0742-10. {{cite journal}}: Cite journal requires |journal= (help) http://www.sun.com/blueprints/1102/817-0742.pdf ↩

  8. van der Pas, Ruud (2002). "Memory Hierarchy in Cache-Based Systems" (PDF). Santa Clara, California: Sun Microsystems: 26. 817-0742-10. {{cite journal}}: Cite journal requires |journal= (help) http://www.sun.com/blueprints/1102/817-0742.pdf ↩

  9. "Memory & Storage – Timeline of Computer History – Computer History Museum". www.computerhistory.org. http://www.computerhistory.org/timeline/memory-storage/ ↩

  10. Crothers, Brooke. "Dissecting Intel's top graphics in Apple's 15-inch MacBook Pro – CNET". News.cnet.com. Retrieved 2014-07-31. http://news.cnet.com/8301-13579_3-57609045-37/dissecting-intels-top-graphics-in-apples-15-inch-macbook-pro/ ↩

  11. "Intel's Haswell Architecture Analyzed: Building a New PC and a New Intel". AnandTech. Retrieved 2014-07-31. http://www.anandtech.com/show/6355/intels-haswell-architecture/6 ↩

  12. "SiSoftware Zone". Sisoftware.co.uk. Archived from the original on 2014-09-13. Retrieved 2014-07-31. https://web.archive.org/web/20140913231938/http://www.sisoftware.co.uk/?d=qa&f=mem_hsw ↩

  13. "SiSoftware Zone". Sisoftware.co.uk. Archived from the original on 2014-09-13. Retrieved 2014-07-31. https://web.archive.org/web/20140913231938/http://www.sisoftware.co.uk/?d=qa&f=mem_hsw ↩

  14. "SiSoftware Zone". Sisoftware.co.uk. Archived from the original on 2014-09-13. Retrieved 2014-07-31. https://web.archive.org/web/20140913231938/http://www.sisoftware.co.uk/?d=qa&f=mem_hsw ↩

  15. "SiSoftware Zone". Sisoftware.co.uk. Archived from the original on 2014-09-13. Retrieved 2014-07-31. https://web.archive.org/web/20140913231938/http://www.sisoftware.co.uk/?d=qa&f=mem_hsw ↩

  16. "SiSoftware Zone". Sisoftware.co.uk. Archived from the original on 2014-09-13. Retrieved 2014-07-31. https://web.archive.org/web/20140913231938/http://www.sisoftware.co.uk/?d=qa&f=mem_hsw ↩

  17. "Samsung 960 Pro M.2 NVMe SSD Review". storagereview.com. 20 October 2016. Retrieved 2017-04-13. http://www.storagereview.com/samsung_960_pro_m2_nvme_ssd_review ↩

  18. "Ultrium – LTO Technology – Ultrium GenerationsLTO". Lto.org. Archived from the original on 2011-07-27. Retrieved 2014-07-31. https://web.archive.org/web/20110727052050/http://www.lto.org/technology/generations.html ↩

  19. Pearson, Tony (2010). "Correct use of the term Nearline". IBM Developerworks, Inside System Storage. Archived from the original on 2018-11-27. Retrieved 2015-08-16. https://web.archive.org/web/20181127020712/https://www.ibm.com/developerworks/community/blogs/InsideSystemStorage/entry/the_correct_use_of_the_term_nearline2?lang=en ↩