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Technology

• Cache line block on L2/L3 cache was reduced from 128 bytes in NetBurst & Merom/Penryn to 64 bytes per line in this generation (same size as Yonah and Pentium M).
• Hyper-threading reintroduced.
• Intel Turbo Boost 1.0.⁶
• 2–24 MiB L3 cache with Smart Cache in some models.
• Instruction Fetch Unit (IFU) containing second-level branch predictor with two level Branch Target Buffer (BTB) and Return Stack Buffer (RSB). Nehalem also supports all predictor types previously used in Intel's processors like Indirect Predictor and Loop Detector.⁷
• sTLB (second level unified translation lookaside buffer) (i.e. both instructions and data) that contains 512 entries for small pages only, and is again 4 way associative.⁸
• 3 integer ALU, 2 vector ALU and 2 AGU per core.⁹
• Native (all processor cores on a single die) quad- , hex-, and octa-core processors
• Intel QuickPath Interconnect in HEDT, server, and workstation models and Direct Media Interface on other models replacing the legacy front side bus.
• 64 KB L1 cache per core (32 KB L1 data and 32 KB L1 instruction), and 256 KB L2 cache per core.
• Integration of PCI Express and DMI into the processor in mid-range models, replacing the northbridge.
• Integrated memory controller supporting two or three memory channels of DDR3 SDRAM or four FB-DIMM2 channels.
• Second-generation Intel Virtualization Technology, which introduced Extended Page Table support, virtual processor identifiers (VPIDs), and non-maskable interrupt-window exiting. ¹⁰
• SSE4.2 and POPCNT instructions.
• Macro-op fusion now works in 64-bit mode.
• 20 to 24 pipeline stages.¹¹

Performance and power improvements

It has been reported that Nehalem has a focus on performance, thus the increased core size.¹³ Compared to Penryn, Nehalem has:

• 10–25% better single-threaded performance / 20–100% better multithreaded performance at the same power level
• 30% lower power consumption for the same performance
• On average, Nehalem provides a 15–20% clock-for-clock increase in performance per core.

Overclocking is possible with Bloomfield processors and the X58 chipset. Lynnfield processors use a PCH removing the need for a northbridge.¹⁴

Nehalem processors incorporate SSE4.2 SIMD instructions, adding seven new instructions to the SSE 4.1 set in the Core 2 series. The Nehalem architecture reduces atomic operation latency by 50% in an attempt to eliminate overhead on atomic operations such as the LOCK CMPXCHG compare-and-swap instruction.¹⁵

Variants

• Lynnfield processors feature 16 PCIe lanes, which can be used in 1x16 or 2x8 configuration.
• 1 6500 series scalable up to 2 sockets, 7500 series scalable up to 4/8 sockets.¹⁷

Server, workstation, and desktop processors

Main articles: List of Intel Core processors and List of Intel Xeon processors (Nehalem-based)

• Intel states the Gainestown processors have six memory channels. Gainestown processors have dual QPI links and have a separate set of memory registers for each link in effect, a multiplexed six-channel system.³⁴³⁵

Mobile processors

Main article: List of Intel Core i7 processors

See also

• List of Intel CPU microarchitectures
• Tick–tock model

Further reading

• InfoWorld review: Intel's Westmere struts its stuff, InfoWorld, March 16, 2010
• IDF: Intel Clarkdale Up Close and Personal, X-bit Labs, September 24, 2009, archived from the original on March 8, 2011
• Intel Core i7 Processors: Nehalem and X58 Have Arrived, Hot Hardware, November 3, 2008, archived from the original on March 6, 2009, retrieved June 10, 2009
• Intel Core i7 CPU & Nehalem Architecture Review, hardCOREware.net, November 3, 2008, archived from the original on November 6, 2008
• Intel Nehalem Core i7 Series Complete Review, PC Perspective, November 3, 2008, archived from the original on November 6, 2008, retrieved November 3, 2008
• Intel Nehalem Core i7 940 Review, Xtreview, October 1, 2008
• Altavilla, Dave (March 17, 2008), Intel Showcases Dunnington, Nehalem and Larrabee Processors, HotHardware, archived from the original on May 23, 2012, retrieved March 26, 2008
• Shrout, Ryan (March 28, 2008), Intel Slides and Nehalem architecture information, PC Perspective, archived from the original on May 14, 2010, retrieved April 23, 2007
• Stokes, Jon (March 28, 2007), Intel drops a Nehalem bomb on AMD's Fusion: integrated graphics, on-die memory controller, SMT, Ars Technica
• Lal Shimpi, Anand (September 18, 2007), Nehalem: Single die, 8-cores, 731M transistors, AnandTech
• Lal Shimpi, Anand (November 3, 2008), Nehalem - Everything You Need to Know about Intel's New Architecture, AnandTech
• David Kanter (April 4, 2010). "Inside Nehalem: Intel's Future Processor and System". realworldtech.com. Retrieved December 16, 2010.
• Holland, Maggie (September 19, 2007), IDF 2007: Intel debuts Nehalem, IT Pro, archived from the original on October 18, 2007
• Everything we know about Nehalem (in Spanish), CHW.net, January 5, 2008, archived from the original on July 5, 2008
• Stokes, Jon (April 9, 2008), What you need to know about Intel's Nehalem CPU, Ars Technica
• Torres, Gabriel (March 17, 2008), Details on the Forthcoming Intel Nehalem Processor, Hardware Secrets, archived from the original on May 16, 2008
• Shimpi, Anand Lal (June 5, 2008), The Nehalem Preview: Intel Does It Again, AnandTech
• Shimpi, Anand Lal (August 21, 2008), Nehalem – Everything You Need to Know about Intel's New Architecture, AnandTech
• First Look at Nehalem Microarchitecture, X-bit Labs, November 2, 2008, archived from the original on November 6, 2008

External links

• Nehalem processor at Intel.com

References

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