OR-AND-invert gates, or OAI-gates, are logic gates comprising OR gates followed by a NAND gate. They can be efficiently implemented in logic families like CMOS and TTL. They are dual to AND-OR-invert gates.
Overview
OR-AND-invert gates implement the inverted product of sums. n {\displaystyle n} groups of m i {\displaystyle m_{i}} , m i ≥ 1 , i = 1 … n {\displaystyle m_{i}\geq 1,i=1\ldots n} input signals combined with OR, and the results then combined with NAND.
Examples
2-1 OAI-gate
A 2-1-OAI gate realizes the following function:
Y = ( A ∨ B ) ∧ C ¯ {\displaystyle Y={\overline {(A\lor B)\land C}}}| Truth table 2-1 OAI | |||
| InputA B C | Output Y | ||
| 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 0 |
2-2 OAI gate
A 2-2-OAI gate realizes the following function:
Y = ( A ∨ B ) ∧ ( C ∨ D ) ¯ {\displaystyle Y={\overline {(A\lor B)\land (C\lor D)}}}| Truth table 2-2 OAI | ||||
| INPUTA B C D | OUTPUT Q | |||
| 0 | 0 | 0 | 0 | 1 |
| 0 | 0 | 0 | 1 | 1 |
| 0 | 0 | 1 | 0 | 1 |
| 0 | 0 | 1 | 1 | 1 |
| 0 | 1 | 0 | 0 | 1 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 |
| 0 | 1 | 1 | 1 | 0 |
| 1 | 0 | 0 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 0 |
| 1 | 0 | 1 | 1 | 0 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 |
| 1 | 1 | 1 | 1 | 0 |
Realization
OAI-gates can efficiently be implemented as complex gates. An example of a 3-1 OAI-gate is shown in the figure below.1
Examples of use
One possibility of implementing an XOR gate is by using a 2-2-OAI-gate with non-inverted and inverted inputs. 2
References
Hendrichs, Norman. "CMOS OAI31 or-and-invert complex gate". University of Hamburg. Retrieved 2024-02-12. https://tams.informatik.uni-hamburg.de/applets/hades/webdemos/05-switched/40-cmos/oai31.html ↩
Fischer, P. "Aussagenlogik und Gatter" (PDF). University of Heidelberg. Retrieved 2024-01-21. https://sus.ziti.uni-heidelberg.de/Lehre/WS1617_DST/DST_Fischer_03_Logik_Gatter.pptx.pdf ↩