Serial concatenated convolutional codes (SCCCs) are a type of forward error correction codes well-suited for turbo (iterative) decoding, where data encoded with an SCCC can be recovered from errors introduced by noisy channels through repeated decoding and interleaving. SCCCs combine an inner code, an outer code, and a linking interleaver, with the inner code typically being a recursive convolutional code, which provides crucial interleaver gain and enhances performance. Developed from research at NASA's Jet Propulsion Laboratory in the 1990s following the discovery of turbo codes, SCCCs offer competitive error correction with reasonable complexity. While not widely adopted commercially, SCCCs influenced standards like DVB-S2 and advanced understanding of iterative codes including turbo and LDPC codes.
History
Serial concatenated convolutional codes were first analyzed with a view toward turbo decoding in "Serial Concatenation of Interleaved Codes: Performance Analysis, Design, and Iterative Decoding" by S. Benedetto, D. Divsalar, G. Montorsi and F. Pollara.4 This analysis yielded a set of observations for designing high performance, turbo decodable serial concatenated codes that resembled turbo codes. One of these observations was that "the use of a recursive convolutional inner encoder always yields an interleaver gain." This is in contrast to the use of block codes or non-recursive convolutional codes, which do not provide comparable interleaver gain.
Additional analysis of SCCCs was done in "Coding Theorems for 'Turbo-Like' Codes" by D. Divsalar, Hui Jin, and Robert J. McEliece.5 This paper analyzed repeat-accumulate (RA) codes which are the serial concatenation of an inner two-state recursive convolutional code (also called an 'accumulator' or parity-check code) with a simple repeat code as the outer code, with both codes linked by an interleaver. The performance of the RA codes is quite good considering the simplicity of the constituent codes themselves.
SCCC codes were further analyzed in "Serial Turbo Trellis Coded Modulation with Rate-1 Inner Code".6 In this paper SCCCs were designed for use with higher order modulation schemes. Excellent performing codes with inner and outer constituent convolutional codes of only two or four states were presented.
Example Encoder
Fig 1 is an example of a SCCC.
The example encoder is composed of a 16-state outer convolutional code and a 2-state inner convolutional code linked by an interleaver. The natural code rate of the configuration shown is 1/4, however, the inner and/or outer codes may be punctured to achieve higher code rates as needed. For example, an overall code rate of 1/2 may be achieved by puncturing the outer convolutional code to rate 3/4 and the inner convolutional code to rate 2/3.
A recursive inner convolutional code is preferable for turbo decoding of the SCCC. The inner code may be punctured to a rate as high as 1/1 with reasonable performance.
Example Decoder
An example of an iterative SCCC decoder.
The SCCC decoder includes two soft-in-soft-out (SISO) decoders and an interleaver. While shown as separate units, the two SISO decoders may share all or part of their circuitry. The SISO decoding may be done is serial or parallel fashion, or some combination thereof. The SISO decoding is typically done using Maximum a posteriori (MAP) decoders using the BCJR algorithm.
Performance
SCCCs provide performance comparable to other iteratively decodable codes including turbo codes and LDPC codes. They are noted for having slightly worse performance at lower SNR environments (i.e. worse waterfall region), but slightly better performance at higher SNR environments (i.e. lower error floor).
See also
- Convolutional code
- Viterbi algorithm
- Soft-decision decoding
- Interleaver
- BCJR algorithm
- Low-density parity-check code
- Repeat-accumulate code
- Turbo equalizer
External links
- Forney, Dave (2009). "Concatenated codes". Scholarpedia. 4 (2): 8374. Bibcode:2009SchpJ...4.8374F. doi:10.4249/scholarpedia.8374.
- Ryan, Willian E. (2001). "Concatenated Convolutional Codes and Iterative Decoding" (PDF). Department of Electrical & Computer Engineering, University of Arizona.
References
Minoli, Daniel (2008). "5 Error Correction Techniques §5.1.4 Turbo Codes". Satellite Systems Engineering in an IPv6 Environment. CRC Press. pp. 152–. ISBN 9781420078695. Retrieved 4 June 2014. 9781420078695 ↩
Ryan, William; Lin, Shu (2009). "7.3 Serial-Concatenated Convolutional Codes". Channel Codes: Classical and Modern. Cambridge University Press. pp. 320–. ISBN 9781139483018. Retrieved 4 June 2014. 9781139483018 ↩
US Expired 6023783, Dariush Divsalar & Fabrizio Pollara, "Hybrid concatenated codes and iterative decoding", issued 2000-02-08 https://www.google.com/patents/US6023783 ↩
Benedetto, S.; Divsalar, D.; Montorsi, G.; Pollara, F. (August 15, 1996). "Serial Concatenation of Interleaved Codes: Performance Analysis, Design, and Iterative Decoding" (PDF). TDA Progress Report 42-126. Archived from the original (PDF) on 2017-08-13. Retrieved 2014-04-02. https://web.archive.org/web/20170813054421/http://www.systems.caltech.edu/EE/Courses/EE127/EE127C/handout/serial.pdf ↩
Divsalar, Dariush; Jin, Hui; McEliece, Robert J. (1998). "Coding Theorems for "Turbo-Like" Codes" (PDF). Jet Propulsion Laboratory, California Institute of Technology. Retrieved 2014-06-04. http://www.mif.vu.lt/~skersys/vsd/turbo/Allerton98.pdf ↩
Divsalar, D.; Dolinar, S.; Pollara, E (2000). "Serial Turbo Trellis Coded Modulation with Rate-1 Inner Code" (PDF). Globecom '00 - IEEE. Global Telecommunications Conference. doi:10.1109/GLOCOM.2000.891245. ISBN 0-7803-6451-1. Archived from the original (PDF) on 2010-05-29. 0-7803-6451-1 ↩