A multi-cycle processor is a processor that carries out one instruction over multiple clock cycles, often without starting up a new instruction in that time (as opposed to a pipelined processor).
See also
- Single-cycle processor, a processor executing (and finishing) one instruction per clock cycle
References
Harris (2016). Digital Design and Computer Architecture ARM Edition. Elsevier. sec. 7.3-7.5. ISBN 978-0-12-800056-4. 978-0-12-800056-4 ↩
"Multi-cycle MIPS Processor" (PDF). System Security Group, ETH Zurich. Zürich, Switzerland: ETH Zurich. https://syssec.ethz.ch/content/dam/ethz/special-interest/infk/inst-infsec/system-security-group-dam/education/Digitaltechnik_14/21_Architecture_MultiCycle.pdf ↩
"Lecture 9: Processor design – multi cycle" (PDF). School of Informatics :The University of Edinburgh. Edinburgh , Scotland: University of Edinburgh. Archived (PDF) from the original on 2017-08-08. Retrieved 2020-07-20. https://www.inf.ed.ac.uk/teaching/courses/inf2c-cs/13-14/lectures/lec09-slides.pdf ↩
"ESE 545: Computer Architecture: Designing a Multicycle Processor" (PDF). Electrical and Computer Engineering - Stony Brook University. Stony Brook, New York: Stony Brook University. Archived (PDF) from the original on 2018-05-16. Retrieved 2020-07-20. http://www.ece.sunysb.edu/~midor/ESE545/CA_Multicycle%20processor%20design.pdf ↩