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FLAGS register
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<h2 id="flags">FLAGS</h2> <table><tbody><tr><th colspan="7">Intel x86 FLAGS register<a class="footnote-ref" id="fnref:1" href="#fn:1"><sup>1</sup></a></th></tr><tr><th>Bit #</th><th>Mask</th><th>Abbreviation</th><th>Description</th><th>Category</th><th>=1</th><th>=0</th></tr><tr><th colspan="7">FLAGS</th></tr><tr><td>0</td><td>0x0001</td><td>CF</td><td><a href="/facts/Carry_flag/fjHdYBld">Carry flag</a></td><td>Status</td><td>CY (Carry)</td><td>NC (No Carry)</td></tr><tr><td>1</td><td>0x0002</td><td>—</td><td>Reserved, always 1 in EFLAGS<a class="footnote-ref" id="fnref:2" href="#fn:2"><sup>2</sup></a><a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a></td><td>—</td></tr><tr><td>2</td><td>0x0004</td><td>PF</td><td><a href="/facts/Parity_flag/2bP7x318">Parity flag</a></td><td>Status</td><td>PE (Parity Even)</td><td>PO (Parity Odd)</td></tr><tr><td>3</td><td>0x0008</td><td>—</td><td>Reserved<a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a></td><td>—</td></tr><tr><td>4</td><td>0x0010</td><td>AF</td><td><a href="/facts/Half-carry_flag/M2gxsbg9">Auxiliary Carry flag</a><a class="footnote-ref" id="fnref:5" href="#fn:5"><sup>5</sup></a></td><td>Status</td><td>AC (Auxiliary Carry)</td><td>NA (No Auxiliary Carry)</td></tr><tr><td>5</td><td>0x0020</td><td>—</td><td>Reserved<a class="footnote-ref" id="fnref:6" href="#fn:6"><sup>6</sup></a></td><td>—</td></tr><tr><td>6</td><td>0x0040</td><td>ZF</td><td><a href="/facts/Zero_flag/HSE5Ttls">Zero flag</a></td><td>Status</td><td>ZR (Zero)</td><td>NZ (Not Zero)</td></tr><tr><td>7</td><td>0x0080</td><td>SF</td><td><a href="/facts/Sign_flag/k5Efe9hJ">Sign flag</a></td><td>Status</td><td>NG (Negative)</td><td>PL (Positive)</td></tr><tr><td>8</td><td>0x0100</td><td>TF</td><td><a href="/facts/Trap_flag/oJID8rXg">Trap flag</a> (single step)</td><td>Control</td></tr><tr><td>9</td><td>0x0200</td><td>IF</td><td><a href="/facts/IF_(x86_flag)/97Wj40MR">Interrupt enable flag</a></td><td>Control</td><td>EI (Enable Interrupt)</td><td>DI (Disable Interrupt)</td></tr><tr><td>10</td><td>0x0400</td><td>DF</td><td><a href="/facts/Direction_flag/UGUrFGQE">Direction flag</a></td><td>Control</td><td>DN (Down)</td><td>UP (Up)</td></tr><tr><td>11</td><td>0x0800</td><td>OF</td><td><a href="/facts/Overflow_flag/nrUFjlQj">Overflow flag</a></td><td>Status</td><td>OV (Overflow)</td><td>NV (Not Overflow)</td></tr><tr><td>12–13</td><td>0x3000</td><td>IOPL</td><td><a href="/facts/IOPL/27y4kjHs">I/O privilege level</a> (286+ only), always all-1s on 8086 and 186</td><td>System</td></tr><tr><td>14</td><td>0x4000</td><td>NT</td><td>Nested task flag (286+ only), always 1 on 8086 and 186</td><td>System</td></tr><tr><td>15</td><td>0x8000</td><td>MD</td><td>Mode flag (<a href="/facts/NEC_V20/gUVUbklA">NEC V-series</a> only),<a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a>reserved on all Intel CPUs.Always 1 on 8086/186, 0 on 286 and later.</td><td>Control</td><td>(NEC only)Native Mode(<a href="/facts/Intel_80186/jUjWLMEX">186</a> compatible)</td><td>(NEC only)Emulation Mode(<a href="/facts/Intel_8080/32FvNTcD">8080</a> compatible)</td></tr><tr><th colspan="7">EFLAGS</th></tr><tr><td>16</td><td>0x0001 0000</td><td>RF</td><td>Resume flag (386+ only)</td><td>System</td></tr><tr><td>17</td><td>0x0002 0000</td><td>VM</td><td><a href="/facts/Virtual_8086_mode/f4fjXWdU">Virtual 8086 mode</a> flag (386+ only)</td><td>System</td></tr><tr><td>18</td><td>0x0004 0000</td><td>AC</td><td>Alignment Check (486+, ring 3),<a href="/facts/Supervisor_Mode_Access_Prevention/H8RSCNy2">SMAP</a> Access Check (<a href="/facts/Broadwell_(microarchitecture)/32jqNWRS">Broadwell</a>+, ring 0-2)</td><td>System</td></tr><tr><td>19</td><td>0x0008 0000</td><td>VIF</td><td><a href="/facts/Virtual_8086_mode/f4fjXWdU">Virtual interrupt flag</a> (Pentium+)</td><td>System</td></tr><tr><td>20</td><td>0x0010 0000</td><td>VIP</td><td><a href="/facts/Virtual_8086_mode/f4fjXWdU">Virtual interrupt pending</a> (Pentium+)</td><td>System</td></tr><tr><td>21</td><td>0x0020 0000</td><td>ID</td><td>Able to use <a href="/facts/CPUID/BdbdpdgB">CPUID</a> instruction (Pentium+)</td><td>System</td></tr><tr><td>22–29</td><td>0x3FC0 0000</td><td>—</td><td>Reserved</td><td>—</td></tr><tr><td>30</td><td>0x4000 0000</td><td>(none)</td><td>AES key schedule loaded flag<a class="footnote-ref" id="fnref:8" href="#fn:8"><sup>8</sup></a>(CPUs with <a href="/facts/VIA_PadLock/GtR3rG4z">VIA PadLock</a> only)</td><td>System</td></tr><tr><td>31</td><td>0x8000 0000</td><td>AI</td><td><a href="/facts/Alternate_Instruction_Set/oEgD3PFV">Alternate Instruction Set</a> enabled(<a href="/facts/VIA_C3/Y4IQ8VCd">VIA C5XL</a> processors only)<a class="footnote-ref" id="fnref:9" href="#fn:9"><sup>9</sup></a></td><td>System</td></tr><tr><th colspan="7">RFLAGS</th></tr><tr><td>32‑63</td><td>0xFFFF FFFF… …0000 0000</td><td>—</td><td>Reserved</td><td>—</td></tr></tbody></table> <p>Note: The mask column in the table is the AND <a href="/facts/Bitmask/d9Cu1A1Y">bitmask</a> (as <a href="/facts/Hexadecimal/02ohQW22">hexadecimal</a> value) to query the flag(s) within FLAGS register value. </p> <h2 id="usage">Usage</h2> <p>All FLAGS registers contain the <a href="/facts/Condition_code_register/7KMY9LR9">condition codes</a>, flag bits that let the results of one <a href="/facts/Machine_language/bgdQ1Fxf">machine-language</a> instruction affect another instruction. Arithmetic and logical instructions set some or all of the flags, and conditional jump instructions take variable action based on the value of certain flags. For example, jz (Jump if Zero), jc (Jump if Carry), and jo (Jump if Overflow) depend on specific flags. Other conditional jumps test combinations of several flags. </p><p>FLAGS registers can be moved from or to the stack. This is part of the job of saving and restoring CPU context, against a routine such as an interrupt service routine whose changes to registers should not be seen by the calling code. Here are the relevant instructions: </p> <ul><li>The PUSHF and POPF instructions transfer the 16-bit FLAGS register.</li> <li>PUSHFD/POPFD (introduced with the <a href="/facts/I386/ag5eSgWv">i386</a> architecture) transfer the 32-bit double register EFLAGS.</li> <li>PUSHFQ/POPFQ (introduced with the <a href="/facts/X86-64/cyWvUFlP">x86-64</a> architecture) transfer the 64-bit quadword register RFLAGS.</li></ul> <p>In 64-bit mode, PUSHF/POPF and PUSHFQ/POPFQ are available but PUSHFD/POPFD are not.<a class="footnote-ref" id="fnref:10" href="#fn:10"><sup>10</sup></a>: 4–349, 4–432 </p><p>The lower 8 bits of the FLAGS register is also open to direct load/store manipulation by SAHF and LAHF (load/store AH into flags). </p> <h3>Example</h3> <p>The ability to push and pop FLAGS registers lets a program manipulate information in the FLAGS in ways for which machine-language instructions do not exist. For example, the cld and std instructions clear and set the direction flag (DF), respectively; but there is no instruction to complement DF. This can be achieved with the following <a href="/facts/Assembly_code/7XuV0cla">assembly code</a>: </p> ; This is 8086 code, with 16-bit registers pushed onto the stack, ; and the flags register is only 16 bits with this CPU. pushf ; Use the stack to transfer the FLAGS pop ax ; … into the AX register push ax ; and copy them back onto the stack for storage xor ax, 400h ; Toggle (invert, ‘complement’) the DF only; other bits are unchanged push ax ; Use the stack again to move the modified value popf ; … into the FLAGS register ; Insert here the code that required the DF flag to be complemented popf ; Restore the original value of the FLAGS <p>By manipulating the FLAGS register, a program can determine the model of the installed processor. For example, the alignment flag can only be changed on the <a href="/facts/Intel_80486/2zfEAXAw">486</a> and above. If the program tries to modify this flag and senses that the modification did not persist, the processor is earlier than the 486. </p><p>Starting with the <a href="/facts/P5_(microarchitecture)/dqChAmxz">Intel Pentium</a>, the <a href="/facts/CPUID/BdbdpdgB">CPUID</a> instruction reports the processor model. However, the above method remains useful to distinguish between earlier models. </p> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/Bit_field/fWgTjqvX">Bit field</a></li> <li><a href="/facts/Control_register/9VGRHh3f">Control register</a></li> <li><a href="/facts/CPU_flag_(x86)/BdbdpdgB">CPU flag (x86)</a></li> <li><a href="/facts/Program_status_word/ejBFel3W">Program status word</a></li> <li><a href="/facts/Status_register/7KMY9LR9">Status register</a></li> <li><a href="/facts/X86_assembly_language/GTUtvkMm">x86 assembly language</a></li> <li><a href="/facts/X86_instruction_listings/bM7kSLwj">x86 instruction listings</a></li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>Intel 64 and IA-32 Architectures Software Developer's Manual (PDF). Vol. 1. May 2012. pp. 3–21. <a href="https://download.intel.com/products/processor/manual/253665.pdf#page=93" target="_blank">https://download.intel.com/products/processor/manual/253665.pdf#page=93</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>Intel 64 and IA-32 Architectures Software Developer's Manual (PDF). Vol. 1. Dec 2016. p. 78. <a href="https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf#page=78" target="_blank">https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf#page=78</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>"Silicon reverse engineering: The 8085's undocumented flags". www.righto.com. Retrieved 2018-10-21. <a href="https://www.righto.com/2013/02/looking-at-silicon-to-understanding.html" target="_blank">https://www.righto.com/2013/02/looking-at-silicon-to-understanding.html</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>"Silicon reverse engineering: The 8085's undocumented flags". www.righto.com. Retrieved 2018-10-21. <a href="https://www.righto.com/2013/02/looking-at-silicon-to-understanding.html" target="_blank">https://www.righto.com/2013/02/looking-at-silicon-to-understanding.html</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>Intel 64 and IA-32 Architectures Software Developer's Manual, Vol. 1. Dec 2022. pp. 3–16. <a href="https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html" target="_blank">https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>"Silicon reverse engineering: The 8085's undocumented flags". www.righto.com. Retrieved 2018-10-21. <a href="https://www.righto.com/2013/02/looking-at-silicon-to-understanding.html" target="_blank">https://www.righto.com/2013/02/looking-at-silicon-to-understanding.html</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>NEC, 16-bit V-Series User's Manual, document no. U11301E, sep 2000, p. 186 <a href="https://www.ardent-tool.com/CPU/docs/NEC/V20-V30/v_series.pdf" target="_blank">https://www.ardent-tool.com/CPU/docs/NEC/V20-V30/v_series.pdf</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> <li id="fn:8"><p>VIA, PadLock Programming Guide, v1.66, Aug 4, 2005, pp. 7-8. Archived from the original on May 26, 2010. <a href="https://web.archive.org/web/20100526054140/http://linux.via.com.tw/support/beginDownload.action?eleid=181&fid=261" target="_blank">https://web.archive.org/web/20100526054140/http://linux.via.com.tw/support/beginDownload.action?eleid=181&fid=261</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></p></li> <li id="fn:9"><p>VIA, VIA C3 Processor Alternate Instruction Set Application Note, version 0.24, 2002 - see figure 2 on page 12 and chapter 4 on page 21 for details on the EFLAGS.AI flag. <a href="https://www.bitsavers.org/components/viaTechnologies/C3-ais-appnote.pdf" target="_blank">https://www.bitsavers.org/components/viaTechnologies/C3-ais-appnote.pdf</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></p></li> <li id="fn:10"><p>Intel 64 and IA-32 Architectures Software Developer's Manual (PDF). Vol. 2B. May 2012. <a href="https://download.intel.com/products/processor/manual/253667.pdf#page=351" target="_blank">https://download.intel.com/products/processor/manual/253667.pdf#page=351</a> <a href="#fnref:10" class="footnote-back-ref">↩</a></p></li> </ol>