If these two assembly pseudocode instructions run in a pipeline, after fetching and decoding the second instruction, the pipeline stalls, waiting until the result of the addition is written and read.
In some cases all stalls from such read-after-write data hazards can be completely eliminated by operand forwarding:345
The CPU control unit must implement logic to detect dependencies where operand forwarding makes sense. A multiplexer can then be used to select the proper register or flip-flop to read the operand from.
"CMSC 411 Lecture 19, Pipelining Data Forwarding". University of Maryland Baltimore County Computer Science and Electrical Engineering Department. Retrieved 2020-01-22. http://www.csee.umbc.edu/~squire/cs411_l19.html ↩
"High performance computing, Notes of class 11". hpc.serc.iisc.ernet.in. September 2000. Archived from the original on 2013-12-27. Retrieved 2014-02-08. https://web.archive.org/web/20131227033204/http://hpc.serc.iisc.ernet.in/~govind/hpc/L10-Pipeline.txt ↩
Gurpur M. Prabhu. "Computer Architecture Tutorial". Sections "Forwarding". and "Data Hazard Classification". https://web.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/forward.html ↩
Dr. Orion Lawlor. "Pipelining, Pipeline Stalls, and Operand Forwarding". https://www.cs.uaf.edu/2011/fall/cs441/lecture/09_20_pipelining.html ↩
Larry Snyder. "Pipeline Review". https://courses.cs.washington.edu/courses/cse378/09au/lectures/cse378au09-15.pdf ↩