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Multiplexers are part of computer systems to select data from a specific source, be it a memory chip or a hardware peripheral. A computer uses multiplexers to control the data and address buses, allowing the processor to select data from multiple data sources.

In digital communications, multiplexers allow several connections over a single channel by connecting the multiplexer's single output to the demultiplexer's single input (Time-Division Multiplexing). The image to the right demonstrates this benefit. In this case, the cost of implementing separate channels for each data source is higher than the cost and inconvenience of providing the multiplexing/demultiplexing functions.

At the receiving end of the data link a complementary demultiplexer is usually required to break the single data stream back down into the original streams. In some cases, the far end system may have functionality greater than a simple demultiplexer, and while the demultiplexing still occurs technically, it may never be implemented discretely. This would be the case when, for instance, a multiplexer serves a number of IP network users; and then feeds directly into a router, which immediately reads the content of the entire link into its routing processor; and then does the demultiplexing in memory from where it will be converted directly into IP sections.

Often, a multiplexer and demultiplexer are combined into a single piece of equipment, which is simply referred to as a multiplexer. Both circuit elements are needed at both ends of a transmission link because most communications systems transmit in both directions.

In analog circuit design, a multiplexer is a special type of analog switch that connects one signal selected from several inputs to a single output.

Digital multiplexers

In digital circuit design, the selector wires are of digital value. In the case of a 2-to-1 multiplexer, a logic value of 0 would connect I 0 {\displaystyle I_{0}} to the output, while a logic value of 1 would connect I 1 {\displaystyle I_{1}} to the output. In larger multiplexers, the number of selector pins is equal to ⌈ log 2 ⁡ ( n ) ⌉ {\displaystyle \left\lceil \log _{2}(n)\right\rceil } where n {\displaystyle n} is the number of inputs.

For example, 9 to 16 inputs would require no fewer than 4 selector pins and 17 to 32 inputs would require no fewer than 5 selector pins. The binary value expressed on these selector pins determines the selected input pin.

A 2-to-1 multiplexer has a Boolean equation where A {\displaystyle A} and B {\displaystyle B} are the two inputs, S 0 {\displaystyle S_{0}} is the selector input, and Z {\displaystyle Z} is the output:

Z = ( A ∧ ¬ S 0 ) ∨ ( B ∧ S 0 ) {\displaystyle Z=(A\wedge \neg S_{0})\vee (B\wedge S_{0})} or Z = ( A ⋅ S 0 ¯ ) + ( B ⋅ S 0 ) {\displaystyle Z=(A\cdot {\overline {S_{0}}})+(B\cdot S_{0})}

Which can be expressed as a truth table:

S 0 {\displaystyle S_{0}}	A {\displaystyle A}	B {\displaystyle B}	Z {\displaystyle Z}
0	0	0	0
0	0	1	0
0	1	0	1
0	1	1	1
1	0	0	0
1	0	1	1
1	1	0	0
1	1	1	1

Or, in simpler notation:

S 0 {\displaystyle S_{0}}	Z {\displaystyle Z}
0	A
1	B

These tables show that when S 0 = 0 {\displaystyle S_{0}=0} then Z = A {\displaystyle Z=A} but when S 0 = 1 {\displaystyle S_{0}=1} then Z = B {\displaystyle Z=B} . A straightforward realization of this 2-to-1 multiplexer would need 2 AND gates, an OR gate, and a NOT gate. While this is mathematically correct, a direct physical implementation would be prone to race conditions that require additional gates to suppress.⁴

Larger multiplexers are also common and, as stated above, require ⌈ log 2 ⁡ ( n ) ⌉ {\displaystyle \left\lceil \log _{2}(n)\right\rceil } selector pins for n {\displaystyle n} inputs. Other common sizes are 4-to-1, 8-to-1, and 16-to-1. Since digital logic uses binary values, powers of 2 are used (4, 8, 16) to maximally control a number of inputs for the given number of selector inputs.

The Boolean equation for a 4-to-1 multiplexer is:

Z = ( A ∧ ¬ S 1 ∧ ¬ S 0 ) ∨ ( B ∧ ¬ S 1 ∧ S 0 ) ∨ ( C ∧ S 1 ∧ ¬ S 0 ) ∨ ( D ∧ S 1 ∧ S 0 ) {\displaystyle Z=(A\wedge \neg {S_{1}}\wedge \neg S_{0})\vee (B\wedge \neg S_{1}\wedge S_{0})\vee (C\wedge S_{1}\wedge \neg S_{0})\vee (D\wedge S_{1}\wedge S_{0})} or Z = ( A ⋅ S 1 ¯ ⋅ S 0 ¯ ) + ( B ⋅ S 1 ¯ . S 0 ) + ( C ⋅ S 1 ⋅ S 0 ¯ ) + ( D ⋅ S 1 ⋅ S 0 ) {\displaystyle Z=(A\cdot {\overline {S_{1}}}\cdot {\overline {S_{0}}})+(B\cdot {\overline {S_{1}}}.S_{0})+(C\cdot S_{1}\cdot {\overline {S_{0}}})+(D\cdot S_{1}\cdot S_{0})}

Which can be expressed as a truth table:

S 1 {\displaystyle S_{1}}	S 0 {\displaystyle S_{0}}	Z {\displaystyle Z}
0	0	A
0	1	B
1	0	C
1	1	D

The following 4-to-1 multiplexer is constructed from 3-state buffers and AND gates (the AND gates are acting as the decoder):

The subscripts on the I n {\displaystyle I_{n}} inputs indicate the decimal value of the binary control inputs at which that input is let through.

Chaining multiplexers and mux trees

Larger Multiplexers can be constructed by using smaller multiplexers by chaining them together in what are called "mux trees". For example, an 8:1 multiplexer can be made with two 4:1 multiplexers and one 2:1 multiplexer. The two 4:1 multiplexer outputs are fed into the 2:1 with the selector pins on the 4:1's put in parallel giving a total number of selector inputs to 3, which is equivalent to an 8:1.

List of ICs which provide multiplexing

For 7400 series part numbers in the following table, "x" is the logic family.

IC No.	Function	Output State
74x157	Quad 2:1 mux.	Output same as input given
74x158	Quad 2:1 mux.	Output is inverted input
74x153	Dual 4:1 mux.	Output same as input
74x352	Dual 4:1 mux.	Output is inverted input
74x151A	8:1 mux.	Both outputs available (i.e., complementary outputs)
74x151	8:1 mux.	Output is inverted input
74x150	16:1 mux.	Output is inverted input

Digital demultiplexers

See also: Inverse multiplexer

Demultiplexers take one data input and a number of selection inputs, and they have several outputs. They forward the data input to one of the outputs depending on the values of the selection inputs. Demultiplexers are sometimes convenient for designing general-purpose logic because if the demultiplexer's input is always true, the demultiplexer acts as a binary decoder. This means that any function of the selection bits can be constructed by logically OR-ing the correct set of outputs.

If X is the input and S is the selector, and A and B are the outputs:

A = ( X ∧ ¬ S ) {\displaystyle A=(X\wedge \neg S)} B = ( X ∧ S ) {\displaystyle B=(X\wedge S)}

List of ICs which provide demultiplexing

For 7400 series part numbers in the following table, "x" is the logic family.

IC No. (7400)	IC No. (4000)	Function	Output State
74x139		Dual 1:4 demux.	Output is inverted input
74x156		Dual 1:4 demux.	Output is open collector
74x138		1:8 demux.	Output is inverted input
74x238		1:8 demux.
74x154		1:16 demux.	Output is inverted input
74x159	CD4514/15	1:16 demux.	Output is open collector and same as input

Bi-directional multiplexers

Bi-directional multiplexers are built using analog switches or transmission gates controlled by the select pins. This allows the roles of input and output to be swapped so that a bi-directional multiplexer can function both as a demultiplexer and multiplexer.⁵

Multiplexers as PLDs

Multiplexers can also be used as programmable logic devices, to implement Boolean functions. Any Boolean function of n variables and one result can be implemented with a multiplexer with n selector inputs. The variables are connected to the selector inputs, and the function result, 0 or 1, for each possible combination of selector inputs is connected to the corresponding data input. If one of the variables (for example, D) is also available inverted, a multiplexer with n-1 selector inputs is sufficient; the data inputs are connected to 0, 1, D, or ~D, according to the desired output for each combination of the selector inputs.⁶

Unconventional use of multiplexers for arithmetic

Multiplexers have found application in unconventional stochastic computing (SC), particularly in facilitating arithmetic addition. In this paradigm, data is represented as a probability bitstream where the number of '1' bits signifies the magnitude of a value. Thus, the function of a 2-to-1 multiplexer can be conceptualized as a probability function denoted as:

y = P ( a ) × P ( 1 − s ) + P ( b ) × P ( s ) {\displaystyle y=P(a)\times P(1-s)+P(b)\times P(s)}

, where a and b are the input bitstream and s is the select input. Using the select input = 0.5 yields:

y = P ( a ) + P ( b ) 2 {\displaystyle y={\frac {P(a)+P(b)}{2}}}

While this approach doesn't yield exact addition but rather scaled addition, it is deemed acceptable in most SC studies. Multiplexers are extensively utilized for tasks such as average addition, average pooling, and median filtering within SC circuits. Moreover, more sophisticated applications of multiplexers include serving as Bernstein polynomial function generator,⁷ capable of producing arbitrary mathematical functions within the SC domain. Recent research has also revealed that combinations of multiplexers can facilitate large-scale multiply-accumulate operation,⁸ demonstrating feasibility in accelerating convolutional neural network on field-programmable gate arrays.

See also

• Digital subscriber line access multiplexer (DSLAM)
• Inverse multiplexer
• Multiplexing
  • Code-division multiplexing
  • Frequency-division multiplexing
  • Time-division multiplexing
  • Wavelength-division multiplexing
  • Statistical multiplexing
  • Charlieplexing
• Priority encoder
• Rule 184, a cellular automaton in which each cell acts as a multiplexer for the values from the two adjacent cells
• Statistical multiplexer
• Ternary conditional operator

Further reading

• Mano, M. Morris; Kime, Charles R. (2008). Logic and Computer Design Fundamentals (4th ed.). Prentice Hall. ISBN 978-0-13-198926-9..

External links

• Media related to Multiplexers at Wikimedia Commons
• The dictionary definition of multiplexer at Wiktionary

References

1. Debashis, De (2010). Basic Electronics. Dorling Kindersley. p. 557. ISBN 9788131710685. 9788131710685 ↩

2. Lipták, Béla (2002). Instrument engineers' handbook: Process software and digital networks. CRC Press. p. 343. ISBN 9781439863442. 9781439863442 ↩

3. Harris, David (2007). Digital Design and Computer Architecture. Penrose. p. 79. ISBN 9780080547060. 9780080547060 ↩

4. Crowe, John; Hayes-Gill, Barrie (1998). "The multiplexer hazard". Introduction to Digital Electronics. Elsevier. pp. 111–3. ISBN 9780080534992. 9780080534992 ↩

5. "Are switches & multiplexers bidirectional? | Video | TI.com". Texas Instruments. Retrieved 2023-08-03. https://www.ti.com/video/6112994495001 ↩

6. Lancaster, Donald E. (1974). The TTL Cookbook. H.W. Sams. pp. 140–3. ISBN 9780672210358. 9780672210358 ↩

7. Najafi, M. Hassan; Li, Peng; Lilja, David J.; Qian, Weikang; Bazargan, Kia; Riedel, Marc (2017-06-29). "A Reconfigurable Architecture with Sequential Logic-Based Stochastic Computing". ACM Journal on Emerging Technologies in Computing Systems. 13 (4): 57:1–57:28. doi:10.1145/3060537. ISSN 1550-4832. https://dl.acm.org/doi/10.1145/3060537 ↩

8. Lee, Yang Yang; Halim, Zaini Abdul; Wahab, Mohd Nadhir Ab; Almohamad, Tarik Adnan (2024-03-04). "Stochastic Computing Convolutional Neural Network Architecture Reinvented for Highly Efficient Artificial Intelligence Workload on Field-Programmable Gate Array". Research. 7: 0307. Bibcode:2024Resea...7..307L. doi:10.34133/research.0307. ISSN 2639-5274. PMC 10911856. PMID 38439995. https://www.ncbi.nlm.nih.gov/pmc/articles/PMC10911856 ↩