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<h2 id="motivation">Motivation</h2> <p>In memory design, there is an inherent trade-off between capacity and speed because larger capacity implies larger size and thus greater physical distances for signals to travel causing <a href="/facts/Propagation_delay/tUcrAwwe">propagation delays</a>. There is also a tradeoff between high-performance technologies such as <a href="/facts/Static_random-access_memory/Pmyo4V5e">SRAM</a> and cheaper, easily mass-produced commodities such as <a href="/facts/DRAM/koI9FGo5">DRAM</a>, <a href="/facts/Flash_memory/Cn8JsStx">flash</a>, or <a href="/facts/Hard_disk/kekLSGSE">hard disks</a>. </p><p>The <a href="/facts/Data_buffer/tVy4j2Dc">buffering</a> provided by a cache benefits one or both of <a href="/facts/Latency_(engineering)/6Bjhn30H">latency</a> and <a href="/facts/Throughput/6zAUsXqw">throughput</a> (<a href="/facts/Bandwidth_(computing)/lY6Tb4gX">bandwidth</a>). </p><p>A larger resource incurs a significant latency for access – e.g. it can take hundreds of clock cycles for a modern 4 GHz processor to reach DRAM. This is mitigated by reading large chunks into the cache, in the hope that subsequent reads will be from nearby locations and can be read from the cache. Prediction or explicit <a href="/facts/Cache_prefetching/cuCGl0Vm">prefetching</a> can be used to guess where future reads will come from and make requests ahead of time; if done optimally, the latency is bypassed altogether. </p><p>The use of a cache also allows for higher throughput from the underlying resource, by assembling multiple fine-grain transfers into larger, more efficient requests. In the case of DRAM circuits, the additional throughput may be gained by using a wider data bus. </p> <h2 id="operation">Operation</h2> <p>Hardware implements cache as a <a href="/facts/Block_(data_storage)/S3vT7c6N">block</a> of memory for temporary storage of data likely to be used again. <a href="/facts/Central_processing_unit/Jxp1bqMV">Central processing units</a> (CPUs), <a href="/facts/Solid-state_drive/aMHBy8gU">solid-state drives</a> (SSDs) and hard disk drives (HDDs) frequently include hardware-based cache, while <a href="/facts/Web_browser/2pfyymLs">web browsers</a> and <a href="/facts/Web_server/A4GS6thA">web servers</a> commonly rely on software caching. </p><p>A cache is made up of a pool of entries. Each entry has associated <i>data</i>, which is a copy of the same data in some <i>backing store</i>. Each entry also has a <i>tag</i>, which specifies the identity of the data in the backing store of which the entry is a copy. </p><p>When the cache client (a CPU, web browser, <a href="/facts/Operating_system/8XTuvMh2">operating system</a>) needs to access data presumed to exist in the backing store, it first checks the cache. If an entry can be found with a tag matching that of the desired data, the data in the entry is used instead. This situation is known as a cache hit. For example, a web browser program might check its local cache on disk to see if it has a local copy of the contents of a web page at a particular <a href="/facts/URL/pPD5g7Wq">URL</a>. In this example, the URL is the tag, and the content of the web page is the data. The percentage of accesses that result in cache hits is known as the hit rate or hit ratio of the cache. </p><p>The alternative situation, when the cache is checked and found not to contain any entry with the desired tag, is known as a cache miss. This requires a more expensive access of data from the backing store. Once the requested data is retrieved, it is typically copied into the cache, ready for the next access. </p><p>During a cache miss, some other previously existing cache entry is typically removed in order to make room for the newly retrieved data. The <a href="/facts/Heuristic_(computer_science)/PM2qkoa2">heuristic</a> used to select the entry to replace is known as the <a href="/facts/Cache_replacement_policies/LFW5UqPo">replacement policy</a>. One popular replacement policy, least recently used (LRU), replaces the oldest entry, the entry that was accessed less recently than any other entry. More sophisticated caching algorithms also take into account the frequency of use of entries. </p> <h3>Write policies</h3> <p>Cache writes must eventually be propagated to the backing store. The timing for this is governed by the <i>write policy</i>. The two primary write policies are:<a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a> </p> <ul><li><i>Write-through</i>: Writes are performed synchronously to both the cache and the backing store.</li> <li><i>Write-back</i>: Initially, writing is done only to the cache. The write to the backing store is postponed until the modified content is about to be replaced by another cache block.</li></ul> <p>A write-back cache is more complex to implement since it needs to track which of its locations have been written over and mark them as <i>dirty</i> for later writing to the backing store. The data in these locations are written back to the backing store only when they are evicted from the cache, a process referred to as a <i>lazy write</i>. For this reason, a read miss in a write-back cache may require two memory accesses to the backing store: one to write back the dirty data, and one to retrieve the requested data. Other policies may also trigger data write-back. The client may make many changes to data in the cache, and then explicitly notify the cache to write back the data. </p><p>Write operations do not return data. Consequently, a decision needs to be made for write misses: whether or not to load the data into the cache. This is determined by these <i>write-miss policies</i>: </p> <ul><li><i>Write allocate</i> (also called <i>fetch on write</i>): Data at the missed-write location is loaded to cache, followed by a write-hit operation. In this approach, write misses are similar to read misses.</li> <li><i>No-write allocate</i> (also called <i>write-no-allocate</i> or <i>write around</i>): Data at the missed-write location is not loaded to cache, and is written directly to the backing store. In this approach, data is loaded into the cache on read misses only.</li></ul> <p>While both write policies can Implement either write-miss policy, they are typically paired as follows:<a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a><a class="footnote-ref" id="fnref:5" href="#fn:5"><sup>5</sup></a> </p> <ul><li>A write-back cache typically employs write allocate, anticipating that subsequent writes or reads to the same location will benefit from having the data already in the cache.</li> <li>A write-through cache uses no-write allocate. Here, subsequent writes have no advantage, since they still need to be written directly to the backing store.</li></ul> <p>Entities other than the cache may change the data in the backing store, in which case the copy in the cache may become out-of-date or <i>stale</i>. Alternatively, when the client updates the data in the cache, copies of that data in other caches will become stale. Communication protocols between the cache managers that keep the data consistent are associated with <a href="/facts/Cache_coherence/MhUD576q">cache coherence</a>. </p> <h3>Prefetch</h3> <p class="note">Main article: <a href="/facts/Cache_prefetching/cuCGl0Vm">Cache prefetching</a></p> <p class="note">Further information: <a href="/facts/Memory_paging/KR889x5k">Memory paging § Page replacement techniques</a></p> <p>On a cache read miss, caches with a <i><a href="/facts/Demand_paging/Y4L70dUh">demand paging</a> policy</i> read the minimum amount from the backing store. A typical demand-paging virtual memory implementation reads one page of virtual memory (often 4 KB) from disk into the disk cache in RAM. A typical CPU reads a single L2 cache line of 128 bytes from DRAM into the L2 cache, and a single L1 cache line of 64 bytes from the L2 cache into the L1 cache. </p><p>Caches with a <a href="/facts/Prefetch_input_queue/17p4x4Ix">prefetch input queue</a> or more general <i>anticipatory paging policy</i> go further—they not only read the data requested, but guess that the next chunk or two of data will soon be required, and so prefetch that data into the cache ahead of time. Anticipatory paging is especially helpful when the backing store has a long latency to read the first chunk and much shorter times to sequentially read the next few chunks, such as <a href="/facts/Disk_storage/hnsXRb5X">disk storage</a> and DRAM. </p><p>A few operating systems go further with a <a href="/facts/Loader_(computing)/eIK4f2xB">loader</a> that always pre-loads the entire executable into RAM. A few caches go even further, not only pre-loading an entire file, but also starting to load other related files that may soon be requested, such as the <a href="/facts/Page_cache/rcKoMtMD">page cache</a> associated with a <a href="/facts/Prefetcher/AzVy2rIL">prefetcher</a> or the <a href="/facts/Web_cache/DqIBcWem">web cache</a> associated with <a href="/facts/Link_prefetching/Mfdpx7UJ">link prefetching</a>. </p> <h2 id="examples-of-hardware-caches">Examples of hardware caches</h2> <h3>CPU cache</h3> <p class="note">Main article: <a href="/facts/CPU_cache/x8BYFcdv">CPU cache</a></p> <p>Small memories on or close to the CPU can operate faster than the much larger <a href="/facts/Main_memory/wPHKFpdx">main memory</a>.<a class="footnote-ref" id="fnref:6" href="#fn:6"><sup>6</sup></a> Most CPUs since the 1980s have used one or more caches, sometimes <a href="/facts/CPU_cache/x8BYFcdv">in cascaded levels</a>; modern high-end <a href="/facts/Embedded_computing/a4muX1wU">embedded</a>, <a href="/facts/Desktop_computer/edFPINdK">desktop</a> and server <a href="/facts/Microprocessor/Fx9CaQht">microprocessors</a> may have as many as six types of cache (between levels and functions).<a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a> Some examples of caches with a specific function are the <a href="/facts/D-cache/Gg0UkuqW">D-cache</a>, <a href="/facts/I-cache/Gg0UkuqW">I-cache</a> and the <a href="/facts/Translation_lookaside_buffer/vvwGkfvD">translation lookaside buffer</a> for the <a href="/facts/Memory_management_unit/tJQtAQzI">memory management unit</a> (MMU). </p> <h3>GPU cache</h3> <p>Earlier <a href="/facts/Graphics_processing_unit/PTK1RQVp">graphics processing units</a> (GPUs) often had limited read-only <a href="/facts/Texture_cache/GfIomenN">texture caches</a> and used <a href="/facts/Swizzling_(computer_graphics)/MAbcpupJ">swizzling</a> to improve 2D <a href="/facts/Locality_of_reference/fYFKDv5q">locality of reference</a>. <a href="/facts/Cache_miss/gmJYN8wm">Cache misses</a> would drastically affect performance, e.g. if <a href="/facts/Mipmapping/z0alvP6k">mipmapping</a> was not used. Caching was important to leverage 32-bit (and wider) transfers for texture data that was often as little as 4 bits per pixel. </p><p>As GPUs advanced, supporting <a href="/facts/General-purpose_computing_on_graphics_processing_units/roBwsPY2">general-purpose computing on graphics processing units</a> and <a href="/facts/Compute_kernel/BxyI4vSf">compute kernels</a>, they have developed progressively larger and increasingly general caches, including <a href="/facts/Instruction_cache/x8BYFcdv">instruction caches</a> for <a href="/facts/Shader/qfhkKFwA">shaders</a>, exhibiting functionality commonly found in CPU caches. These caches have grown to handle <a href="/facts/Synchronization_primitive/n7ID76uM">synchronization primitives</a> between threads and <a href="/facts/Atomic_operation/u3pnNCvs">atomic operations</a>, and interface with a CPU-style MMU. </p> <h3>DSPs</h3> <p><a href="/facts/Digital_signal_processor/YuBXweos">Digital signal processors</a> have similarly generalized over the years. Earlier designs used <a href="/facts/Scratchpad_memory/qd5mHQul">scratchpad memory</a> fed by <a href="/facts/Direct_memory_access/DWuVgclV">direct memory access</a>, but modern DSPs such as <a href="/facts/Qualcomm_Hexagon/o2TV91up">Qualcomm Hexagon</a> often include a very similar set of caches to a CPU (e.g. <a href="/facts/Modified_Harvard_architecture/JhWgY0Ph">Modified Harvard architecture</a> with shared L2, split L1 I-cache and D-cache).<a class="footnote-ref" id="fnref:8" href="#fn:8"><sup>8</sup></a> </p> <h3>Translation lookaside buffer</h3> <p class="note">Main article: <a href="/facts/Translation_lookaside_buffer/vvwGkfvD">Translation lookaside buffer</a></p> <p>A memory management unit (MMU) that fetches page table entries from main memory has a specialized cache, used for recording the results of <a href="/facts/Virtual_address/ILxbMjgv">virtual address</a> to <a href="/facts/Physical_address/G01PUI6A">physical address</a> translations. This specialized cache is called a translation lookaside buffer (TLB).<a class="footnote-ref" id="fnref:9" href="#fn:9"><sup>9</sup></a> </p> <h2 id="in-network-cache">In-network cache</h2> <h3>Information-centric networking</h3> <p><a href="/facts/Information-centric_networking/wPwwCDU9">Information-centric networking</a> (ICN) is an approach to evolve the <a href="/facts/Internet/Xw1rVvJU">Internet</a> infrastructure away from a host-centric paradigm, based on perpetual connectivity and the <a href="/facts/End-to-end_principle/6RkKmdUm">end-to-end principle</a>, to a network architecture in which the focal point is identified information. Due to the inherent caching capability of the nodes in an ICN, it can be viewed as a loosely connected network of caches, which has unique requirements for caching policies. However, ubiquitous content caching introduces the challenge to content protection against unauthorized access, which requires extra care and solutions.<a class="footnote-ref" id="fnref:10" href="#fn:10"><sup>10</sup></a> </p><p>Unlike proxy servers, in ICN the cache is a network-level solution. Therefore, it has rapidly changing cache states and higher request arrival rates; moreover, smaller cache sizes impose different requirements on the content eviction policies. In particular, eviction policies for ICN should be fast and lightweight. Various cache replication and eviction schemes for different ICN architectures and applications have been proposed. </p> <h4>Policies</h4> <h5>Time aware least recently used</h5> <p>The time aware least recently used (TLRU) is a variant of LRU designed for the situation where the stored contents in cache have a valid lifetime. The algorithm is suitable in network cache applications, such as ICN, <a href="/facts/Content_delivery_network/SVuID7jd">content delivery networks</a> (CDNs) and distributed networks in general. TLRU introduces a new term: time to use (TTU). TTU is a time stamp on content which stipulates the usability time for the content based on the locality of the content and information from the content publisher. Owing to this locality-based time stamp, TTU provides more control to the local administrator to regulate in-network storage. </p><p>In the TLRU algorithm, when a piece of content arrives, a cache node calculates the local TTU value based on the TTU value assigned by the content publisher. The local TTU value is calculated by using a locally-defined function. Once the local TTU value is calculated the replacement of content is performed on a subset of the total content stored in cache node. The TLRU ensures that less popular and short-lived content should be replaced with incoming content.<a class="footnote-ref" id="fnref:11" href="#fn:11"><sup>11</sup></a> </p> <h5>Least frequent recently used</h5> <p>The least frequent recently used (LFRU) cache replacement scheme combines the benefits of LFU and LRU schemes. LFRU is suitable for network cache applications, such as ICN, CDNs and distributed networks in general. In LFRU, the cache is divided into two partitions called privileged and unprivileged partitions. The privileged partition can be seen as a protected partition. If content is highly popular, it is pushed into the privileged partition. Replacement of the privileged partition is done by first evicting content from the unprivileged partition, then pushing content from the privileged partition to the unprivileged partition, and finally inserting new content into the privileged partition. In the above procedure, the LRU is used for the privileged partition and an approximated LFU (ALFU) scheme is used for the unprivileged partition. The basic idea is to cache the locally popular content with the ALFU scheme and push the popular content to the privileged partition.<a class="footnote-ref" id="fnref:12" href="#fn:12"><sup>12</sup></a> </p> <h4>Weather forecast</h4> <p>In 2011, the use of smartphones with weather forecasting options was overly taxing <a href="/facts/AccuWeather/7VdQvMhD">AccuWeather</a> servers; two requests from the same area would generate separate requests. An optimization by edge-servers to truncate the GPS coordinates to fewer decimal places meant that the cached results from a nearby query would be used. The number of to-the-server lookups per day dropped by half.<a class="footnote-ref" id="fnref:13" href="#fn:13"><sup>13</sup></a> </p> <h2 id="software-caches">Software caches</h2> <h3>Disk cache</h3> <p>While CPU caches are generally managed entirely by hardware, a variety of software manages other caches. The <a href="/facts/Page_cache/rcKoMtMD">page cache</a> in main memory is managed by the <a href="/facts/Operating_system_kernel/uEj4U3Rz">operating system kernel</a>. </p><p>While the <a href="/facts/Disk_buffer/rvrlT8YE">disk buffer</a>, which is an integrated part of the hard disk drive or solid state drive, is sometimes misleadingly referred to as <i>disk cache</i>, its main functions are write sequencing and read prefetching. High-end <a href="/facts/Disk_controller/dfRSYlMq">disk controllers</a> often have their own on-board cache for the hard disk drive's data blocks. </p><p>Finally, a fast local hard disk drive can also cache information held on even slower data storage devices, such as remote servers (<a href="/facts/Web_cache/DqIBcWem">web cache</a>) or local <a href="/facts/Tape_drive/9MfLuCa0">tape drives</a> or <a href="/facts/Optical_jukebox/facFElHA">optical jukeboxes</a>; such a scheme is the main concept of <a href="/facts/Hierarchical_storage_management/PuGQdMKY">hierarchical storage management</a>. Also, fast flash-based solid-state drives (SSDs) can be used as caches for slower rotational-media hard disk drives, working together as <a href="/facts/Hybrid_drive/zkmDxd7q">hybrid drives</a>. </p> <h3>Web cache</h3> <p class="note">Main article: <a href="/facts/Web_cache/DqIBcWem">Web cache</a></p> <p>Web browsers and <a href="/facts/Web_proxy_server/ArhwQE74">web proxy servers</a>, either locally or at the <a href="/facts/Internet_service_provider/dUacAxef">Internet service provider</a> (ISP), employ web caches to store previous responses from web servers, such as <a href="/facts/Web_page/5JK7xQLe">web pages</a> and <a href="/facts/Image_file_format/tLGQogv3">images</a>. Web caches reduce the amount of information that needs to be transmitted across the network, as information previously stored in the cache can often be re-used. This reduces bandwidth and processing requirements of the web server, and helps to improve <a href="/facts/Responsiveness/80sDpDoI">responsiveness</a> for users of the web.<a class="footnote-ref" id="fnref:14" href="#fn:14"><sup>14</sup></a> </p><p>Another form of cache is <a href="/facts/P2P_caching/uEyP9okg">P2P caching</a>, where the files most sought for by <a href="/facts/Peer-to-peer/wCCdPb0H">peer-to-peer</a> applications are stored in an ISP cache to accelerate P2P transfers. Similarly, decentralised equivalents exist, which allow communities to perform the same task for P2P traffic, for example, Corelli.<a class="footnote-ref" id="fnref:15" href="#fn:15"><sup>15</sup></a> </p> <h3>Memoization</h3> <p class="note">Main article: <a href="/facts/Memoization/u08VhUKm">Memoization</a></p> <p>A cache can store data that is computed on demand rather than retrieved from a backing store. <a href="/facts/Memoization/u08VhUKm">Memoization</a> is an <a href="/facts/Program_optimization/nXz6RpRM">optimization</a> technique that stores the results of resource-consuming <a href="/facts/Function_call/9vFJrg0A">function calls</a> within a lookup table, allowing subsequent calls to reuse the stored results and avoid repeated computation. It is related to the <a href="/facts/Dynamic_programming/CLcabtmk">dynamic programming</a> algorithm design methodology, which can also be thought of as a means of caching. </p> <h3>Content delivery network</h3> <p>A <a href="/facts/Content_delivery_network/SVuID7jd">content delivery network</a> (CDN) is a network of distributed servers that deliver pages and other <a href="/facts/Web_content/u4p0t6kz">web content</a> to a user, based on the geographic locations of the user, the origin of the web page and the content delivery server. </p><p>CDNs were introduced in the late 1990s as a way to speed up the delivery of static content, such as HTML pages, images and videos. By replicating content on multiple servers around the world and delivering it to users based on their location, CDNs can significantly improve the speed and availability of a website or application. When a user requests a piece of content, the CDN will check to see if it has a copy of the content in its cache. If it does, the CDN will deliver the content to the user from the cache.<a class="footnote-ref" id="fnref:16" href="#fn:16"><sup>16</sup></a> </p> <h3>Cloud storage gateway</h3> <p class="note">Main article: <a href="/facts/Cloud_storage_gateway/94RXzkP1">Cloud storage gateway</a></p> <p>A <a href="/facts/Cloud_storage_gateway/94RXzkP1">cloud storage gateway</a> is a <a href="/facts/Hybrid_cloud_storage/tRwq1fm5">hybrid cloud storage</a> device that connects a local network to one or more <a href="/facts/Cloud_storage_service/AWz9wQt8">cloud storage services</a>, typically <a href="/facts/Object_storage/NPHWJSW6">object storage</a> services such as <a href="/facts/Amazon_S3/bqAXYCxq">Amazon S3</a>. It provides a cache for frequently accessed data, providing high speed local access to frequently accessed data in the cloud storage service. Cloud storage gateways also provide additional benefits such as accessing cloud object storage through traditional file serving protocols as well as continued access to cached data during connectivity outages.<a class="footnote-ref" id="fnref:17" href="#fn:17"><sup>17</sup></a> </p> <h3>Other caches</h3> <p>The <a href="/facts/BIND/Mj5qNIuW">BIND DNS daemon</a> caches a mapping of domain names to <a href="/facts/IP_address/z9V22Sw9">IP addresses</a>, as does a <a href="/facts/DNS_resolver/rfxdWFsj">DNS resolver</a> library. </p><p>Write-through operation is common when operating over <a href="/facts/Unreliable_network/v3kGvfvs">unreliable networks</a>, because of the enormous complexity of the coherency protocol required between multiple write-back caches when communication is unreliable. For instance, web page caches and <a href="/facts/Client-side/FSnf27C5">client-side</a> caches for <a href="/facts/Distributed_file_system/Bz61f7Ce">distributed file systems</a> (like those in <a href="/facts/Network_File_System_(protocol)/jWRRALVo">NFS</a> or <a href="/facts/Server_Message_Block/pWM35pl8">SMB</a>) are typically read-only or write-through specifically to keep the network protocol simple and reliable. </p><p><a href="/facts/Web_search_engine/SRntsbz2">Web search engines</a> also frequently make web pages they have indexed available from their <a href="/facts/Search_engine_cache/WALVnxTu">cache</a>. This can prove useful when web pages from a web server are temporarily or permanently inaccessible. </p><p><a href="/facts/Database_caching/9pakVo8M">Database caching</a> can substantially improve the throughput of <a href="/facts/Database/VYcpkevb">database</a> applications, for example in the processing of <a href="/facts/Database_index/TRqmk9It">indexes</a>, <a href="/facts/Data_dictionary/GyQLYd7j">data dictionaries</a>, and frequently used subsets of data. </p><p>A <a href="/facts/Distributed_cache/ry6do0bs">distributed cache</a><a class="footnote-ref" id="fnref:18" href="#fn:18"><sup>18</sup></a> uses networked hosts to provide scalability, reliability and performance to the application.<a class="footnote-ref" id="fnref:19" href="#fn:19"><sup>19</sup></a> The hosts can be co-located or spread over different geographical regions. </p> <h2 id="buffer-vs-cache">Buffer vs. cache</h2> <p>The semantics of a "buffer" and a "cache" are not totally different; even so, there are fundamental differences in intent between the process of caching and the process of buffering. </p><p>Fundamentally, caching realizes a performance increase for transfers of data that is being repeatedly transferred. While a caching system may realize a performance increase upon the initial (typically write) transfer of a data item, this performance increase is due to buffering occurring within the caching system. </p><p>With read caches, a data item must have been fetched from its residing location at least once in order for subsequent reads of the data item to realize a performance increase by virtue of being able to be fetched from the cache's (faster) intermediate storage rather than the data's residing location. With write caches, a performance increase of writing a data item may be realized upon the first write of the data item by virtue of the data item immediately being stored in the cache's intermediate storage, deferring the transfer of the data item to its residing storage at a later stage or else occurring as a background process. Contrary to strict buffering, a caching process must adhere to a (potentially distributed) cache coherency protocol in order to maintain consistency between the cache's intermediate storage and the location where the data resides. Buffering, on the other hand, </p> <ul><li>reduces the number of transfers for otherwise novel data amongst communicating processes, which amortizes overhead involved for several small transfers over fewer, larger transfers,</li> <li>provides an intermediary for communicating processes which are incapable of direct transfers amongst each other, or</li> <li>ensures a minimum data size or representation required by at least one of the communicating processes involved in a transfer.</li></ul> <p>With typical caching implementations, a data item that is read or written for the first time is effectively being buffered; and in the case of a write, mostly realizing a performance increase for the application from where the write originated. Additionally, the portion of a caching protocol where individual writes are deferred to a batch of writes is a form of buffering. The portion of a caching protocol where individual reads are deferred to a batch of reads is also a form of buffering, although this form may negatively impact the performance of at least the initial reads (even though it may positively impact the performance of the sum of the individual reads). In practice, caching almost always involves some form of buffering, while strict buffering does not involve caching. </p><p>A buffer is a temporary memory location that is traditionally used because CPU <a href="/facts/Instruction_(computing)/8p8vwUeE">instructions</a> cannot directly address data stored in peripheral devices. Thus, addressable memory is used as an intermediate stage. Additionally, such a buffer may be feasible when a large block of data is assembled or disassembled (as required by a storage device), or when data may be delivered in a different order than that in which it is produced. Also, a whole buffer of data is usually transferred sequentially (for example to hard disk), so buffering itself sometimes increases transfer performance or reduces the variation or jitter of the transfer's latency as opposed to caching where the intent is to reduce the latency. These benefits are present even if the buffered data are written to the buffer once and read from the buffer once. </p><p>A cache also increases transfer performance. A part of the increase similarly comes from the possibility that multiple small transfers will combine into one large block. But the main performance-gain occurs because there is a good chance that the same data will be read from cache multiple times, or that written data will soon be read. A cache's sole purpose is to reduce accesses to the underlying slower storage. Cache is also usually an <a href="/facts/Abstraction_layer/EV8c84SY">abstraction layer</a> that is designed to be invisible from the perspective of neighboring layers. </p> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/Cache_coloring/68NjspRE">Cache coloring</a></li> <li><a href="/facts/Cache_hierarchy/9lGPQ5r6">Cache hierarchy</a></li> <li><a href="/facts/Cache-oblivious_algorithm/8pueWrAn">Cache-oblivious algorithm</a></li> <li><a href="/facts/Cache_stampede/XQVW4ed4">Cache stampede</a></li> <li><a href="/facts/Cache_language_model/j3G58KP0">Cache language model</a></li> <li><a href="/facts/Cache_manifest_in_HTML5/cY7bRxPq">Cache manifest in HTML5</a></li> <li><a href="/facts/Dirty_bit/VMH0pb1v">Dirty bit</a></li> <li><a href="/facts/Five-minute_rule/JVQ5MBRQ">Five-minute rule</a></li> <li><a href="/facts/Materialized_view/eJhoKA2Q">Materialized view</a></li> <li><a href="/facts/Memory_hierarchy/ttwjvRyd">Memory hierarchy</a></li> <li><a href="/facts/Pipeline_burst_cache/CUTCF7fD">Pipeline burst cache</a></li> <li><a href="/facts/Temporary_file/5PRRodGA">Temporary file</a></li></ul> <h2 id="further-reading">Further reading</h2> <ul><li><a href="https://people.freebsd.org/~lstewart/articles/cpumemory.pdf">"What Every Programmer Should Know About Memory"</a></li> <li><a href="http://msdn.microsoft.com/en-us/library/dd129907.aspx">"Caching in the Distributed Environment"</a></li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>"Cache". 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