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Dynamic frequency scaling
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<h2 id="operation">Operation</h2> <p class="note">See also: <a href="/facts/Processor_power_dissipation/nmyJTs0m">Processor power dissipation § Sources</a></p> <p>The dynamic power (<i><a href="/facts/Switching_power/BNbaFmEL">switching power</a></i>) dissipated by a chip is <i>C·V2·A·f</i>, where C is the <a href="/facts/Capacitance/0pH046TL">capacitance</a> being switched per clock cycle, V is <a href="/facts/Voltage/EN2po6N2">voltage</a>, A is the <i>activity factor</i><a class="footnote-ref" id="fnref:1" href="#fn:1"><sup>1</sup></a> indicating the average number of switching events per clock cycle by the transistors in the chip (as a unitless quantity) and f is the clock frequency.<a class="footnote-ref" id="fnref:2" href="#fn:2"><sup>2</sup></a> </p><p>Voltage is therefore the main determinant of power usage and heating.<a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a> The voltage required for stable operation is determined by the frequency at which the circuit is clocked, and can be reduced if the frequency is also reduced.<a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a> Dynamic power alone does not account for the total power of the chip, however, as there is also static power, which is primarily because of various leakage currents. Due to static power consumption and asymptotic execution time it has been shown that the energy consumption of software shows convex energy behavior, i.e., there exists an optimal CPU frequency at which energy consumption is minimized.<a class="footnote-ref" id="fnref:5" href="#fn:5"><sup>5</sup></a> <a href="/facts/Subthreshold_leakage/bB9yIDqF">Leakage current</a> has become more and more important as transistor sizes have become smaller and threshold voltage levels are reduced. A decade ago, dynamic power accounted for approximately two-thirds of the total chip power. The power loss due to leakage currents in contemporary CPUs and SoCs tend to dominate the total power consumption. In the attempt to control the leakage power, <a href="/facts/High-%25CE%25BA_dielectric/4E8qtXmp">high-k metal-gates</a> and power gating have been common methods. </p><p>Dynamic voltage scaling is another related power conservation technique that is often used in conjunction with frequency scaling, as the frequency that a chip may run at is related to the operating voltage. </p><p>The efficiency of some electrical components, such as voltage regulators, decreases with increasing temperature, so the power usage may increase with temperature. Since increasing power use may increase the temperature, increases in voltage or frequency may increase system power demands even further than the CMOS formula indicates, and vice versa.<a class="footnote-ref" id="fnref:6" href="#fn:6"><sup>6</sup></a><a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a> </p> <h2 id="standard-interface"> Standard interface</h2> <p><a href="/facts/ACPI/odRvjcxt">ACPI</a> 1.0 (1996) defines a way for a CPU to go to idle "C states", but defines no frequency-scaling system. </p><p>ACPI 2.0 (2000) introduces a system of <i>P states</i> (power-performance states) that a processor can use to communicate its possible frequency–power settings to the OS. The operating system then sets the speed as needed by switching between these states. Throttling technology such as SpeedStep, PowerNow!/Cool'n'Quiet, and PowerSaver all work through P states. There is a limit of 16 states maximum.<a class="footnote-ref" id="fnref:8" href="#fn:8"><sup>8</sup></a> </p><p>ACPI 5.0 (2011) introduces collaborative processor performance control (CPPC), exposing hundreds of performance levels to the OS for selection in the form of a "performance level" abstracted away from the frequency. This abstraction provides some leeway for the processor to adjust its workings in ways other than just the frequency.<a class="footnote-ref" id="fnref:9" href="#fn:9"><sup>9</sup></a><a class="footnote-ref" id="fnref:10" href="#fn:10"><sup>10</sup></a><a class="footnote-ref" id="fnref:11" href="#fn:11"><sup>11</sup></a> </p> <h2 id="autonomous-frequency-scaling">Autonomous frequency scaling</h2> <p>A number of modern CPUs can perform frequency scaling autonomously, using a performance level range and a "efficiency/performance preference" hint from the OS. </p> <ul><li>Intel CPUs starting with <a href="/facts/Skylake_(microarchitecture)/qpcDcebM">Skylake</a> support <i>hardware-managed P-states</i> aka <i>Speed Shift</i>, It based on CPPC protocol, and it using <a href="/facts/Model-specific_register/uzoD3Ynm">model-specific register</a> as the control channel.<a class="footnote-ref" id="fnref:12" href="#fn:12"><sup>12</sup></a><a class="footnote-ref" id="fnref:13" href="#fn:13"><sup>13</sup></a></li> <li>AMD CPUs starting with <a href="/facts/Zen_2/pdL7I80c">Zen 2</a> supports a similar feature. It depends on CPPC being enabled. The preferred communication channel is a MSR (different from the Intel one) introduced in Zen 3; Zen 2 units use the ACPI AML method.<a class="footnote-ref" id="fnref:14" href="#fn:14"><sup>14</sup></a></li></ul> <h2 id="performance-impact">Performance impact</h2> <p>Dynamic frequency scaling reduces the number of instructions a processor can issue in a given amount of time, thus reducing performance. Hence, it is generally used when the workload is not CPU-bound. </p><p>Dynamic frequency scaling by itself is rarely worthwhile as a way to conserve switching power. Saving the highest possible amount of power requires dynamic voltage scaling too, because of the V2 component and the fact that modern CPUs are strongly optimized for low power idle states. In most constant-voltage cases, it is more efficient to run briefly at peak speed and stay in a deep idle state for longer time (called "race to idle" or computational sprinting), than it is to run at a reduced clock rate for a long time and only stay briefly in a light idle state. However, reducing voltage along with clock rate can change those trade-offs. </p><p>A related-but-opposite technique is <a href="/facts/Overclocking/wNpjgAFI">overclocking</a>, whereby processor performance is increased by ramping the processor's (dynamic) frequency beyond the manufacturer's design specifications. </p><p>One major difference between the two is that in modern PC systems overclocking is mostly done over the <a href="/facts/Front_Side_Bus/LgYSB7Wl">Front Side Bus</a> (mainly because the multiplier is normally locked), but dynamic frequency scaling is done with the <a href="/facts/CPU_multiplier/p1GVNh7K">multiplier</a>. Moreover, overclocking is often static, while dynamic frequency scaling is always dynamic. Software can often incorporate overclocked frequencies into the frequency scaling algorithm, if the chip degradation risks are allowable. </p> <h2 id="support-across-vendors">Support across vendors</h2> <h3>Intel</h3> <p><a href="/facts/Intel/SMF0gJJX">Intel</a>'s CPU throttling technology, <a href="/facts/SpeedStep/kbjhM3Wz">SpeedStep</a>, is used in its mobile and desktop CPU lines. </p> <h3>AMD</h3> <p><a href="/facts/AMD/CB1G7QTb">AMD</a> employs two different CPU throttling technologies. AMD's <a href="/facts/Cool%2527n%2527Quiet/uMumqebr">Cool'n'Quiet</a> technology is used on its desktop and server processor lines. The aim of Cool'n'Quiet is not to save battery life, as it is not used in AMD's mobile processor line, but instead with the purpose of producing less heat, which in turn allows the system fan to spin down to slower speeds, resulting in cooler and quieter operation, hence the name of the technology. AMD's <a href="/facts/PowerNow!/RL9bTB8f">PowerNow!</a> CPU throttling technology is used in its mobile processor line, though some supporting CPUs like the <a href="/facts/AMD_K6-2/xu2VCf0r">AMD K6-2</a>+ can be found in desktops as well. </p><p><a href="/facts/AMD_PowerTune/NMNAqExx">AMD PowerTune</a> and <a href="/facts/AMD_ZeroCore_Power/WYNvhDUP">AMD ZeroCore Power</a> are dynamic frequency scaling technologies for <a href="/facts/Graphics_processing_unit/PTK1RQVp">GPUs</a>. </p> <h3>VIA Technologies</h3> <p><a href="/facts/VIA_Technologies/g6REHNFE">VIA Technologies</a> processors use a technology named <a href="/facts/LongHaul/1ngAuB99">LongHaul</a> (PowerSaver), while <a href="/facts/Transmeta/RmnrADmX">Transmeta</a>'s version was called <a href="/facts/LongRun/lUQSvKWL">LongRun</a>. </p><p>The 36-processor <a href="/facts/Asynchronous_array_of_simple_processors/beVk7CXa">AsAP 1</a> chip is among the first multi-core processor chips to support completely unconstrained clock operation (requiring only that frequencies are below the maximum allowed) including arbitrary changes in frequency, starts, and stops. The 167-processor <a href="/facts/Asynchronous_array_of_simple_processors/beVk7CXa">AsAP 2</a> chip is the first multi-core processor chip which enables individual processors to make fully unconstrained changes to their own clock frequencies. </p><p>According to the <a href="/facts/Advanced_Configuration_and_Power_Interface/GnLLzfyr">ACPI</a> Specs, the C0 working state of a modern-day CPU can be divided into the so-called "P"-states (performance states) which allow clock rate reduction and "T"-states (throttling states) which will further throttle down a CPU (but not the actual clock rate) by inserting STPCLK (stop clock) signals and thus omitting duty cycles. </p> <h3>ARM</h3> <p>Different ARM-based systems on chip provide CPU and GPU throttling. </p> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/Dynamic_voltage_scaling/BNbaFmEL">Dynamic voltage scaling</a></li> <li><a href="/facts/Clock_gating/u2nGKGPm">Clock gating</a></li> <li><a href="/facts/HLT_(x86_instruction)/3uRtLUe4">HLT (x86 instruction)</a></li></ul> <p>Power Saving Technologies: </p> <ul><li><a href="/facts/Cool%2527n%2527Quiet/uMumqebr">AMD Cool'n'Quiet</a> (desktop CPUs)</li> <li><a href="/facts/PowerNow!/RL9bTB8f">AMD PowerNow!</a> (laptop CPUs)</li> <li><a href="/facts/AMD_PowerTune/NMNAqExx">AMD PowerTune</a>/<a href="/facts/AMD_PowerPlay/By12rf5S">AMD PowerPlay</a> (graphics)</li> <li><a href="/facts/SpeedStep/kbjhM3Wz">Intel SpeedStep</a> (CPUs)</li></ul> <p>Performance Boosting Technologies: </p> <ul><li><a href="/facts/AMD_Turbo_Core/1ql0h5BK">AMD Turbo Core</a> (CPUs)</li> <li><a href="/facts/Intel_Turbo_Boost/W9I2PUcg">Intel Turbo Boost</a> (CPUs)</li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>K. Moiseev, A. Kolodny and S. Wimer (September 2008). "Timing-aware power-optimal ordering of signals". ACM Transactions on Design Automation of Electronic Systems. 13 (4): 1–17. doi:10.1145/1391962.1391973. S2CID 18895687. <a href="/wiki/Doi_(identifier)" target="_blank">/wiki/Doi_(identifier)</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>Rabaey, J. M. (1996). Digital Integrated Circuits. Prentice Hall. <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>Victoria Zhislina (19 February 2014). "Why has CPU frequency ceased to grow?". Intel. <a href="https://software.intel.com/en-us/blogs/2014/02/19/why-has-cpu-frequency-ceased-to-grow" target="_blank">https://software.intel.com/en-us/blogs/2014/02/19/why-has-cpu-frequency-ceased-to-grow</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>https://www.usenix.org/legacy/events/hotpower/tech/full_papers/LeSueur.pdf [bare URL PDF] <a href="https://www.usenix.org/legacy/events/hotpower/tech/full_papers/LeSueur.pdf" target="_blank">https://www.usenix.org/legacy/events/hotpower/tech/full_papers/LeSueur.pdf</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>Karel De Vogeleer; Memmi, Gerard; Jouvelot, Pierre; Coelho, Fabien (2014). "The Energy/Frequency Convexity Rule: Modeling and Experimental Validation on Mobile Devices". arXiv:1401.4655 [cs.OH]. <a href="/wiki/ArXiv_(identifier)" target="_blank">/wiki/ArXiv_(identifier)</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>Mike Chin. "Asus EN9600GT Silent Edition Graphics Card". Silent PC Review. p. 5. Retrieved 21 April 2008. <a href="http://www.silentpcreview.com/article821-page5.html" target="_blank">http://www.silentpcreview.com/article821-page5.html</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>Mike Chin (19 March 2008). "80 Plus expands podium for Bronze, Silver & Gold". Silent PC Review. Retrieved 21 April 2008. <a href="http://www.silentpcreview.com/article814-page1.html" target="_blank">http://www.silentpcreview.com/article814-page1.html</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> <li id="fn:8"><p>"Advanced Configuration and Power Interface Specification, Revision 3.0, Section 2.6 Device and Processor Performance State Definitions" (PDF). ACPI.info. 2 September 2004. p. 23. Archived from the original (PDF) on 28 November 2015. Retrieved 19 August 2015. <a href="https://web.archive.org/web/20151128143452/http://www.acpi.info/DOWNLOADS/ACPIspec30.pdf" target="_blank">https://web.archive.org/web/20151128143452/http://www.acpi.info/DOWNLOADS/ACPIspec30.pdf</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></p></li> <li id="fn:9"><p>"Collaborative Processor Performance Control (CPPC) — The Linux Kernel documentation". www.kernel.org. <a href="https://www.kernel.org/doc/html/latest/admin-guide/acpi/cppc_sysfs.html" target="_blank">https://www.kernel.org/doc/html/latest/admin-guide/acpi/cppc_sysfs.html</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></p></li> <li id="fn:10"><p>"8.4. Declaring Processors". ACPI Specification 6.4 documentation. <a href="https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/08_Processor_Configuration_and_Control/declaring-processors.html#collaborative-processor-performance-control" target="_blank">https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/08_Processor_Configuration_and_Control/declaring-processors.html#collaborative-processor-performance-control</a> <a href="#fnref:10" class="footnote-back-ref">↩</a></p></li> <li id="fn:11"><p>"Overview about power and performance tuning for the Windows Server". learn.microsoft.com. 29 August 2022. <a href="https://learn.microsoft.com/en-us/windows-server/administration/performance-tuning/hardware/power/power-performance-tuning" target="_blank">https://learn.microsoft.com/en-us/windows-server/administration/performance-tuning/hardware/power/power-performance-tuning</a> <a href="#fnref:11" class="footnote-back-ref">↩</a></p></li> <li id="fn:12"><p>x86_energy_perf_policy(8) – Linux Programmer's Manual – Administration and Privileged Commands <a href="https://manned.org/x86_energy_perf_policy.8" target="_blank">https://manned.org/x86_energy_perf_policy.8</a> <a href="#fnref:12" class="footnote-back-ref">↩</a></p></li> <li id="fn:13"><p>"intel_pstate CPU Performance Scaling Driver — The Linux Kernel documentation". www.kernel.org. <a href="https://www.kernel.org/doc/html/v4.19/admin-guide/pm/intel_pstate.html" target="_blank">https://www.kernel.org/doc/html/v4.19/admin-guide/pm/intel_pstate.html</a> <a href="#fnref:13" class="footnote-back-ref">↩</a></p></li> <li id="fn:14"><p>"amd-pstate CPU Performance Scaling Driver — The Linux Kernel documentation". docs.kernel.org. <a href="https://docs.kernel.org/admin-guide/pm/amd-pstate.html" target="_blank">https://docs.kernel.org/admin-guide/pm/amd-pstate.html</a> <a href="#fnref:14" class="footnote-back-ref">↩</a></p></li> </ol>