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Zen (first generation)
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<h2 id="design">Design</h2> <p>According to <a href="/facts/AMD/CB1G7QTb">AMD</a>, the main focus of Zen is on increasing per-core performance.<a class="footnote-ref" id="fnref:9" href="#fn:9"><sup>9</sup></a><a class="footnote-ref" id="fnref:10" href="#fn:10"><sup>10</sup></a><a class="footnote-ref" id="fnref:11" href="#fn:11"><sup>11</sup></a> </p><p>New or improved features include:<a class="footnote-ref" id="fnref:12" href="#fn:12"><sup>12</sup></a> </p> <ul><li>The L1 cache has been changed from <a href="/facts/Cache_(computing)/gmJYN8wm">write-through</a> to write-back, allowing for lower latency and higher bandwidth.</li> <li><a href="/facts/Simultaneous_multithreading/bk8ec9yn">SMT (simultaneous multithreading)</a> architecture allows for two threads per core, a departure from the CMT (clustered multi-thread) design used in the previous <a href="/facts/Bulldozer_(microarchitecture)/fUPzoGrd">Bulldozer architecture</a>. This is a feature previously offered in some <a href="/facts/IBM/QszA7nwd">IBM</a>, <a href="/facts/Intel/SMF0gJJX">Intel</a> and <a href="/facts/Oracle_Corporation/0z14FygH">Oracle</a> processors.<a class="footnote-ref" id="fnref:13" href="#fn:13"><sup>13</sup></a></li> <li>A fundamental building block for all Zen-based CPUs is the <i>Core Complex</i> (CCX) consisting of four cores and their associated caches. Processors with more than four cores consist of multiple CCXs connected by <a href="/facts/Infinity_Fabric/6CPnQ1RL">Infinity Fabric</a>.<a class="footnote-ref" id="fnref:14" href="#fn:14"><sup>14</sup></a> Processors with non-multiple-of-four core counts have some cores disabled.</li> <li>Four <a href="/facts/Arithmetic_logic_unit/SgIjPzSc">ALUs</a>, two <a href="/facts/Address_generation_unit/KC7YYg8n">AGUs</a>/<a href="/facts/Load%25E2%2580%2593store_unit_(computing)/8QEBxzRl">load–store units</a>, and two <a href="/facts/Floating-point_unit/XWTW2AbF">floating-point units</a> per core.<a class="footnote-ref" id="fnref:15" href="#fn:15"><sup>15</sup></a></li> <li>Newly introduced "large" <a href="/facts/CPU_cache/x8BYFcdv">micro-operation cache</a>.<a class="footnote-ref" id="fnref:16" href="#fn:16"><sup>16</sup></a></li> <li>Each SMT core can dispatch up to six micro-ops per cycle (a combination of 6 <a href="/facts/Integer_(computer_science)/zWabo5M9">integer</a> micro-ops and 4 <a href="/facts/Floating_point/eIckahxe">floating point</a> micro-ops per cycle).<a class="footnote-ref" id="fnref:17" href="#fn:17"><sup>17</sup></a><a class="footnote-ref" id="fnref:18" href="#fn:18"><sup>18</sup></a></li> <li>Close to 2× faster L1 and L2 bandwidth, with total L3 cache bandwidth up 5×.</li> <li><a href="/facts/Clock_gating/u2nGKGPm">Clock gating</a>.</li> <li>Larger retire, load, and store queues.</li> <li>Improved <a href="/facts/Branch_prediction/pGPhFMj5">branch prediction</a> using a hashed <a href="/facts/Perceptron/ArxdkAC1">perceptron</a> system with Indirect Target Array similar to the Bobcat microarchitecture,<a class="footnote-ref" id="fnref:19" href="#fn:19"><sup>19</sup></a> something that has been compared to a <a href="/facts/Artificial_neural_network/6V1jMlkx">neural network</a> by AMD engineer Mike Clark.<a class="footnote-ref" id="fnref:20" href="#fn:20"><sup>20</sup></a></li> <li>The branch predictor is decoupled from the fetch stage.</li> <li>A dedicated <a href="/facts/Stack_engine/eWgwlmtz">stack engine</a> for modifying the <a href="/facts/Stack_pointer/1sMt713v">stack pointer</a>, similar to that of Intel Haswell and Broadwell processors.<a class="footnote-ref" id="fnref:21" href="#fn:21"><sup>21</sup></a></li> <li>Move elimination, a method that reduces physical data movement to reduce power consumption.</li> <li><a href="/facts/Binary_compatibility/7lkFAUfv">Binary compatibility</a> with Intel's <a href="/facts/Skylake_(microarchitecture)/qpcDcebM">Skylake</a> (excluding VT-x and private MSRs): <ul><li><a href="/facts/RDSEED/IdeN4y36">RDSEED</a> support, a set of high-performance hardware <a href="/facts/Random_number_generation/RtXEfbzd">random number generator</a> instructions introduced in Broadwell.<a class="footnote-ref" id="fnref:22" href="#fn:22"><sup>22</sup></a></li> <li>Support for the <a href="/facts/Supervisor_Mode_Access_Prevention/H8RSCNy2">SMAP</a>, SMEP, XSAVEC/XSAVES/XRSTORS, and CLFLUSHOPT instructions.<a class="footnote-ref" id="fnref:23" href="#fn:23"><sup>23</sup></a></li> <li><a href="/facts/Intel_ADX/7I3KDzYA">ADX</a> support.</li> <li><a href="/facts/Intel_SHA_extensions/qDzy2N70">SHA</a> support.</li></ul></li> <li>CLZERO instruction for clearing a cache line.<a class="footnote-ref" id="fnref:24" href="#fn:24"><sup>24</sup></a> Useful for handling ECC-related <a href="/facts/Machine-check_exception/8aLxkI6W">Machine-check exceptions</a>.</li> <li>PTE (<a href="/facts/Page_table/0IBU5cwg">page table</a> entry) <a href="/facts/Coalescing_(computer_science)/zpX2lMK1">coalescing</a>, which combines 4 kB page tables into 32 kB page size.</li> <li>"Pure Power" (more accurate power monitoring sensors).<a class="footnote-ref" id="fnref:25" href="#fn:25"><sup>25</sup></a> <ul><li>Support for intel-style running average power limit (RAPL) measurement.<a class="footnote-ref" id="fnref:26" href="#fn:26"><sup>26</sup></a></li></ul></li> <li>Smart Prefetch.</li> <li>Precision Boost.</li> <li>eXtended Frequency Range (XFR), an automated overclocking feature which boosts clock speeds beyond the advertised turbo frequency.<a class="footnote-ref" id="fnref:27" href="#fn:27"><sup>27</sup></a></li></ul> <blockquote><p>This is the first time in a very long time that we engineers have been given the total freedom to build a processor from scratch and do the best we can do. It is a multi-year project with a really large team. It's like a marathon effort with some sprints in the middle. The team is working very hard, but they can see the finish line. I guarantee that it will deliver a huge improvement in performance and power consumption over the previous generation.</p>— Suzanne Plummer, Zen team leader, on September 19th, 2015.<a class="footnote-ref" id="fnref:28" href="#fn:28"><sup>28</sup></a></blockquote> <p>The Zen architecture is built on a <a href="/facts/14_nanometer/lQYsD92n">14 nanometer</a> <a href="/facts/FinFET/xox63kP7">FinFET</a> process subcontracted to <a href="/facts/GlobalFoundries/lFTS5fbT">GlobalFoundries</a>,<a class="footnote-ref" id="fnref:29" href="#fn:29"><sup>29</sup></a> which in turn licenses its 14 nm process from <a href="/facts/Samsung_Electronics/STxnmHwl">Samsung Electronics</a>.<a class="footnote-ref" id="fnref:30" href="#fn:30"><sup>30</sup></a> This gives greater efficiency than the 32 nm and 28 nm processes of previous <a href="/facts/AMD_FX/uPMHuACf">AMD FX</a> CPUs and <a href="/facts/AMD_Accelerated_Processing_Unit/hdApEUQw">AMD APUs</a>, respectively.<a class="footnote-ref" id="fnref:31" href="#fn:31"><sup>31</sup></a> The "Summit Ridge" Zen family of CPUs use the AM4 socket and feature <a href="/facts/DDR4_SDRAM/70r37baX">DDR4</a> support and a 95 W TDP (<a href="/facts/Thermal_design_power/Idcy26tM">thermal design power</a>).<a class="footnote-ref" id="fnref:32" href="#fn:32"><sup>32</sup></a> While newer roadmaps don't confirm the TDP for desktop products, they suggest a range for low-power mobile products with up to two Zen cores from 5 to 15 W and 15 to 35 W for performance-oriented mobile products with up to four Zen cores.<a class="footnote-ref" id="fnref:33" href="#fn:33"><sup>33</sup></a> </p><p>Each Zen core can decode four <a href="/facts/Instructions_per_cycle/nHl8f6Ho">instructions per clock cycle</a> and includes a micro-op cache which feeds two schedulers, one each for the integer and <a href="/facts/Floating_point/eIckahxe">floating point</a> segments.<a class="footnote-ref" id="fnref:34" href="#fn:34"><sup>34</sup></a><a class="footnote-ref" id="fnref:35" href="#fn:35"><sup>35</sup></a> Each core has two address generation units, four integer units, and four floating point units. Two of the floating point units are adders, and two are multiply-adders. However, using multiply-add-operations may prevent simultaneous add operation in one of the adder units.<a class="footnote-ref" id="fnref:36" href="#fn:36"><sup>36</sup></a> There are also improvements in the branch predictor. The L1 cache size is 64 KB for instructions per core and 32 KB for data per core. The L2 cache size 512 KB per core, and the L3 is 1–2 MB per core. L3 caches offer 5× the bandwidth of previous AMD designs. </p> <h2 id="history-and-development">History and development</h2> <p>AMD began planning the Zen microarchitecture shortly after re-hiring <a href="/facts/Jim_Keller_(engineer)/q0FR1l6w">Jim Keller</a> in August 2012.<a class="footnote-ref" id="fnref:37" href="#fn:37"><sup>37</sup></a> AMD formally revealed Zen in 2015. </p><p>The team in charge of Zen was led by Keller (who left in September 2015 after a 3-year tenure) and Zen Team Leader Suzanne Plummer.<a class="footnote-ref" id="fnref:38" href="#fn:38"><sup>38</sup></a><a class="footnote-ref" id="fnref:39" href="#fn:39"><sup>39</sup></a> The Chief Architect of Zen was AMD Senior Fellow Michael Clark.<a class="footnote-ref" id="fnref:40" href="#fn:40"><sup>40</sup></a><a class="footnote-ref" id="fnref:41" href="#fn:41"><sup>41</sup></a><a class="footnote-ref" id="fnref:42" href="#fn:42"><sup>42</sup></a> </p><p>Zen was originally planned for 2017 following the ARM64-based <a href="/facts/AMD_K12/yqQh6QrC">K12</a> sister core, but on AMD's 2015 Financial Analyst Day it was revealed that K12 was delayed in favor of the Zen design, to allow it to enter the market within the 2016 timeframe,<a class="footnote-ref" id="fnref:43" href="#fn:43"><sup>43</sup></a> with the release of the first Zen-based processors expected for October 2016.<a class="footnote-ref" id="fnref:44" href="#fn:44"><sup>44</sup></a> </p><p>In November 2015, a source inside AMD reported that Zen microprocessors had been tested and "met all expectations" with "no significant bottlenecks found".<a class="footnote-ref" id="fnref:45" href="#fn:45"><sup>45</sup></a><a class="footnote-ref" id="fnref:46" href="#fn:46"><sup>46</sup></a> </p><p>In December 2015, it was rumored that Samsung may have been contracted as a fabricator for AMD's 14 nm FinFET processors, including both Zen and AMD's then-upcoming <a href="/facts/Polaris_(microarchitecture)/WYNvhDUP">Polaris</a> GPU architecture.<a class="footnote-ref" id="fnref:47" href="#fn:47"><sup>47</sup></a> This was clarified by AMD's July 2016 announcement that products had been successfully produced on Samsung's 14 nm FinFET process.<a class="footnote-ref" id="fnref:48" href="#fn:48"><sup>48</sup></a> AMD stated Samsung would be used "if needed", arguing this would reduce risk for AMD by decreasing dependence on any one foundry. </p><p>In December 2019, AMD started putting out first generation Ryzen products built using the second generation Zen+ architecture.<a class="footnote-ref" id="fnref:49" href="#fn:49"><sup>49</sup></a> </p> <h2 id="advantages-over-predecessors">Advantages over predecessors</h2> <h3>Manufacturing process</h3> <p>Processors based on Zen use 14 nm <a href="/facts/FinFET/xox63kP7">FinFET</a> silicon.<a class="footnote-ref" id="fnref:50" href="#fn:50"><sup>50</sup></a> These processors are reportedly produced at <a href="/facts/GlobalFoundries/lFTS5fbT">GlobalFoundries</a>.<a class="footnote-ref" id="fnref:51" href="#fn:51"><sup>51</sup></a> Prior to Zen, AMD's smallest process size was 28 nm, as utilized by their <a href="/facts/Steamroller_(microarchitecture)/SxtLaauz">Steamroller</a> and <a href="/facts/Excavator_(microarchitecture)/Bzj9WKGV">Excavator</a> microarchitectures.<a class="footnote-ref" id="fnref:52" href="#fn:52"><sup>52</sup></a><a class="footnote-ref" id="fnref:53" href="#fn:53"><sup>53</sup></a> The immediate competition, Intel's <a href="/facts/Skylake_(microarchitecture)/qpcDcebM">Skylake</a> and <a href="/facts/Kaby_Lake/DbfMWB0T">Kaby Lake</a> microarchitecture, are also fabricated on 14 nm FinFET;<a class="footnote-ref" id="fnref:54" href="#fn:54"><sup>54</sup></a> though Intel planned to begin the release of <a href="/facts/10_nanometer/h5qaJnz9">10 nm</a> parts later in 2017.<a class="footnote-ref" id="fnref:55" href="#fn:55"><sup>55</sup></a> Intel was unable to reach this goal, and in 2021, only mobile chips have been produced with the 10nm process. In comparison to Intel's 14 nm FinFET, AMD claimed in February 2017 the Zen cores would be 10% smaller.<a class="footnote-ref" id="fnref:56" href="#fn:56"><sup>56</sup></a> Intel has later announced in July 2018 that 10nm mainstream processors should not be expected before the second half of 2019.<a class="footnote-ref" id="fnref:57" href="#fn:57"><sup>57</sup></a> </p><p>For identical designs, these <a href="/facts/Die_shrink/fgJ8nL4b">die shrinks</a> would use less current (and power) at the same frequency (or voltage). As CPUs are usually power limited (typically up to ~125 W, or ~45 W for mobile), smaller transistors allow for either lower power at the same frequency, or higher frequency at the same power.<a class="footnote-ref" id="fnref:58" href="#fn:58"><sup>58</sup></a> </p> <h3>Performance</h3> <p>One of Zen's major goals in 2016 was to focus on performance per-core, and it was targeting a 40% improvement in <a href="/facts/Instructions_per_cycle/nHl8f6Ho">instructions per cycle (IPC)</a> over its predecessor.<a class="footnote-ref" id="fnref:59" href="#fn:59"><sup>59</sup></a> <a href="/facts/Excavator_(microarchitecture)/Bzj9WKGV">Excavator</a>, in comparison, offered 4–15% improvement over previous architectures.<a class="footnote-ref" id="fnref:60" href="#fn:60"><sup>60</sup></a><a class="footnote-ref" id="fnref:61" href="#fn:61"><sup>61</sup></a> AMD announced the final Zen microarchitecture actually achieved 52% improvement in IPC over Excavator.<a class="footnote-ref" id="fnref:62" href="#fn:62"><sup>62</sup></a> The inclusion of SMT also allows each core to process up to two threads, increasing processing throughput by better use of available resources. </p><p>The Zen processors also employ sensors across the chip to dynamically scale frequency and voltage.<a class="footnote-ref" id="fnref:63" href="#fn:63"><sup>63</sup></a> This allows for the maximum frequency to be dynamically and automatically defined by the processor itself based upon available cooling. </p><p>AMD has demonstrated an 8-core/16-thread Zen processor outperforming an equally-clocked <a href="/facts/Broadwell_(microarchitecture)/32jqNWRS">Intel Broadwell-E</a> processor in <a href="/facts/Blender_(software)/yzuvB0fL">Blender</a> rendering<a class="footnote-ref" id="fnref:64" href="#fn:64"><sup>64</sup></a><a class="footnote-ref" id="fnref:65" href="#fn:65"><sup>65</sup></a> and <a href="/facts/HandBrake/SYY3a9xX">HandBrake</a> benchmarks.<a class="footnote-ref" id="fnref:66" href="#fn:66"><sup>66</sup></a> </p><p>Zen supports <a href="/facts/AVX2/znDpc6Vt">AVX2</a> but it requires two clock cycles to complete each AVX2 instruction compared to Intel's one.<a class="footnote-ref" id="fnref:67" href="#fn:67"><sup>67</sup></a><a class="footnote-ref" id="fnref:68" href="#fn:68"><sup>68</sup></a> This difference was corrected in <a href="/facts/Zen_2/pdL7I80c">Zen 2</a>. </p> <h3>Memory</h3> <p>Zen supports <a href="/facts/DDR4_SDRAM/70r37baX">DDR4 memory</a> (up to eight channels)<a class="footnote-ref" id="fnref:69" href="#fn:69"><sup>69</sup></a> and <a href="/facts/ECC_memory/eG38xJoR">ECC</a>.<a class="footnote-ref" id="fnref:70" href="#fn:70"><sup>70</sup></a> </p><p>Pre-release reports stated APUs using the Zen architecture would also support <a href="/facts/High_Bandwidth_Memory/EgF2q99p">High Bandwidth Memory</a> (HBM).<a class="footnote-ref" id="fnref:71" href="#fn:71"><sup>71</sup></a> However, the first demonstrated APU did not use HBM.<a class="footnote-ref" id="fnref:72" href="#fn:72"><sup>72</sup></a> Previous APUs from AMD relied on shared memory for both the GPU and the CPU. </p> <h3>Power consumption and heat output</h3> <p>Processors built at the 14 nm node on FinFET silicon should show reduced power consumption and therefore heat over their 28 nm and 32 nm non-FinFET predecessors (for equivalent designs), or be more computationally powerful at equivalent heat output/power consumption. </p><p>Zen also uses <a href="/facts/Clock_gating/u2nGKGPm">clock gating</a>,<a class="footnote-ref" id="fnref:73" href="#fn:73"><sup>73</sup></a> reducing the frequency of underutilized portions of the core to save power. This comes from AMD's SenseMI technology, using sensors across the chip to dynamically scale frequency and voltage.<a class="footnote-ref" id="fnref:74" href="#fn:74"><sup>74</sup></a> </p> <h3>Enhanced security and virtualization support</h3> <p>Zen added support for AMD's Secure Memory Encryption (SME) and AMD's Secure Encrypted Virtualization (SEV). Secure Memory Encryption is real-time memory encryption done per page table entry. Encryption occurs on a hardware AES engine and keys are managed by the onboard "Security" Processor (<a href="/facts/ARM_Cortex-A5/F8QS0Phr">ARM Cortex-A5</a>) at boot time to encrypt each page, allowing any DDR4 memory (including non-volatile varieties) to be encrypted. AMD SME also makes the contents of the memory more resistant to memory snooping and <a href="/facts/Cold_boot_attack/vQ8jgrra">cold boot attacks</a>.<a class="footnote-ref" id="fnref:75" href="#fn:75"><sup>75</sup></a><a class="footnote-ref" id="fnref:76" href="#fn:76"><sup>76</sup></a> </p> <blockquote><p>SME can be used to mark individual pages of memory as encrypted through the page tables. A page of memory that is marked encrypted will be automatically decrypted when read from DRAM and will be automatically encrypted when written to DRAM. The SME feature is identified through a CPUID function and enabled through the SYSCFG MSR. Once enabled, page table entries will determine how the memory is accessed. If a page table entry has the memory encryption mask set, then that memory will be accessed as encrypted memory. The memory encryption mask (as well as other related information) is determined from settings returned through the same CPUID function that identifies the presence of the feature.<a class="footnote-ref" id="fnref:77" href="#fn:77"><sup>77</sup></a></p></blockquote> <p>The Secure Encrypted Virtualization (SEV) feature allows the memory contents of a virtual machine (VM) to be transparently encrypted with a key unique to the guest VM. The memory controller contains a high-performance encryption engine which can be programmed with multiple keys for use by different VMs in the system. The programming and management of these keys is handled by the AMD Secure Processor firmware which exposes an API for these tasks.<a class="footnote-ref" id="fnref:78" href="#fn:78"><sup>78</sup></a> </p> <h3>Connectivity</h3> <p>Incorporating much of the <a href="/facts/Southbridge_(computing)/K0bg0LSP">southbridge</a> into the <a href="/facts/System_on_a_Chip/1RVvVe6N">SoC</a>, the Zen CPU includes <a href="/facts/SATA/dW8yAMm8">SATA</a>, <a href="/facts/USB/XcIKWLyg">USB</a>, and <a href="/facts/PCI_Express/ADhsLCUK">PCI Express</a> <a href="/facts/NVMe/Ye7N4elE">NVMe</a> links.<a class="footnote-ref" id="fnref:79" href="#fn:79"><sup>79</sup></a><a class="footnote-ref" id="fnref:80" href="#fn:80"><sup>80</sup></a> This can be augmented by available <a href="/facts/List_of_AMD_chipsets/AesBnfxQ">Socket AM4 chipsets</a> which add connectivity options including additional SATA and USB connections, and support for <a href="/facts/AMD_CrossFireX/g0kg9ur0">AMD's Crossfire</a> and <a href="/facts/Scalable_Link_Interface/AdEeMsh2">Nvidia's SLI</a>.<a class="footnote-ref" id="fnref:81" href="#fn:81"><sup>81</sup></a> </p><p>AMD, in announcing its Radeon Instinct line, argued that the upcoming Zen-based Naples server CPU would be particularly suited for building <a href="/facts/Deep_learning/JLuwD3ea">deep learning</a> systems.<a class="footnote-ref" id="fnref:82" href="#fn:82"><sup>82</sup></a><a class="footnote-ref" id="fnref:83" href="#fn:83"><sup>83</sup></a> The 128<a class="footnote-ref" id="fnref:84" href="#fn:84"><sup>84</sup></a> <a href="/facts/PCIe/ADhsLCUK">PCIe</a> lanes per Naples CPU allows for eight <a href="/facts/Radeon_Instinct/awBes71U">Instinct cards</a> to connect at PCIe x16 to a single CPU. This compares favorably to the Intel Xeon line, with only 40 PCIe lanes. </p> <h2 id="features">Features</h2> <h3>CPUs</h3> <h3>APUs</h3> <p>APU features table </p> <h2 id="products">Products</h2> <p>The Zen architecture is used in the current-generation desktop <a href="/facts/Ryzen/0hKNcAra">Ryzen</a> CPUs. It is also in <a href="/facts/Epyc/5d30N0BK">Epyc</a> server processors (successor of <a href="/facts/Opteron/IF1ueyIJ">Opteron</a> processors), and APUs.<a class="footnote-ref" id="fnref:85" href="#fn:85"><sup>85</sup></a>[<i>unreliable source</i>]<a class="footnote-ref" id="fnref:86" href="#fn:86"><sup>86</sup></a><a class="footnote-ref" id="fnref:87" href="#fn:87"><sup>87</sup></a> </p><p>The first desktop processors without graphics processing units (codenamed "Summit Ridge") were initially expected to start selling at the end of 2016, according to an AMD roadmap; with the first mobile and desktop processors of the <a href="/facts/AMD_Accelerated_Processing_Unit/hdApEUQw">AMD Accelerated Processing Unit</a> type (codenamed "Raven Ridge") following in late 2017.<a class="footnote-ref" id="fnref:88" href="#fn:88"><sup>88</sup></a> AMD officially delayed Zen until Q1 of 2017. In August 2016, an early demonstration of the architecture showed an 8-core/16-thread engineering sample CPU at 3.0 GHz.<a class="footnote-ref" id="fnref:89" href="#fn:89"><sup>89</sup></a> </p><p>In December 2016, AMD officially announced the desktop CPU line under the <a href="/facts/Ryzen/0hKNcAra">Ryzen</a> brand for release in Q1 2017. It also confirmed Server processors would be released in Q2 2017, and mobile APUs in H2 2017.<a class="footnote-ref" id="fnref:90" href="#fn:90"><sup>90</sup></a> </p><p>On March 2, 2017, AMD officially launched the first Zen architecture-based octacore Ryzen desktop CPUs. The final clock speeds and TDPs for the 3 CPUs released in Q1 of 2017 demonstrated significant performance-per-watt benefits over the previous <a href="/facts/Piledriver_(microarchitecture)/Fhxly06H">K15h (Piledriver)</a> architecture.<a class="footnote-ref" id="fnref:91" href="#fn:91"><sup>91</sup></a><a class="footnote-ref" id="fnref:92" href="#fn:92"><sup>92</sup></a> The octacore Ryzen desktop CPUs demonstrated performance-per-watt comparable to Intel's Broadwell octacore CPUs.<a class="footnote-ref" id="fnref:93" href="#fn:93"><sup>93</sup></a><a class="footnote-ref" id="fnref:94" href="#fn:94"><sup>94</sup></a> </p><p>In March 2017, AMD also demonstrated an engineering sample of a server CPU based on the Zen architecture. The CPU (codenamed "Naples") was configured as a dual-socket server platform with each CPU having 32 cores/64 threads.<a class="footnote-ref" id="fnref:95" href="#fn:95"><sup>95</sup></a><a class="footnote-ref" id="fnref:96" href="#fn:96"><sup>96</sup></a> </p> <h3>Desktop processors</h3> <p class="note">Main article: <a href="/facts/Ryzen/0hKNcAra">Ryzen</a></p> <p>Common features of Ryzen 1000 desktop CPUs: </p> <ul><li>Socket: <a href="/facts/Socket_AM4/MuNKCgeF">AM4</a>.</li> <li>All the CPUs support <a href="/facts/DDR4_SDRAM/70r37baX">DDR4</a>-2666 in <a href="/facts/Multi-channel_memory_architecture/2XQeG01g">dual-channel</a> mode.</li> <li>All the CPUs support 24 <a href="/facts/PCI_Express/ADhsLCUK">PCIe 3.0</a> lanes. 4 of the lanes are reserved as link to the chipset.</li> <li>No integrated graphics.</li> <li>L1 <a href="/facts/Cache_(computing)/gmJYN8wm">cache</a>: 96 KB (32 KB data + 64 KB instruction) per core.</li> <li>L2 cache: 512 KB per core.</li> <li>Node/fabrication process: <a href="/facts/GlobalFoundries/lFTS5fbT">GlobalFoundries</a> <a href="/facts/14_nm_process/lQYsD92n">14 LP</a>.</li></ul> <table><tbody><tr><th colspan="2" rowspan="2">Branding and Model</th><th rowspan="2"><a href="/facts/Multi-core_processor/ABNb65hQ">Cores</a>(<a href="/facts/Thread_(computing)/hh8WHyPd">threads</a>)</th><th colspan="3"><a href="/facts/Clock_rate/w055Woaj">Clock rate</a> (<a href="/facts/Hertz/6Wshj5qm">GHz</a>)</th><th rowspan="2"><a href="/facts/Cache_(computing)/gmJYN8wm">L3 cache</a>(total)</th><th rowspan="2"><a href="/facts/Thermal_design_power/Idcy26tM">TDP</a></th><th rowspan="2">Coreconfig<a class="footnote-ref" id="fnref:97" href="#fn:97"><sup>97</sup></a></th><th rowspan="2">Releasedate</th><th rowspan="2">Launchprice<a class="footnote-ref" id="fnref:98" href="#fn:98"><sup>98</sup></a></th></tr><tr><th>Base</th><th>PBO1–2(≥3)</th><th>XFR<a class="footnote-ref" id="fnref:99" href="#fn:99"><sup>99</sup></a>1–2</th></tr><tr><th rowspan="5">Ryzen 7</th><th><a href="https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-1000-series/amd-ryzen-7-1800x.html">1800X</a><a class="footnote-ref" id="fnref:100" href="#fn:100"><sup>100</sup></a></th><td rowspan="5">8 (16)</td><td>3.6</td><td>4.0 (3.7)</td><td>4.1</td><td rowspan="10">16 MB</td><td rowspan="3">95 W</td><td rowspan="5">2 × 4</td><td>March 2, 2017</td><td>US $499</td></tr><tr><th><a href="https://www.amd.com/en/product/2011">PRO 1700X</a></th><td rowspan="2">3.4</td><td rowspan="2">3.8 (3.5)</td><td rowspan="2">3.9</td><td>June 29, 2017</td><td>OEM</td></tr><tr><th><a href="https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-1000-series/amd-ryzen-7-1700x.html">1700X</a><a class="footnote-ref" id="fnref:101" href="#fn:101"><sup>101</sup></a></th><td>March 2, 2017</td><td>US $399</td></tr><tr><th><a href="https://www.amd.com/en/product/2016">PRO 1700</a></th><td rowspan="2">3.0</td><td rowspan="2">3.7 (3.2)</td><td rowspan="2">3.75</td><td rowspan="2">65 W</td><td>June 29, 2017</td><td>OEM</td></tr><tr><th><a href="https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-1000-series/amd-ryzen-7-1700.html">1700</a><a class="footnote-ref" id="fnref:102" href="#fn:102"><sup>102</sup></a></th><td>March 2, 2017</td><td>US $329</td></tr><tr><th rowspan="6">Ryzen 5</th><th><a href="https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-1000-series/amd-ryzen-5-1600x.html">1600X</a><a class="footnote-ref" id="fnref:103" href="#fn:103"><sup>103</sup></a></th><td rowspan="3">6 (12)</td><td>3.6</td><td>4.0 (3.7)</td><td>4.1</td><td>95 W</td><td rowspan="3">2 × 3</td><td rowspan="1">April 11, 2017</td><td>US $249</td></tr><tr><th><a href="https://www.amd.com/en/product/2021">PRO 1600</a></th><td rowspan="2">3.2</td><td rowspan="2">3.6 (3.4)</td><td rowspan="2">3.7</td><td rowspan="9">65 W</td><td>June 29, 2017</td><td>OEM</td></tr><tr><th><a href="https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-1000-series/amd-ryzen-5-1600.html">1600</a><a class="footnote-ref" id="fnref:104" href="#fn:104"><sup>104</sup></a></th><td rowspan="2">April 11, 2017</td><td>US $219</td></tr><tr><th><a href="https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-1000-series/amd-ryzen-5-1500x.html">1500X</a><a class="footnote-ref" id="fnref:105" href="#fn:105"><sup>105</sup></a></th><td rowspan="3">4 (8)</td><td rowspan="2">3.5</td><td rowspan="2">3.7 (3.6)</td><td rowspan="2">3.9</td><td rowspan="7">2 × 2</td><td>US $189</td></tr><tr><th><a href="https://www.amd.com/en/product/2026">PRO 1500</a></th><td>June 29, 2017</td><td>OEM</td></tr><tr><th><a href="https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-1000-series/amd-ryzen-5-1400.html">1400</a><a class="footnote-ref" id="fnref:106" href="#fn:106"><sup>106</sup></a></th><td>3.2</td><td>3.4 (3.4)</td><td>3.45</td><td rowspan="5">8 MB</td><td>April 11, 2017</td><td>US $169</td></tr><tr><th rowspan="4">Ryzen 3</th><th><a href="https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-1000-series/amd-ryzen-3-1300x.html">1300X</a><a class="footnote-ref" id="fnref:107" href="#fn:107"><sup>107</sup></a></th><td rowspan="4">4 (4)</td><td rowspan="2">3.5</td><td rowspan="2">3.7 (3.5)</td><td rowspan="2">3.9</td><td>July 27, 2017</td><td>US $129</td></tr><tr><th><a href="https://www.amd.com/en/product/2031">PRO 1300</a></th><td rowspan="2">June 29, 2017</td><td rowspan="2">OEM</td></tr><tr><th><a href="https://www.amd.com/en/product/2036">PRO 1200</a></th><td rowspan="2">3.1</td><td rowspan="2">3.4 (3.1)</td><td rowspan="2">3.45</td></tr><tr><th><a href="https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-1000-series/amd-ryzen-3-1200.html">1200</a><a class="footnote-ref" id="fnref:108" href="#fn:108"><sup>108</sup></a></th><td>July 27, 2017</td><td>US $109</td></tr></tbody></table> <ul><li>v</li><li>t</li><li>e</li></ul> <p> Common features of Ryzen 1000 HEDT CPUs: </p> <ul><li>Socket: <a href="/facts/Socket_TR4/ETTnjzH3">TR4</a>.</li> <li>All the CPUs support <a href="/facts/DDR4_SDRAM/70r37baX">DDR4</a>-2666 in <a href="/facts/Multi-channel_memory_architecture/2XQeG01g">quad-channel</a> mode.</li> <li>All the CPUs support 64 <a href="/facts/PCI_Express/ADhsLCUK">PCIe 3.0</a> lanes. 4 of the lanes are reserved as link to the chipset.</li> <li>No integrated graphics.</li> <li>L1 <a href="/facts/Cache_(computing)/gmJYN8wm">cache</a>: 96 KB (32 KB data + 64 KB instruction) per core.</li> <li>L2 cache: 512 KB per core.</li> <li>Node/fabrication process: <a href="/facts/GlobalFoundries/lFTS5fbT">GlobalFoundries</a> <a href="/facts/14_nm_process/lQYsD92n">14LP</a>.</li></ul> <table><tbody><tr><th colspan="2" rowspan="2">Branding and Model</th><th rowspan="2"><a href="/facts/Multi-core_processor/ABNb65hQ">Cores</a>(<a href="/facts/Thread_(computing)/hh8WHyPd">threads</a>)</th><th colspan="3"><a href="/facts/Clock_rate/w055Woaj">Clock rate</a> (<a href="/facts/Hertz/6Wshj5qm">GHz</a>)</th><th rowspan="2"><a href="/facts/Cache_(computing)/gmJYN8wm">L3 cache</a>(total)</th><th rowspan="2"><a href="/facts/Thermal_design_power/Idcy26tM">TDP</a></th><th rowspan="2"><a href="/facts/Multi-chip_module/AzyVaNNp">Chiplets</a></th><th rowspan="2">Coreconfig<a class="footnote-ref" id="fnref:109" href="#fn:109"><sup>109</sup></a></th><th rowspan="2">Releasedate</th><th rowspan="2">Launchprice<a class="footnote-ref" id="fnref:110" href="#fn:110"><sup>110</sup></a></th></tr><tr><th>Base</th><th>PBO1–4(≥5)</th><th>XFR<a class="footnote-ref" id="fnref:111" href="#fn:111"><sup>111</sup></a>1–2</th></tr><tr><th rowspan="3">RyzenThreadripper</th><th><a href="https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen-threadripper/ryzen-threadripper-1000-series/amd-ryzen-threadripper-1950x.html">1950X</a><a class="footnote-ref" id="fnref:112" href="#fn:112"><sup>112</sup></a></th><td>16 (32)</td><td>3.4</td><td rowspan="2">4.0(3.7)</td><td rowspan="3">4.2</td><td rowspan="2">32 MB</td><td rowspan="3">180 W</td><td rowspan="3">2 × CCD<a class="footnote-ref" id="fnref:113" href="#fn:113"><sup>113</sup></a></td><td>4 × 4</td><td rowspan="2">August 10, 2017</td><td>US $999</td></tr><tr><th><a href="https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen-threadripper/ryzen-threadripper-1000-series/amd-ryzen-threadripper-1920x.html">1920X</a><a class="footnote-ref" id="fnref:114" href="#fn:114"><sup>114</sup></a></th><td>12 (24)</td><td>3.5</td><td>4 × 3</td><td>US $799</td></tr><tr><th><a href="https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen-threadripper/ryzen-threadripper-1000-series/amd-ryzen-threadripper-1900x.html">1900X</a><a class="footnote-ref" id="fnref:115" href="#fn:115"><sup>115</sup></a></th><td>8 (16)</td><td>3.8</td><td>4.0(3.9)</td><td>16 MB</td><td>2 × 4</td><td>August 31, 2017</td><td>US $549</td></tr></tbody></table> <ul><li>v</li><li>t</li><li>e</li></ul> <h3>Desktop APUs</h3> <p>Ryzen APUs are identified by either the G or GE suffix in their name. </p> <table><tbody><tr><th rowspan="3">Model</th><th rowspan="3">Release date& price</th><th rowspan="3"><a href="/facts/Semiconductor_device_fabrication/Jd23Mu1z">Fab</a></th><th rowspan="3">Thermal Solution</th><th colspan="6">CPU</th><th colspan="4">GPU</th><th rowspan="3"><a href="/facts/CPU_socket/ndWcsnq6">Socket</a></th><th rowspan="3"><a href="/facts/PCIe/ADhsLCUK">PCIe</a> lanes</th><th rowspan="3"><a href="/facts/Memory_controller/tHq2zlws">DDR4memorysupport</a></th><th rowspan="3"><a href="/facts/Thermal_design_power/Idcy26tM">TDP</a>(W)</th></tr><tr><th rowspan="2"><a href="/facts/Multi-core_processor/ABNb65hQ">Cores</a>(<a href="/facts/Thread_(computing)/hh8WHyPd">threads</a>)</th><th colspan="2"><a href="/facts/Clock_rate/w055Woaj">Clock rate</a> (<a href="/facts/Gigahertz/6Wshj5qm">GHz</a>)</th><th colspan="3"><a href="/facts/Cache_memory/gmJYN8wm">Cache</a></th><th rowspan="2">Model</th><th rowspan="2">Config<a class="footnote-ref" id="fnref:116" href="#fn:116"><sup>116</sup></a></th><th rowspan="2">Clock(GHz)</th><th rowspan="2">Processingpower(<a href="/facts/GFLOPS/6zYlH68F">GFLOPS</a>)<a class="footnote-ref" id="fnref:117" href="#fn:117"><sup>117</sup></a></th></tr><tr><th>Base</th><th>Boost</th><th><a href="/facts/L1_cache/x8BYFcdv">L1</a></th><th><a href="/facts/L2_cache/x8BYFcdv">L2</a></th><th><a href="/facts/L3_cache/x8BYFcdv">L3</a></th></tr><tr><th>Athlon 200GE<a class="footnote-ref" id="fnref:118" href="#fn:118"><sup>118</sup></a></th><td>September 6, 2018US $55</td><td rowspan="16"><a href="/facts/Global_Foundries/lFTS5fbT">GloFo</a><a href="/facts/14_nm_process/lQYsD92n">14LP</a></td><td>AMD 65W thermal solution</td><td rowspan="8">2 (4)</td><td rowspan="2">3.2</td><td rowspan="7">—</td><td rowspan="16">64 KB inst.32 KB dataper core</td><td rowspan="16">512 KBper core</td><td rowspan="16">4 MB</td><td rowspan="8">Vega 3</td><td rowspan="8">192:12:43 CU</td><td rowspan="4">1.0</td><td rowspan="4">384</td><td rowspan="16">AM4</td><td rowspan="16">16 (8+4+4)</td><td rowspan="7">2667dual-channel</td><td rowspan="10">35</td></tr><tr><th>Athlon Pro 200GE<a class="footnote-ref" id="fnref:119" href="#fn:119"><sup>119</sup></a></th><td>September 6, 2018OEM</td><td>OEM</td></tr><tr><th>Athlon 220GE<a class="footnote-ref" id="fnref:120" href="#fn:120"><sup>120</sup></a></th><td>December 21, 2018US $65</td><td rowspan="3">AMD 65W thermal solution</td><td>3.4</td></tr><tr><th>Athlon 240GE<a class="footnote-ref" id="fnref:121" href="#fn:121"><sup>121</sup></a></th><td>December 21, 2018US $75</td><td rowspan="2">3.5</td></tr><tr><th>Athlon 3000G<a class="footnote-ref" id="fnref:122" href="#fn:122"><sup>122</sup></a></th><td>November 19, 2019US $49</td><td rowspan="8">1.1</td><td rowspan="3">424.4</td></tr><tr><th>Athlon 300GE<a class="footnote-ref" id="fnref:123" href="#fn:123"><sup>123</sup></a></th><td>July 7, 2019OEM</td><td rowspan="5">OEM</td><td rowspan="2">3.4</td></tr><tr><th>Athlon Silver 3050GE<a class="footnote-ref" id="fnref:124" href="#fn:124"><sup>124</sup></a></th><td>July 21, 2020OEM</td></tr><tr><th>Ryzen 3 Pro 2100GE<a class="footnote-ref" id="fnref:125" href="#fn:125"><sup>125</sup></a></th><td>c. 2019<p>OEM</p></td><td>3.2</td><td>?</td><td>?</td><td rowspan="9">2933dual-channel</td></tr><tr><th>Ryzen 3 2200GE<a class="footnote-ref" id="fnref:126" href="#fn:126"><sup>126</sup></a></th><td>April 19, 2018OEM</td><td rowspan="4">4 (4)</td><td rowspan="2">3.2</td><td rowspan="2">3.6</td><td rowspan="4">Vega 8</td><td rowspan="4">512:32:168 CU</td><td rowspan="4">1126</td></tr><tr><th>Ryzen 3 Pro 2200GE<a class="footnote-ref" id="fnref:127" href="#fn:127"><sup>127</sup></a></th><td>May 10, 2018OEM</td></tr><tr><th>Ryzen 3 2200G</th><td>February 12, 2018US $99</td><td><a href="/facts/AMD_Wraith/xgRrUnQA">Wraith Stealth</a></td><td rowspan="2">3.5</td><td rowspan="2">3.7</td><td rowspan="2">45–65</td></tr><tr><th>Ryzen 3 Pro 2200G<a class="footnote-ref" id="fnref:128" href="#fn:128"><sup>128</sup></a></th><td>May 10, 2018OEM</td><td rowspan="3">OEM</td></tr><tr><th>Ryzen 5 2400GE<a class="footnote-ref" id="fnref:129" href="#fn:129"><sup>129</sup></a></th><td>April 19, 2018OEM</td><td rowspan="4">4 (8)</td><td rowspan="2">3.2</td><td rowspan="2">3.8</td><td rowspan="4">RX Vega 11</td><td rowspan="4">704:44:1611 CU</td><td rowspan="4">1.25</td><td rowspan="4">1760</td><td rowspan="2">35</td></tr><tr><th>Ryzen 5 Pro 2400GE<a class="footnote-ref" id="fnref:130" href="#fn:130"><sup>130</sup></a></th><td>May 10, 2018OEM</td></tr><tr><th>Ryzen 5 2400G<a class="footnote-ref" id="fnref:131" href="#fn:131"><sup>131</sup></a></th><td>February 12, 2018<a class="footnote-ref" id="fnref:132" href="#fn:132"><sup>132</sup></a><a class="footnote-ref" id="fnref:133" href="#fn:133"><sup>133</sup></a>US $169</td><td><a href="/facts/AMD_Wraith/xgRrUnQA">Wraith Stealth</a></td><td rowspan="2">3.6</td><td rowspan="2">3.9</td><td rowspan="2">45–65</td></tr><tr><th>Ryzen 5 Pro 2400G<a class="footnote-ref" id="fnref:134" href="#fn:134"><sup>134</sup></a></th><td>May 10, 2018OEM</td><td>OEM</td></tr></tbody></table> <ul><li>v</li><li>t</li><li>e</li></ul> <h3>Mobile APUs</h3> <table><tbody><tr><th rowspan="3">Model</th><th rowspan="3">Releasedate</th><th rowspan="3"><a href="/facts/Semiconductor_device_fabrication/Jd23Mu1z">Fab</a></th><th colspan="6">CPU</th><th colspan="4">GPU</th><th rowspan="3"><a href="/facts/CPU_socket/ndWcsnq6">Socket</a></th><th rowspan="3"><a href="/facts/PCI_Express/ADhsLCUK">PCIe</a>lanes</th><th rowspan="3"><a href="/facts/Memory_controller/tHq2zlws">Memorysupport</a></th><th rowspan="3"><a href="/facts/Thermal_design_power/Idcy26tM">TDP</a></th></tr><tr><th rowspan="2"><a href="/facts/Multi-core_processor/ABNb65hQ">Cores</a>(<a href="/facts/Thread_(computing)/hh8WHyPd">threads</a>)</th><th colspan="2"><a href="/facts/Clock_rate/w055Woaj">Clock rate</a> (<a href="/facts/Hertz/6Wshj5qm">GHz</a>)</th><th colspan="3"><a href="/facts/Cache_(computing)/gmJYN8wm">Cache</a></th><th rowspan="2">Model</th><th rowspan="2">Config<a class="footnote-ref" id="fnref:135" href="#fn:135"><sup>135</sup></a></th><th rowspan="2">Clock(<a href="/facts/Hertz/6Wshj5qm">MHz</a>)</th><th rowspan="2">Processingpower(<a href="/facts/FLOPS/6zYlH68F">GFLOPS</a>)<a class="footnote-ref" id="fnref:136" href="#fn:136"><sup>136</sup></a></th></tr><tr><th>Base</th><th>Boost</th><th><a href="/facts/L2_cache/x8BYFcdv">L1</a></th><th><a href="/facts/L2_cache/x8BYFcdv">L2</a></th><th><a href="/facts/L3_cache/x8BYFcdv">L3</a></th></tr><tr><th><a href="https://www.amd.com/en/product/8201">Athlon Pro 200U</a></th><td>2019</td><td rowspan="12"><a href="/facts/GlobalFoundries/lFTS5fbT">GloFo</a><a href="/facts/14_nm_process/lQYsD92n">14LP</a></td><td rowspan="4">2 (4)</td><td>2.3</td><td>3.2</td><td rowspan="12">64 KB inst.32 KB dataper core</td><td rowspan="12">512 KBper core</td><td rowspan="12">4 MB</td><td rowspan="4">Radeon Vega 3</td><td rowspan="4">192:12:43 CU</td><td rowspan="2">1000</td><td rowspan="2">384</td><td rowspan="12">FP5</td><td rowspan="12">12 (8+4)</td><td rowspan="8">DDR4-2400<a href="/facts/Dual-channel_architecture/2XQeG01g">dual-channel</a></td><td rowspan="8">12–25 W</td></tr><tr><th><a href="https://www.amd.com/en/product/8356">Athlon 300U</a></th><td>Jan 6, 2019</td><td>2.4</td><td>3.3</td></tr><tr><th><a href="https://www.amd.com/en/product/7231">Ryzen 3 2200U</a></th><td>Jan 8, 2018</td><td>2.5</td><td>3.4</td><td>1100</td><td>422.4</td></tr><tr><th><a href="https://www.amd.com/en/product/8351">Ryzen 3 3200U</a></th><td>Jan 6, 2019</td><td>2.6</td><td>3.5</td><td>1200</td><td>460.8</td></tr><tr><th><a href="https://www.amd.com/en/product/7236">Ryzen 3 2300U</a></th><td>Jan 8, 2018</td><td rowspan="2">4 (4)</td><td rowspan="4">2.0</td><td rowspan="2">3.4</td><td rowspan="2">Radeon Vega 6</td><td rowspan="2">384:24:86 CU</td><td rowspan="5">1100</td><td rowspan="2">844.8</td></tr><tr><th><a href="https://www.amd.com/en/product/7216">Ryzen 3 Pro 2300U</a></th><td>May 15, 2018</td></tr><tr><th><a href="https://www.amd.com/en/product/5311">Ryzen 5 2500U</a></th><td>Oct 26, 2017</td><td rowspan="6">4 (8)</td><td rowspan="3">3.6</td><td rowspan="3">Radeon Vega 8</td><td rowspan="3">512:32:168 CU</td><td rowspan="3">1126.4</td></tr><tr><th><a href="https://www.amd.com/en/product/7211">Ryzen 5 Pro 2500U</a></th><td>May 15, 2018</td></tr><tr><th><a href="https://www.amd.com/en/product/8256">Ryzen 5 2600H</a></th><td>Sep 10, 2018</td><td>3.2</td><td>DDR4-3200dual-channel</td><td>35–54 W</td></tr><tr><th><a href="https://www.amd.com/en/product/5306">Ryzen 7 2700U</a></th><td>Oct 26, 2017</td><td rowspan="2">2.2</td><td rowspan="3">3.8</td><td>Radeon RX Vega 10</td><td rowspan="2">640:40:1610 CU</td><td rowspan="3">1300</td><td rowspan="2">1664</td><td rowspan="2">DDR4-2400dual-channel</td><td rowspan="2">12–25 W</td></tr><tr><th><a href="https://www.amd.com/en/product/7206">Ryzen 7 Pro 2700U</a></th><td>May 15, 2018</td><td>Radeon Vega 10</td></tr><tr><th><a href="https://www.amd.com/en/product/8251">Ryzen 7 2800H</a></th><td>Sep 10, 2018</td><td>3.3</td><td>Radeon RX Vega 11</td><td>704:44:1611 CU</td><td>1830.4</td><td>DDR4-3200dual-channel</td><td>35–54 W</td></tr></tbody></table> <ul><li>v</li><li>t</li><li>e</li></ul> <h3>Ultra-mobile APUs</h3> <h4>Dalí</h4> <table><tbody><tr><th rowspan="3">Model</th><th rowspan="3">Releasedate</th><th rowspan="3"><a href="/facts/Semiconductor_device_fabrication/Jd23Mu1z">Fab</a></th><th colspan="6">CPU</th><th colspan="4">GPU</th><th rowspan="3"><a href="/facts/CPU_socket/ndWcsnq6">Socket</a></th><th rowspan="3"><a href="/facts/PCI_Express/ADhsLCUK">PCIe</a>lanes</th><th rowspan="3"><a href="/facts/Memory_controller/tHq2zlws">Memorysupport</a></th><th rowspan="3"><a href="/facts/Thermal_design_power/Idcy26tM">TDP</a></th><th rowspan="3">Part number</th></tr><tr><th rowspan="2"><a href="/facts/Multi-core_processor/ABNb65hQ">Cores</a>(<a href="/facts/Thread_(computing)/hh8WHyPd">threads</a>)</th><th colspan="2"><a href="/facts/Clock_rate/w055Woaj">Clock rate</a> (<a href="/facts/Hertz/6Wshj5qm">GHz</a>)</th><th colspan="3"><a href="/facts/Cache_memory/gmJYN8wm">Cache</a></th><th rowspan="2">Model</th><th rowspan="2">Config<a class="footnote-ref" id="fnref:137" href="#fn:137"><sup>137</sup></a></th><th rowspan="2">Clock(GHz)</th><th rowspan="2">Processingpower(<a href="/facts/FLOPS/6zYlH68F">GFLOPS</a>)<a class="footnote-ref" id="fnref:138" href="#fn:138"><sup>138</sup></a></th></tr><tr><th>Base</th><th>Boost</th><th><a href="/facts/L1_cache/x8BYFcdv">L1</a></th><th><a href="/facts/L2_cache/x8BYFcdv">L2</a></th><th><a href="/facts/L3_cache/x8BYFcdv">L3</a></th></tr><tr><th><a href="https://www.amd.com/en/product/9901">AMD 3020e</a></th><td>Jan 6, 2020</td><td rowspan="10">14 nm</td><td rowspan="4">2 (2)</td><td>1.2</td><td>2.6</td><td rowspan="10">64 KB inst.32 KB dataper core</td><td rowspan="10">512 KBper core</td><td rowspan="10">4 MB</td><td rowspan="10">RadeonGraphics(Vega)</td><td>192:12:43 CU</td><td>1.0</td><td>384</td><td rowspan="10">FP5</td><td rowspan="10">12 (8+4)</td><td rowspan="10">DDR4-2400<a href="/facts/Dual-channel_architecture/2XQeG01g">dual-channel</a></td><td>6 W</td><td>YM3020C7T2OFG</td></tr><tr><th><a href="https://www.amd.com/en/product/10901">Athlon PRO 3045B</a></th><td>Q1 2021</td><td rowspan="3">2.3</td><td rowspan="3">3.2</td><td rowspan="3">128:8:42 CU</td><td rowspan="3">1.1</td><td rowspan="3">281.6</td><td rowspan="3">15 W</td><td>YM3045C4T2OFG</td></tr><tr><th><a href="https://www.amd.com/en/product/9056">Athlon Silver 3050U</a></th><td>Jan 6, 2020</td><td>YM3050C4T2OFG</td></tr><tr><th><a href="https://www.amd.com/en/product/9071">Athlon Silver 3050C</a></th><td>Sep 22, 2020</td><td>YM305CC4T2OFG</td></tr><tr><th><a href="https://www.amd.com/en/product/9896">Athlon Silver 3050e</a></th><td>Jan 6, 2020</td><td rowspan="6">2 (4)</td><td>1.4</td><td>2.8</td><td rowspan="6">192:12:43 CU<a class="footnote-ref" id="fnref:139" href="#fn:139"><sup>139</sup></a></td><td rowspan="4">1.0</td><td rowspan="4">384</td><td>6 W</td><td>YM3050C7T2OFG</td></tr><tr><th><a href="https://www.amd.com/en/product/10896">Athlon PRO 3145B</a></th><td>Q1 2021</td><td rowspan="3">2.4</td><td rowspan="3">3.3</td><td rowspan="5">15 W</td><td>YM3145C4T2OFG</td></tr><tr><th><a href="https://www.amd.com/en/product/9061">Athlon Gold 3150U</a></th><td>Jan 6, 2020</td><td>YM3150C4T2OFG</td></tr><tr><th><a href="https://www.amd.com/en/product/9076">Athlon Gold 3150C</a></th><td>Sep 22, 2020</td><td>YM315CC4T2OFG</td></tr><tr><th><a href="https://www.amd.com/en/product/9051">Ryzen 3 3250U</a></th><td>Jan 6, 2020</td><td rowspan="2">2.6</td><td rowspan="2">3.5</td><td rowspan="2">1.2</td><td rowspan="2">460.8</td><td>YM3250C4T2OFG</td></tr><tr><th><a href="https://www.amd.com/en/product/9066">Ryzen 3 3250C</a></th><td>Sep 22, 2020</td><td>YM325CC4T2OFG</td></tr></tbody></table> <ul><li>v</li><li>t</li><li>e</li></ul> <h4>Pollock</h4> <table><tbody><tr><th rowspan="3">Model</th><th rowspan="3">Releasedate</th><th rowspan="3"><a href="/facts/Semiconductor_device_fabrication/Jd23Mu1z">Fab</a></th><th colspan="6">CPU</th><th colspan="4">GPU</th><th rowspan="3"><a href="/facts/CPU_socket/ndWcsnq6">Socket</a></th><th rowspan="3"><a href="/facts/PCI_Express/ADhsLCUK">PCIe</a>lanes</th><th rowspan="3"><a href="/facts/Memory_controller/tHq2zlws">Memorysupport</a></th><th rowspan="3"><a href="/facts/Thermal_design_power/Idcy26tM">TDP</a></th><th rowspan="3">Part number</th></tr><tr><th rowspan="2"><a href="/facts/Multi-core_processor/ABNb65hQ">Cores</a>(<a href="/facts/Thread_(computing)/hh8WHyPd">threads</a>)</th><th colspan="2"><a href="/facts/Clock_rate/w055Woaj">Clock rate</a> (<a href="/facts/Hertz/6Wshj5qm">GHz</a>)</th><th colspan="3"><a href="/facts/Cache_memory/gmJYN8wm">Cache</a></th><th rowspan="2">Model</th><th rowspan="2">Config<a class="footnote-ref" id="fnref:140" href="#fn:140"><sup>140</sup></a></th><th rowspan="2">Clock(GHz)</th><th rowspan="2">Processingpower(<a href="/facts/FLOPS/6zYlH68F">GFLOPS</a>)<a class="footnote-ref" id="fnref:141" href="#fn:141"><sup>141</sup></a></th></tr><tr><th>Base</th><th>Boost</th><th><a href="/facts/L1_cache/x8BYFcdv">L1</a></th><th><a href="/facts/L2_cache/x8BYFcdv">L2</a></th><th><a href="/facts/L3_cache/x8BYFcdv">L3</a></th></tr><tr><th><a href="https://www.amd.com/en/product/10166">AMD 3015e</a></th><td>Jul 6, 2020</td><td rowspan="2">14 nm</td><td rowspan="2">2 (4)</td><td rowspan="2">1.2</td><td rowspan="2">2.3</td><td rowspan="2">64 KB inst.32 KB dataper core</td><td rowspan="2">512 KBper core</td><td rowspan="2">4 MB</td><td rowspan="2">RadeonGraphics(Vega)</td><td rowspan="2">192:12:43 CU</td><td rowspan="2">0.6</td><td rowspan="2">230.4</td><td rowspan="2">FT5</td><td rowspan="2">12 (8+4)</td><td rowspan="2">DDR4-1600single-channel</td><td rowspan="2">6 W</td><td>AM3015BRP2OFJ</td></tr><tr><th><a href="https://www.amd.com/en/product/11201">AMD 3015Ce</a></th><td>Apr 29, 2021</td><td>AM301CBRP2OFJ</td></tr></tbody></table> <ul><li>v</li><li>t</li><li>e</li></ul> <h3>Embedded processors</h3> <h4>V1000</h4> <p>In February 2018, AMD announced the V1000 series of embedded Zen+Vega APUs with four SKUs.<a class="footnote-ref" id="fnref:142" href="#fn:142"><sup>142</sup></a> (And three more SKUs in December that year.) </p> <table><tbody><tr><th rowspan="3">Model</th><th rowspan="3">Releasedate</th><th rowspan="3"><a href="/facts/Semiconductor_device_fabrication/Jd23Mu1z">Fab</a></th><th colspan="6">CPU</th><th colspan="4">GPU</th><th rowspan="3"><a href="/facts/Memory_controller/tHq2zlws">Memorysupport</a></th><th rowspan="3"><a href="/facts/Thermal_design_power/Idcy26tM">TDP</a></th><th rowspan="3"><a href="/facts/Junction_temperature/9F6XFYEP">Junctiontemp.range</a>(°C)</th></tr><tr><th rowspan="2"><a href="/facts/Multi-core_processor/ABNb65hQ">Cores</a>(<a href="/facts/Thread_(computing)/hh8WHyPd">threads</a>)</th><th colspan="2"><a href="/facts/Clock_rate/w055Woaj">Clock rate</a> (<a href="/facts/Gigahertz/6Wshj5qm">GHz</a>)</th><th colspan="3"><a href="/facts/Cache_memory/gmJYN8wm">Cache</a></th><th rowspan="2">Model</th><th rowspan="2">Config<a class="footnote-ref" id="fnref:143" href="#fn:143"><sup>143</sup></a></th><th rowspan="2">Clock(GHz)</th><th rowspan="2">Processingpower(<a href="/facts/GFLOPS/6zYlH68F">GFLOPS</a>)<a class="footnote-ref" id="fnref:144" href="#fn:144"><sup>144</sup></a></th></tr><tr><th>Base</th><th>Boost</th><th><a href="/facts/L1_cache/x8BYFcdv">L1</a></th><th><a href="/facts/L2_cache/x8BYFcdv">L2</a></th><th><a href="/facts/L3_cache/x8BYFcdv">L3</a></th></tr><tr><th><a href="https://www.amd.com/en/product/7291">V1202B</a></th><td>February 2018</td><td rowspan="7"><a href="/facts/Global_Foundries/lFTS5fbT">GloFo</a><a href="/facts/14_nm_process/lQYsD92n">14LP</a></td><td>2 (4)</td><td>2.3</td><td>3.2</td><td rowspan="7">64 KB inst.32 KB dataper core</td><td rowspan="7">512 KBper core</td><td rowspan="7">4 MB</td><td>Vega 3</td><td>192:12:163 CU</td><td>1.0</td><td>384</td><td rowspan="4">DDR4-2400<a href="/facts/Multi-channel_memory_architecture/2XQeG01g">dual-channel</a></td><td rowspan="4">12–25 W</td><td>0–105</td></tr><tr><th><a href="https://www.amd.com/en/product/9126">V1404I</a></th><td rowspan="2">December 2018</td><td rowspan="6">4 (8)</td><td>2.0</td><td>3.6</td><td>Vega 8</td><td rowspan="1">512:32:168 CU</td><td rowspan="1">1.1</td><td rowspan="1">1126.4</td><td>-40–105</td></tr><tr><th><a href="https://www.amd.com/en/product/8496">V1500B</a></th><td>2.2</td><td>—</td><td rowspan="1" colspan="4">—</td><td rowspan="5">0–105</td></tr><tr><th><a href="https://www.amd.com/en/product/7281">V1605B</a></th><td rowspan="2">February 2018</td><td>2.0</td><td rowspan="3">3.6</td><td rowspan="2">Vega 8</td><td rowspan="2">512:32:168 CU</td><td rowspan="2">1.1</td><td rowspan="2">1126.4</td></tr><tr><th><a href="https://www.amd.com/en/product/7276">V1756B</a></th><td>3.25</td><td rowspan="3">DDR4-3200dual-channel</td><td rowspan="3">35–54 W</td></tr><tr><th><a href="https://www.amd.com/en/product/8491">V1780B</a></th><td>December 2018</td><td rowspan="2">3.35</td><td rowspan="1" colspan="4">—</td></tr><tr><th><a href="https://www.amd.com/en/product/7271">V1807B</a></th><td>February 2018</td><td>3.8</td><td>Vega 11</td><td>704:44:1611 CU</td><td>1.3</td><td>1830.4</td></tr></tbody></table> <ul><li>v</li><li>t</li><li>e</li></ul> <h4>R1000</h4> <p>In 2019, AMD announced the R1000 series of embedded Zen+Vega APUs. </p> <table><tbody><tr><th rowspan="3">Model</th><th rowspan="3">Releasedate</th><th rowspan="3"><a href="/facts/Semiconductor_device_fabrication/Jd23Mu1z">Fab</a></th><th colspan="6">CPU</th><th colspan="4">GPU</th><th rowspan="3"><a href="/facts/Memory_controller/tHq2zlws">Memorysupport</a></th><th rowspan="3"><a href="/facts/Thermal_design_power/Idcy26tM">TDP</a></th></tr><tr><th rowspan="2"><a href="/facts/Multi-core_processor/ABNb65hQ">Cores</a>(<a href="/facts/Thread_(computing)/hh8WHyPd">threads</a>)</th><th colspan="2"><a href="/facts/Clock_rate/w055Woaj">Clock rate</a> (<a href="/facts/Gigahertz/6Wshj5qm">GHz</a>)</th><th colspan="3"><a href="/facts/Cache_memory/gmJYN8wm">Cache</a></th><th rowspan="2">Model</th><th rowspan="2">Config<a class="footnote-ref" id="fnref:145" href="#fn:145"><sup>145</sup></a></th><th rowspan="2">Clock(GHz)</th><th rowspan="2">Processingpower(<a href="/facts/GFLOPS/6zYlH68F">GFLOPS</a>)<a class="footnote-ref" id="fnref:146" href="#fn:146"><sup>146</sup></a></th></tr><tr><th>Base</th><th>Boost</th><th><a href="/facts/L1_cache/x8BYFcdv">L1</a></th><th><a href="/facts/L2_cache/x8BYFcdv">L2</a></th><th><a href="/facts/L3_cache/x8BYFcdv">L3</a></th></tr><tr><th><a href="https://www.amd.com/en/product/9226">R1102G</a></th><td rowspan="2">February 25, 2020</td><td rowspan="4"><a href="/facts/Global_Foundries/lFTS5fbT">GloFo</a>14LP</td><td>2 (2)</td><td>1.2</td><td>2.6</td><td rowspan="4">64 KB inst.32 KB dataper core</td><td rowspan="4">512 KBper core</td><td rowspan="4">4 MB</td><td rowspan="4">Vega 3</td><td rowspan="4">192:12:43 CU</td><td rowspan="3">1.0</td><td rowspan="3">384</td><td>DDR4-2400single-channel</td><td>6 W</td></tr><tr><th><a href="https://www.amd.com/en/product/9221">R1305G</a></th><td rowspan="3">2 (4)</td><td>1.5</td><td>2.8</td><td rowspan="3">DDR4-2400<a href="/facts/Multi-channel_memory_architecture/2XQeG01g">dual-channel</a></td><td>8-10 W</td></tr><tr><th><a href="https://www.amd.com/en/product/8431">R1505G</a></th><td rowspan="2">April 16, 2019</td><td>2.4</td><td>3.3</td><td rowspan="2">12–25 W</td></tr><tr><th><a href="https://www.amd.com/en/product/8426">R1606G</a></th><td>2.6</td><td>3.5</td><td>1.2</td><td>460.8</td></tr></tbody></table> <ul><li>v</li><li>t</li><li>e</li></ul> <h3>Server processors</h3> <p class="note">Main article: <a href="/facts/Epyc/5d30N0BK">Epyc</a></p> <p>AMD announced in March 2017 that it would release a server platform based on Zen, codenamed Naples, in the second quarter of the year. The platform include 1- and 2-socket systems. The CPUs in multi-processor configurations communicate via AMD's Infinity Fabric.<a class="footnote-ref" id="fnref:147" href="#fn:147"><sup>147</sup></a> Each chip supports eight channels of memory and 128 PCIe 3.0 lanes, of which 64 lanes are used for CPU-to-CPU communication through Infinity Fabric when installed in a dual-processor configuration.<a class="footnote-ref" id="fnref:148" href="#fn:148"><sup>148</sup></a> AMD officially revealed Naples under the brand name Epyc in May 2017.<a class="footnote-ref" id="fnref:149" href="#fn:149"><sup>149</sup></a> </p><p>On June 20, 2017, AMD officially released the Epyc 7000 series CPUs at a launch event in Austin, Texas.<a class="footnote-ref" id="fnref:150" href="#fn:150"><sup>150</sup></a> Common features: </p> <ul><li><a href="/facts/Socket_SP3/2SCApC28">SP3</a> socket</li> <li>Zen microarchitecture</li> <li><a href="/facts/GlobalFoundries/lFTS5fbT">GloFo</a> <a href="/facts/14_nm_process/lQYsD92n">14 nm process</a></li> <li><a href="/facts/Multi-chip_module/AzyVaNNp">MCM</a> with four <a href="/facts/System_on_a_chip/1RVvVe6N">System-on-a-chip</a> (SOC) dies, two core complexes (CCX) per SOC die<a class="footnote-ref" id="fnref:151" href="#fn:151"><sup>151</sup></a></li> <li><a href="/facts/Multi-channel_memory_architecture/2XQeG01g">Eight-channel</a> DDR4-2666 (the 7251 model is limited to DDR4-2400)</li> <li>128 PCIe 3.0 lanes per socket, 64 of which are used for <a href="/facts/Infinity_Fabric/6CPnQ1RL">Infinity Fabric</a> inter-processor links in 2P platforms</li> <li>7001P series models are limited to uniprocessor operation (<i>1P</i>)</li></ul> <table><tbody><tr><th scope="col" rowspan="2">Model</th><th scope="col" rowspan="2"><a href="/facts/Multi-core_processor/ABNb65hQ">Cores</a>(<a href="/facts/Thread_(computing)/hh8WHyPd">threads</a>)</th><th scope="col" rowspan="2"><a href="/facts/Multi-chip_module/AzyVaNNp">Chiplets</a></th><th scope="col" rowspan="2">Coreconfig<a class="footnote-ref" id="fnref:152" href="#fn:152"><sup>152</sup></a></th><th colspan="2"><a href="/facts/Clock_rate/w055Woaj">Clock rate</a></th><th colspan="3"><a href="/facts/Cache_(computing)/gmJYN8wm">Cache size</a></th><th scope="col" rowspan="2">Socket</th><th scope="col" rowspan="2">Scaling</th><th scope="col" rowspan="2"><a href="/facts/Thermal_design_power/Idcy26tM">TDP</a></th><th scope="col" rowspan="2">Releasedate</th><th scope="col" rowspan="2">Releaseprice</th><th scope="col" rowspan="2">Embeddedoptions<a class="footnote-ref" id="fnref:153" href="#fn:153"><sup>153</sup></a></th></tr><tr><th scope="col">Base(GHz)</th><th scope="col">Boost(GHz)</th><th scope="col"><a href="/facts/L2_cache/x8BYFcdv">L2</a>per core</th><th scope="col"><a href="/facts/L3_cache/x8BYFcdv">L3</a>per CCX</th><th scope="col">Total</th></tr><tr><th scope="row">7251<a class="footnote-ref" id="fnref:154" href="#fn:154"><sup>154</sup></a><a class="footnote-ref" id="fnref:155" href="#fn:155"><sup>155</sup></a></th><td rowspan="2"> 8 (16)</td><td rowspan="12">4<a class="footnote-ref" id="fnref:156" href="#fn:156"><sup>156</sup></a></td><td rowspan="2"> 8 × 1</td><td>2.1</td><td>2.9</td><td rowspan="12">512 KB</td><td>4 MB</td><td>36 MB</td><td rowspan="12"> SP3</td><td>2P</td><td>120 W</td><td>Jun 2017<a class="footnote-ref" id="fnref:157" href="#fn:157"><sup>157</sup></a></td><td> $475</td><td>7251</td></tr><tr><th scope="row">7261<a class="footnote-ref" id="fnref:158" href="#fn:158"><sup>158</sup></a><a class="footnote-ref" id="fnref:159" href="#fn:159"><sup>159</sup></a></th><td>2.5</td><td>2.9</td><td>8 MB</td><td>68 MB</td><td>2P</td><td>155/170 W</td><td>Jun 2018<a class="footnote-ref" id="fnref:160" href="#fn:160"><sup>160</sup></a></td><td> $570</td><td>7261</td></tr><tr><th scope="row">7281<a class="footnote-ref" id="fnref:161" href="#fn:161"><sup>161</sup></a><a class="footnote-ref" id="fnref:162" href="#fn:162"><sup>162</sup></a></th><td rowspan="4">16 (32)</td><td rowspan="4"> 8 × 2</td><td>2.1</td><td>2.7</td><td>4 MB</td><td>40 MB</td><td>2P</td><td rowspan="3">155/170 W</td><td rowspan="3">Jun 2017<a class="footnote-ref" id="fnref:163" href="#fn:163"><sup>163</sup></a></td><td> $650</td><td>7281</td></tr><tr><th scope="row">7301<a class="footnote-ref" id="fnref:164" href="#fn:164"><sup>164</sup></a><a class="footnote-ref" id="fnref:165" href="#fn:165"><sup>165</sup></a></th><td>2.2</td><td>2.7</td><td rowspan="3">8 MB</td><td rowspan="3">72 MB</td><td>2P</td><td> $800</td><td>7301</td></tr><tr><th scope="row">7351(P)<a class="footnote-ref" id="fnref:166" href="#fn:166"><sup>166</sup></a><a class="footnote-ref" id="fnref:167" href="#fn:167"><sup>167</sup></a></th><td>2.4</td><td>2.9</td><td>2P (1P)</td><td>$1100 ($750)</td><td>7351(735P)</td></tr><tr><th scope="row">7371<a class="footnote-ref" id="fnref:168" href="#fn:168"><sup>168</sup></a><a class="footnote-ref" id="fnref:169" href="#fn:169"><sup>169</sup></a></th><td>3.1</td><td>3.8</td><td>2P</td><td>200 W</td><td>Nov 2018<a class="footnote-ref" id="fnref:170" href="#fn:170"><sup>170</sup></a></td><td>$1550</td><td>7371</td></tr><tr><th scope="row">7401(P)<a class="footnote-ref" id="fnref:171" href="#fn:171"><sup>171</sup></a><a class="footnote-ref" id="fnref:172" href="#fn:172"><sup>172</sup></a></th><td rowspan="2">24 (48)</td><td rowspan="2"> 8 × 3</td><td>2.0</td><td>3.0</td><td rowspan="2">8 MB</td><td rowspan="2">76 MB</td><td>2P (1P)</td><td>155/170 W</td><td rowspan="2">Jun 2017<a class="footnote-ref" id="fnref:173" href="#fn:173"><sup>173</sup></a></td><td>$1850 ($1075)</td><td>7401(740P)</td></tr><tr><th scope="row">7451<a class="footnote-ref" id="fnref:174" href="#fn:174"><sup>174</sup></a><a class="footnote-ref" id="fnref:175" href="#fn:175"><sup>175</sup></a></th><td>2.3</td><td>3.2</td><td>2P</td><td>180 W</td><td>$2400</td><td>7451</td></tr><tr><th scope="row">7501<a class="footnote-ref" id="fnref:176" href="#fn:176"><sup>176</sup></a><a class="footnote-ref" id="fnref:177" href="#fn:177"><sup>177</sup></a></th><td rowspan="4">32 (64)</td><td rowspan="4"> 8 × 4</td><td>2.0</td><td>3.0</td><td rowspan="4">8 MB</td><td rowspan="4">80 MB</td><td>2P</td><td>155/170 W</td><td rowspan="2">Jun 2017<a class="footnote-ref" id="fnref:178" href="#fn:178"><sup>178</sup></a></td><td>$3400</td><td>7501</td></tr><tr><th scope="row">7551(P)<a class="footnote-ref" id="fnref:179" href="#fn:179"><sup>179</sup></a><a class="footnote-ref" id="fnref:180" href="#fn:180"><sup>180</sup></a></th><td>2.0</td><td>3.0</td><td>2P (1P)</td><td>180 W</td><td>$3400 ($2100)</td><td>7551(755P)</td></tr><tr><th scope="row">7571<a class="footnote-ref" id="fnref:181" href="#fn:181"><sup>181</sup></a><a class="footnote-ref" id="fnref:182" href="#fn:182"><sup>182</sup></a></th><td>2.2</td><td>3.0</td><td>2P</td><td>200 W</td><td>Nov 2018</td><td>OEM/<a href="/facts/Amazon_Web_Services/UFVN2796">AWS</a></td><td>--</td></tr><tr><th scope="row">7601<a class="footnote-ref" id="fnref:183" href="#fn:183"><sup>183</sup></a><a class="footnote-ref" id="fnref:184" href="#fn:184"><sup>184</sup></a></th><td>2.2</td><td>3.2</td><td>2P</td><td>180 W</td><td>Jun 2017<a class="footnote-ref" id="fnref:185" href="#fn:185"><sup>185</sup></a></td><td>$4200</td><td>7601</td></tr></tbody></table> <ul><li>v</li><li>t</li><li>e</li></ul> <h3>Embedded server processors</h3> <p>In February 2018, AMD also announced the EPYC 3000 series of embedded Zen CPUs.<a class="footnote-ref" id="fnref:186" href="#fn:186"><sup>186</sup></a>Common features of EPYC Embedded 3000 series CPUs: </p> <ul><li>Socket: SP4 (31xx and 32xx models use SP4r2 package).</li> <li>All the CPUs support <a href="/facts/ECC_memory/eG38xJoR">ECC</a> <a href="/facts/DDR4_SDRAM/70r37baX">DDR4</a>-2666 in <a href="/facts/Multi-channel_memory_architecture/2XQeG01g">dual-channel</a> mode (3201 supports only DDR4-2133), while 33xx and 34xx models support quad-channel mode.</li> <li>L1 <a href="/facts/Cache_(computing)/gmJYN8wm">cache</a>: 96 KB (32 KB data + 64 KB instruction) per core.</li> <li>L2 cache: 512 KB per core.</li> <li>All the CPUs support 32 <a href="/facts/PCI_Express/ADhsLCUK">PCIe 3.0</a> lanes per CCD (max 64 lanes).</li> <li>Fabrication process: <a href="/facts/GlobalFoundries/lFTS5fbT">GlobalFoundries</a> <a href="/facts/14_nm_process/lQYsD92n">14 nm</a>.</li></ul> <table><tbody><tr><th rowspan="3">Model</th><th rowspan="3"><a href="/facts/Multi-core_processor/ABNb65hQ">Cores</a>(<a href="/facts/Thread_(computing)/hh8WHyPd">threads</a>)</th><th colspan="3"><a href="/facts/Clock_rate/w055Woaj">Clock rate</a> (<a href="/facts/Hertz/6Wshj5qm">GHz</a>)</th><th rowspan="3"><a href="/facts/Cache_(computing)/gmJYN8wm">L3 cache</a>(total)</th><th rowspan="3"><a href="/facts/Thermal_design_power/Idcy26tM">TDP</a></th><th rowspan="3"><a href="/facts/Multi-chip_module/AzyVaNNp">Chiplets</a></th><th rowspan="3">Coreconfig<a class="footnote-ref" id="fnref:187" href="#fn:187"><sup>187</sup></a></th><th rowspan="3">Releasedate</th></tr><tr><th rowspan="2">Base</th><th colspan="2">Boost</th></tr><tr><th>All-core</th><th>Max</th></tr><tr><th><a href="https://www.amd.com/en/product/7266">3101</a><a class="footnote-ref" id="fnref:188" href="#fn:188"><sup>188</sup></a></th><td>4 (4)</td><td>2.1</td><td rowspan="2">2.9</td><td rowspan="2">2.9</td><td>8 MB</td><td>35 W</td><td rowspan="5">1 × CCD</td><td>1 × 4</td><td rowspan="4">Feb 2018</td></tr><tr><th><a href="https://www.amd.com/en/product/7261">3151</a><a class="footnote-ref" id="fnref:189" href="#fn:189"><sup>189</sup></a></th><td>4 (8)</td><td>2.7</td><td rowspan="4">16 MB</td><td>45 W</td><td>2 × 2</td></tr><tr><th><a href="https://www.amd.com/en/product/7256">3201</a><a class="footnote-ref" id="fnref:190" href="#fn:190"><sup>190</sup></a></th><td>8 (8)</td><td>1.5</td><td rowspan="3">3.1</td><td rowspan="3">3.1</td><td>30 W</td><td rowspan="3">2 × 4</td></tr><tr><th><a href="https://www.amd.com/en/product/7251">3251</a><a class="footnote-ref" id="fnref:191" href="#fn:191"><sup>191</sup></a></th><td rowspan="2">8 (16)</td><td rowspan="2">2.5</td><td>55 W</td></tr><tr><th><a href="https://www.amd.com/en/product/8856">3255</a><a class="footnote-ref" id="fnref:192" href="#fn:192"><sup>192</sup></a></th><td>25–55 W</td><td>Dec 2018</td></tr><tr><th>3301<a class="footnote-ref" id="fnref:193" href="#fn:193"><sup>193</sup></a></th><td>12 (12)</td><td>2.0</td><td>2.15</td><td rowspan="4">3.0</td><td rowspan="4">32 MB</td><td>65 W</td><td rowspan="4">2 × CCD</td><td rowspan="2">4 × 3</td><td rowspan="4">Feb 2018</td></tr><tr><th><a href="https://www.amd.com/en/product/9011">3351</a><a class="footnote-ref" id="fnref:194" href="#fn:194"><sup>194</sup></a></th><td>12 (24)</td><td>1.9</td><td>2.75</td><td>60–80 W</td></tr><tr><th>3401<a class="footnote-ref" id="fnref:195" href="#fn:195"><sup>195</sup></a></th><td>16 (16)</td><td>1.85</td><td>2.25</td><td>85 W</td><td rowspan="2">4 × 4</td></tr><tr><th><a href="https://www.amd.com/en/product/9006">3451</a><a class="footnote-ref" id="fnref:196" href="#fn:196"><sup>196</sup></a></th><td>16 (32)</td><td>2.15</td><td>2.45</td><td>80–100 W</td></tr></tbody></table> <ul><li>v</li><li>t</li><li>e</li></ul> <h2 id="see-also">See also</h2> Wikimedia Commons has media related to Zen microarchitecture. <ul><li><a href="/facts/AMD_K9/cokIE6Sg">AMD K9</a></li> <li><a href="/facts/AMD_K10/2hQAazep">AMD K10</a></li> <li><a href="/facts/Jim_Keller_(engineer)/q0FR1l6w">Jim Keller (engineer)</a></li> <li><a href="/facts/Ryzen/0hKNcAra">Ryzen</a></li> <li><a href="/facts/Steamroller_(microarchitecture)/SxtLaauz">Steamroller (microarchitecture)</a></li> <li><a href="/facts/Zen%252B/1bJfQtRR">Zen+</a></li> <li><a href="/facts/Zen_2/pdL7I80c">Zen 2</a></li></ul> <h2 id="external-links">External links</h2> <ul><li><a href="https://www.amd.com/en-us/innovations/software-technologies/zen-cpu">Ryzen Processors</a> – AMD</li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>Anthony, Sebastian (18 August 2016). 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Tech Report. Archived from the original on 18 November 2016. Retrieved 18 August 2016. <a href="https://techreport.com/review/30540/amd-gives-us-our-first-real-moment-of-zen" target="_blank">https://techreport.com/review/30540/amd-gives-us-our-first-real-moment-of-zen</a> <a href="#fnref:96" class="footnote-back-ref">↩</a></p></li> <li id="fn:97"><p>Core Complexes (CCX) × cores per CCX <a href="#fnref:97" class="footnote-back-ref">↩</a></p></li> <li id="fn:98"><p>Manufacturer suggested retail price at launch <a href="/wiki/Manufacturer_suggested_retail_price" target="_blank">/wiki/Manufacturer_suggested_retail_price</a> <a href="#fnref:98" class="footnote-back-ref">↩</a></p></li> <li id="fn:99"><p>Chen, Sam (February 13, 2020). "What is XFR? (AMD)". Gear Primer. Retrieved June 11, 2020. <a href="https://www.gearprimer.com/wiki/xfr/" target="_blank">https://www.gearprimer.com/wiki/xfr/</a> <a href="#fnref:99" class="footnote-back-ref">↩</a></p></li> <li id="fn:100"><p>Safford, Matt. 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Retrieved 14 May 2024. <a href="https://www.guru3d.com/review/amd-ryzen-3-1200-and-1300x-review" target="_blank">https://www.guru3d.com/review/amd-ryzen-3-1200-and-1300x-review</a> <a href="#fnref:108" class="footnote-back-ref">↩</a></p></li> <li id="fn:109"><p>Core Complexes (CCX) × cores per CCX <a href="#fnref:109" class="footnote-back-ref">↩</a></p></li> <li id="fn:110"><p>Manufacturer suggested retail price at launch <a href="/wiki/Manufacturer_suggested_retail_price" target="_blank">/wiki/Manufacturer_suggested_retail_price</a> <a href="#fnref:110" class="footnote-back-ref">↩</a></p></li> <li id="fn:111"><p>Chen, Sam (February 13, 2020). "What is XFR? (AMD)". Gear Primer. Retrieved June 11, 2020. <a href="https://www.gearprimer.com/wiki/xfr/" target="_blank">https://www.gearprimer.com/wiki/xfr/</a> <a href="#fnref:111" class="footnote-back-ref">↩</a></p></li> <li id="fn:112"><p>Ung, Gordon Mah (6 September 2017). "AMD Ryzen Threadripper: Everything we know so far about this monster CPU". PCWorld. Retrieved 14 May 2024. <a href="https://www.pcworld.com/article/406810/amd-ryzen-threadripper-prices-specs-release-date-and-more.html" target="_blank">https://www.pcworld.com/article/406810/amd-ryzen-threadripper-prices-specs-release-date-and-more.html</a> <a href="#fnref:112" class="footnote-back-ref">↩</a></p></li> <li id="fn:113"><p>Processor package actually contains two additional inactive dies to provide structural support to the integrated heat spreader. <a href="#fnref:113" class="footnote-back-ref">↩</a></p></li> <li id="fn:114"><p>Ung, Gordon Mah (6 September 2017). "AMD Ryzen Threadripper: Everything we know so far about this monster CPU". PCWorld. Retrieved 14 May 2024. <a href="https://www.pcworld.com/article/406810/amd-ryzen-threadripper-prices-specs-release-date-and-more.html" target="_blank">https://www.pcworld.com/article/406810/amd-ryzen-threadripper-prices-specs-release-date-and-more.html</a> <a href="#fnref:114" class="footnote-back-ref">↩</a></p></li> <li id="fn:115"><p>Ung, Gordon Mah (6 September 2017). "AMD Ryzen Threadripper: Everything we know so far about this monster CPU". PCWorld. Retrieved 14 May 2024. <a href="https://www.pcworld.com/article/406810/amd-ryzen-threadripper-prices-specs-release-date-and-more.html" target="_blank">https://www.pcworld.com/article/406810/amd-ryzen-threadripper-prices-specs-release-date-and-more.html</a> <a href="#fnref:115" class="footnote-back-ref">↩</a></p></li> <li id="fn:116"><p>Unified Shaders : Texture Mapping Units : Render Output Units and Compute Units (CU) <a href="/wiki/Unified_shader_model" target="_blank">/wiki/Unified_shader_model</a> <a href="#fnref:116" class="footnote-back-ref">↩</a></p></li> <li id="fn:117"><p>Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation. <a href="/wiki/Single-precision_floating-point_format" target="_blank">/wiki/Single-precision_floating-point_format</a> <a href="#fnref:117" class="footnote-back-ref">↩</a></p></li> <li id="fn:118"><p>"AMD Athlon 200GE Processor with Radeon Vega 3 Graphics". AMD. <a href="https://www.amd.com/en/products/apu/amd-athlon-200ge" target="_blank">https://www.amd.com/en/products/apu/amd-athlon-200ge</a> <a href="#fnref:118" class="footnote-back-ref">↩</a></p></li> <li id="fn:119"><p>"AMD Athlon PRO 200GE APU". AMD. <a href="https://www.amd.com/en/products/apu/amd-athlon-pro-200ge" target="_blank">https://www.amd.com/en/products/apu/amd-athlon-pro-200ge</a> <a href="#fnref:119" class="footnote-back-ref">↩</a></p></li> <li id="fn:120"><p>"AMD Athlon 220GE Processor with Radeon Vega 3 Graphics". <a href="https://www.amd.com/en/products/apu/amd-athlon-220ge" target="_blank">https://www.amd.com/en/products/apu/amd-athlon-220ge</a> <a href="#fnref:120" class="footnote-back-ref">↩</a></p></li> <li id="fn:121"><p>"AMD Athlon 240GE Processor with Radeon Vega 3 Graphics". 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