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NAND logic
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<h2 id="nand">NAND</h2> <p class="note">Main article: <a href="/facts/NAND_gate/g6FUuhJT">NAND gate</a></p> <p>A NAND gate is an inverted <a href="/facts/AND_gate/tVKQD0w1">AND gate</a>. It has the following truth table: </p> <table><tbody><tr><td></td></tr><tr><td colspan="2"><p>Q = A NAND B</p>Truth Table<table><tbody><tr><th>Input A</th><th>Input B</th><th>Output Q</th></tr><tr><td>0</td><td>0</td><td>1</td></tr><tr><td>0</td><td>1</td><td>1</td></tr><tr><td>1</td><td>0</td><td>1</td></tr><tr><td>1</td><td>1</td><td>0</td></tr></tbody></table></td></tr></tbody></table> <p>In <a href="/facts/CMOS/NJIWYgBl">CMOS</a> logic, if both of the A and B inputs are high, then both the <a href="/facts/N-channel/TerYC6Nz">NMOS</a> <a href="/facts/Transistors/Bmr8zwL0">transistors</a> (bottom half of the diagram) will conduct, neither of the <a href="/facts/P-channel/TerYC6Nz">PMOS</a> transistors (top half) will conduct, and a conductive path will be established between the output and Vss (ground), bringing the output low. If both of the A and B inputs are low, then neither of the NMOS transistors will conduct, while both of the PMOS transistors will conduct, establishing a conductive path between the output and Vdd (voltage source), bringing the output high. If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the PMOS transistors will, and a conductive path will be established between the output and Vdd (voltage source), bringing the output high. As the only configuration of the two inputs that results in a low output is when both are high, this circuit implements a NAND (NOT AND) logic gate. </p> <h2 id="making-other-gates-by-using-nand-gates">Making other gates by using NAND gates</h2> <p>A NAND gate is a <a href="/facts/Universal_gate/RHLulvKI">universal gate</a>, meaning that any other gate can be represented as a combination of NAND gates. </p> <h3>NOT</h3> <p class="note">See also: <a href="/facts/NOT_gate/pGk3qGTI">NOT gate</a></p> <p>A NOT gate is made by joining the inputs of a NAND gate together. Since a NAND gate is equivalent to an AND gate followed by a NOT gate, joining the inputs of a NAND gate leaves only the NOT gate. </p> <table><tbody><tr><th>Desired NOT Gate</th><th>NAND Construction</th></tr><tr><td></td><td></td></tr><tr><td>Q = NOT( A )</td><td>= A NAND A</td></tr><tr><td colspan="2">Truth Table<table><tbody><tr><th>Input A</th><th>Output Q</th></tr><tr><td>0</td><td>1</td></tr><tr><td>1</td><td>0</td></tr></tbody></table></td></tr></tbody></table> <h3>AND</h3> <p class="note">See also: <a href="/facts/AND_gate/tVKQD0w1">AND gate</a></p> <p>An AND gate is made by inverting the output of a NAND gate as shown below. </p> <table><tbody><tr><th>Desired AND Gate</th><th>NAND Construction</th></tr><tr><td></td><td></td></tr><tr><td>Q = A AND B</td><td>= ( A NAND B ) NAND ( A NAND B )</td></tr><tr><td colspan="2">Truth Table<table><tbody><tr><th>Input A</th><th>Input B</th><th>Output Q</th></tr><tr><td>0</td><td>0</td><td>0</td></tr><tr><td>0</td><td>1</td><td>0</td></tr><tr><td>1</td><td>0</td><td>0</td></tr><tr><td>1</td><td>1</td><td>1</td></tr></tbody></table></td></tr></tbody></table> <h3>OR</h3> <p class="note">See also: <a href="/facts/OR_gate/ox2lHgIM">OR gate</a></p> <p>If the truth table for a NAND gate is examined or by applying <a href="/facts/De_Morgan%27s_laws/dj3F8xpt">De Morgan's laws</a>, it can be seen that if any of the inputs are 0, then the output will be 1. To be an OR gate, however, the output must be 1 if any input is 1. Therefore, if the inputs are inverted, any high input will trigger a high output. </p> <table><tbody><tr><th>Desired OR Gate</th><th>NAND Construction</th></tr><tr><td></td><td></td></tr><tr><td>Q = A OR B</td><td>= ( A NAND A ) NAND ( B NAND B )</td></tr><tr><td colspan="2">Truth Table<table><tbody><tr><th>Input A</th><th>Input B</th><th>Output Q</th></tr><tr><td>0</td><td>0</td><td>0</td></tr><tr><td>0</td><td>1</td><td>1</td></tr><tr><td>1</td><td>0</td><td>1</td></tr><tr><td>1</td><td>1</td><td>1</td></tr></tbody></table></td></tr></tbody></table> <h3>NOR</h3> <p class="note">See also: <a href="/facts/NOR_gate/3l3MqaMI">NOR gate</a></p> <p>A NOR gate is an OR gate with an inverted output. Output is high when neither input A nor input B is high. </p> <table><tbody><tr><th>Desired NOR Gate</th><th>NAND Construction</th></tr><tr><td></td><td></td></tr><tr><td>Q = A NOR B</td><td>= [ ( A NAND A ) NAND ( B NAND B ) ] NAND [ ( A NAND A ) NAND ( B NAND B ) ]</td></tr><tr><td colspan="2">Truth Table<table><tbody><tr><th>Input A</th><th>Input B</th><th>Output Q</th></tr><tr><td>0</td><td>0</td><td>1</td></tr><tr><td>0</td><td>1</td><td>0</td></tr><tr><td>1</td><td>0</td><td>0</td></tr><tr><td>1</td><td>1</td><td>0</td></tr></tbody></table></td></tr></tbody></table> <h3>XOR</h3> <p class="note">See also: <a href="/facts/XOR_gate/WSfdqTcA">XOR gate</a></p> <p>An XOR gate is made by connecting four NAND gates as shown below. This construction entails a propagation delay three times that of a single NAND gate. </p> <table><tbody><tr><th>Desired XOR Gate</th><th>NAND Construction</th></tr><tr><td></td><td></td></tr><tr><td>Q = A XOR B</td><td>= [ A NAND ( A NAND B ) ] NAND [ B NAND ( A NAND B ) ]</td></tr><tr><td colspan="2">Truth Table<table><tbody><tr><th>Input A</th><th>Input B</th><th>Output Q</th></tr><tr><td>0</td><td>0</td><td>0</td></tr><tr><td>0</td><td>1</td><td>1</td></tr><tr><td>1</td><td>0</td><td>1</td></tr><tr><td>1</td><td>1</td><td>0</td></tr></tbody></table></td></tr></tbody></table> <p>Alternatively, an XOR gate is made by considering the <a href="/facts/Disjunctive_normal_form/hsw2pRPu">disjunctive normal form</a> A ⋅ B ¯ + A ¯ ⋅ B {\displaystyle A\cdot {\overline {B}}+{\overline {A}}\cdot B} , noting from <a href="/facts/De_Morgan%27s_law/dj3F8xpt">de Morgan's law</a> that a NAND gate is an inverted-input OR gate. This construction uses five gates instead of four. </p> <table><tbody><tr><th>Desired Gate</th><th>NAND Construction</th></tr><tr><td></td><td></td></tr><tr><td>Q = A XOR B</td><td>= [ B NAND ( A NAND A ) ] NAND [ A NAND ( B NAND B ) ]</td></tr></tbody></table> <h3>XNOR</h3> <p class="note">See also: <a href="/facts/XNOR_gate/LW793PwY">XNOR gate</a></p> <p>An XNOR gate is made by considering the <a href="/facts/Disjunctive_normal_form/hsw2pRPu">disjunctive normal form</a> A ⋅ B + A ¯ ⋅ B ¯ {\displaystyle A\cdot B+{\overline {A}}\cdot {\overline {B}}} , noting from <a href="/facts/De_Morgan%27s_law/dj3F8xpt">de Morgan's law</a> that a NAND gate is an inverted-input OR gate. This construction entails a propagation delay three times that of a single NAND gate and uses five gates. </p> <table><tbody><tr><th>Desired XNOR Gate</th><th>NAND Construction</th></tr><tr><td></td><td></td></tr><tr><td>Q = A XNOR B</td><td>= [ ( A NAND A ) NAND ( B NAND B ) ] NAND ( A NAND B )</td></tr><tr><td colspan="2"><table><tbody><tr><th>Input A</th><th>Input B</th><th>Output Q</th></tr><tr><td>0</td><td>0</td><td>1</td></tr><tr><td>0</td><td>1</td><td>0</td></tr><tr><td>1</td><td>0</td><td>0</td></tr><tr><td>1</td><td>1</td><td>1</td></tr></tbody></table></td></tr></tbody></table> <p>Alternatively, the 4-gate version of the XOR gate can be used with an inverter. This construction has a propagation delay four times (instead of three times) that of a single NAND gate. </p> <table><tbody><tr><th>Desired Gate</th><th>NAND Construction</th></tr><tr><td></td><td></td></tr><tr><td>Q = A XNOR B</td><td>= { [ A NAND ( A NAND B ) ] NAND [ B NAND ( A NAND B ) ] } NAND { [ A NAND ( A NAND B ) ] NAND [ B NAND ( A NAND B ) ] }</td></tr></tbody></table> <h2 id="mux">MUX</h2> <p>A <a href="/facts/Multiplexer/lVro0Sfz">multiplexer</a> or a MUX gate is a three-input gate that uses one of the inputs, called the <i>selector bit,</i> to select one of the other two inputs, called <i>data bits</i>, and outputs only the selected data bit.<a class="footnote-ref" id="fnref:1" href="#fn:1"><sup>1</sup></a> </p> <table><tbody><tr><th>Desired MUX Gate</th><th>NAND Construction</th></tr><tr><td>Q = [ A AND NOT( S ) ] OR ( B AND S )</td><td>= [ A NAND ( S NAND S ) ] NAND ( B NAND S )</td></tr><tr><td></td><td></td></tr><tr><td colspan="2">Truth Table<table><tbody><tr><th>Input A</th><th>Input B</th><th>Select</th><th>Output Q</th></tr><tr><td>0</td><td>0</td><td>0</td><td>0</td></tr><tr><td>0</td><td>1</td><td>0</td><td>0</td></tr><tr><td>1</td><td>0</td><td>0</td><td>1</td></tr><tr><td>1</td><td>1</td><td>0</td><td>1</td></tr><tr><td>0</td><td>0</td><td>1</td><td>0</td></tr><tr><td>0</td><td>1</td><td>1</td><td>1</td></tr><tr><td>1</td><td>0</td><td>1</td><td>0</td></tr><tr><td>1</td><td>1</td><td>1</td><td>1</td></tr></tbody></table></td></tr></tbody></table> <h2 id="demux">DEMUX</h2> <p>A demultiplexer performs the opposite function of a multiplexer: It takes a single input and channels it to one of two possible outputs according to a selector bit that specifies which output to choose.<a class="footnote-ref" id="fnref:2" href="#fn:2"><sup>2</sup></a>[<i>copyright violation?</i>] </p> <table><tbody><tr><th>Desired DEMUX Gate</th><th>NAND Construction</th></tr><tr><td></td><td></td></tr><tr><td></td><td></td></tr><tr><td colspan="2">Truth Table<table><tbody><tr><th>Input</th><th>Select</th><th>Output A</th><th>Output B</th></tr><tr><td>0</td><td>0</td><td>0</td><td>0</td></tr><tr><td>1</td><td>0</td><td>1</td><td>0</td></tr><tr><td>0</td><td>1</td><td>0</td><td>0</td></tr><tr><td>1</td><td>1</td><td>0</td><td>1</td></tr></tbody></table></td></tr></tbody></table> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/CMOS/NJIWYgBl">CMOS</a> transistor structures and chip deposition geometries that produce NAND logic elements</li> <li><a href="/facts/Sheffer_stroke/rpXH07u4">Sheffer stroke</a> – other name</li> <li><a href="/facts/NOR_logic/GhHdKb4q">NOR logic</a> – like NAND gates, NOR gates are also universal gates</li> <li><a href="/facts/Functional_completeness/ncyHAsHH">Functional completeness</a></li></ul> <ul><li><a href="/facts/Don_Lancaster/K2SguGNX">Lancaster, Don</a> (1974). <a href="https://archive.org/details/ttlcookbook00lanc/page/126"><i>TTL Cookbook</i></a> (1st ed.). Indianapolis, IN: Howard W Sams. pp. <a href="https://archive.org/details/ttlcookbook00lanc/page/126">126–135</a>. <a href="/facts/ISBN_(identifier)/15AdSPa9">ISBN</a> 0-672-21035-5.</li> <li>Sheffer, H. M. (1913), "A set of five independent postulates for Boolean algebras, with application to logical constants", <i>Transactions of the American Mathematical Society</i>, 14 (4): 481–488, <a href="/facts/Doi_(identifier)/muM9Etpq">doi</a>:<a href="https://doi.org/10.2307%2F1988701">10.2307/1988701</a>, <a href="/facts/JSTOR_(identifier)/YTeVmaJ7">JSTOR</a> <a href="https://www.jstor.org/stable/1988701">1988701</a></li></ul> <h2 id="external-links">External links</h2> <ul><li><a href="http://www.allaboutcircuits.com/vol_4/chpt_3/5.html">TTL NAND and AND gates</a> – All About Circuits</li> <li><a href="http://www.fullchipdesign.com/drive_xor_nand_interview.htm">Steps to Derive XOR from NAND gate.</a></li> <li><a href="https://nandgame.com/">NandGame</a> – a game about building a computer using only NAND gates</li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>Nisan, Noam; Schocken, Shimon (2005). "1. Boolean Logic". From NAND to Tetris: Building a Modern Computer from First Principles (PDF). The MIT Press. Archived from the original (PDF) on 2017-01-10. <a href="/wiki/Noam_Nisan" target="_blank">/wiki/Noam_Nisan</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>Nisan, Noam; Schocken, Shimon (2005). "1. Boolean Logic". From NAND to Tetris: Building a Modern Computer from First Principles (PDF). The MIT Press. Archived from the original (PDF) on 2017-01-10. <a href="/wiki/Noam_Nisan" target="_blank">/wiki/Noam_Nisan</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> </ol>