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Advanced Programmable Interrupt Controller
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<p>In <a href="/facts/Computing/Kghtm9fX">computing</a>, <a href="/facts/Intel/SMF0gJJX">Intel</a>'s Advanced Programmable Interrupt Controller (APIC) is a family of <a href="/facts/Programmable_interrupt_controller/0ukSAuF1">programmable interrupt controllers</a>. As its name suggests, the APIC is more advanced than Intel's <a href="/facts/8259/Y5FhqM6G">8259</a> Programmable Interrupt Controller (PIC), particularly enabling the construction of <a href="/facts/Multiprocessor/aDCfehDQ">multiprocessor</a> systems. It is one of several architectural designs intended to solve interrupt routing efficiency issues in multiprocessor computer systems. </p><p>The APIC is a split architecture design, with a local component (LAPIC) usually integrated into the processor itself, and an optional I/O APIC on a system bus. The first APIC was the 82489DX – it was a discrete chip that functioned both as local and I/O APIC. The 82489DX enabled construction of <a href="/facts/Symmetric_multiprocessor/T9CahUsN">symmetric multiprocessor</a> (SMP) systems with the <a href="/facts/Intel_486/2zfEAXAw">Intel 486</a> and early <a href="/facts/Pentium/czINY469">Pentium</a> processors; for example, the reference two-way 486 SMP system used three 82489DX chips, two as local APICs and one as I/O APIC. Starting with the <a href="/facts/P54C/dqChAmxz">P54C</a> processor, the local APIC functionality was integrated into the Intel processors' silicon. The first dedicated I/O APIC was the Intel 82093AA, which was intended for <a href="/facts/PIIX3/oDUDgNe0">PIIX3</a>-based systems. </p>