Cache hierarchy

<p>Cache hierarchy, or multi-level cache, is a memory architecture that uses a hierarchy of memory stores based on varying access speeds to cache data. Highly requested data is cached in high-speed access memory stores, allowing swifter access by <a href="/facts/Central_processing_unit/Jxp1bqMV">central processing unit</a> (CPU) cores.
</p><p>Cache hierarchy is a form and part of <a href="/facts/Memory_hierarchy/ttwjvRyd">memory hierarchy</a> and can be considered a form of <a href="/facts/Tiered_storage/ttwjvRyd">tiered storage</a>. This design was intended to allow CPU cores to process faster despite the <a href="/facts/CAS_latency/4slUyjdX">memory latency</a> of <a href="/facts/Computer_data_storage/wPHKFpdx">main memory</a> access. Accessing main memory can act as a bottleneck for <a href="/facts/Computer_performance/td1qKox4">CPU core performance</a> as the CPU waits for data, while making all of main memory high-speed may be prohibitively expensive. High-speed caches are a compromise allowing high-speed access to the data most-used by the CPU, permitting a faster <a href="/facts/Clock_rate/w055Woaj">CPU clock</a>.
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Cache hierarchy open-in-new

Cache hierarchy