VIA PadLock

<p>VIA PadLock is a <a href="/facts/Central_processing_unit/Jxp1bqMV">central processing unit</a> (CPU) <a href="/facts/Instruction_set/8p8vwUeE">instruction set</a> extension to the <a href="/facts/X86/Kypq5fgu">x86</a> <a href="/facts/Microprocessor/Fx9CaQht">microprocessor</a> <a href="/facts/Instruction_set_architecture/8p8vwUeE">instruction set architecture</a> (ISA) found on processors produced by <a href="/facts/VIA_Technologies/g6REHNFE">VIA Technologies</a> and <a href="/facts/Zhaoxin/2wpVktlp">Zhaoxin</a>. Introduced in 2003 with the <a href="/facts/List_of_VIA_microprocessor_cores/zxkSpECS">VIA Centaur</a> CPUs, the additional instructions provide hardware-accelerated <a href="/facts/Random_number_generation/RtXEfbzd">random number generation</a> (RNG), <a href="/facts/Advanced_Encryption_Standard/HdXGBY2Q">Advanced Encryption Standard</a> (AES), <a href="/facts/SHA-1/LDYCV1je">SHA-1</a>, <a href="/facts/SHA256/P59oPeGq">SHA256</a>, and <a href="/facts/Montgomery_modular_multiplication/C1UyVrKJ">Montgomery modular multiplication</a>.
</p>

VIA PadLock open-in-new

VIA PadLock