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List of VIA microprocessor cores
List article

This article lists x86-compliant microprocessors sold by VIA Technologies, grouped by technical merits: cores within same group have much in common.

Cyrix design (Cyrix III)

MarketingnameCoreFrequencyFront-side busL1-cacheL2-cacheFPUspeedPipelinestagesTypical powerVoltageProcess
Cyrix IIIJoshua350-450 MHz100-133 MHz64 KB256 KB100%?13-16 W2.2 V180 nm Al

Centaur Technology design

Cyrix III, C3

MarketingnameCoreFrequencyFront-side busL1 cacheL2 cacheFPUspeedPipelinestagesTypical powerVoltageProcess
Cyrix III, C3, 1GigaProSamuel (C5A)466-733 MHz100-133 MHz128 KB0 KB50%126.8-10.6 W1.8-2.0 V180 nm Al
Cyrix III, C3, 1GigaPro, Eden ESP, XP 2000+Samuel 2 (C5B)600-800 MHz100-133 MHz128 KB64 KB50%125.8-6.6 W1.5-1.65 V150 nm Al
C3, Eden ESPEzra (C5C)733-933 MHz100-133 MHz128 KB64 KB50%125.3-5.9 W1.35 V130 nm Al
C3Ezra-T (C5N)800-1000 MHz100-133 MHz128 KB64 KB50%125.3-11.8 W1.35-1.45 V130 nm Al

C3, C7

MarketingnameCoreFrequencyFront-side busL1 cacheL2 cacheFPUspeedPipelinestagesTypical powerVoltageProcess
C3, Eden ESP, Eden-NNehemiah (C5XL)800-1400 MHz133 MHz128 KB64 KB100%1615-19 W1.25 or 1.4-1.45 V130 nm Cu
C3Nehemiah+ (C5P)1-1.4 GHz133 MHz128 KB64 KB100%1611-12 W1.25 V130 nm Cu
C7, C7-D, C7-M, Eden, Eden ULVEsther (C5J)0.4-2.0 GHz400-533 MT/s128 KB128 KB100%1612-20 W0.9-1.1(?) V90 nm SOI
SeriesModelCoreFrequency[MHz]Front-side bus[MHz]YearProcess[nm]Package size[mm2]Power[W]L2 cache[K]L1 I/D cache[K]Performance[SPEC2000]
EdenEden ESPSamuel 2300–60066/100/133200115035×352.5–66464/64Un­known
Eden ESPNehemiah667–1000133/2002003–200413035×356–76464/64Un­known
Eden-NNehemiah533–1000133200313015×152.5–76464/64Un­known
EdenEsther400–1500400–8002006–20079030<7.512832/32Un­known
Eden X2Un­known800Un­known20114011×6Un­knownUn­knownUn­knownUn­known
C3C3Samuel 2667–800100–1332001150Un­known136464/64Un­known
C3Ezra800–1000100–1332002130Un­known8.3–106464/64Un­known
C3Nehemiah1000–1400133–200200313035×3515–216464/64Un­known
C3-MNehemiah1000–1400133–200200313035×3511–196464/64Un­known
C7C7-DEsther1500–180040020069021×2120–2512816/16Un­known
C7-MEsther1000–200040020059021×2112–2012816/16Un­known
C7Esther1500–200080020079021×2112–2012816/16Un­known

Nano

  • First VIA processor with x86-64 instruction set
SeriesModelCoreFrequency[MHz]Front-side bus[MHz]YearProcess[nm]Package size[mm2]Power[W]L2 cache[K]L1 I/D cache[K]Performance[SPEC2000]
QuadCoreQuadCoreIsaiah1000-1460106620114021×2127.54× 102444× 64/6430.1/24.1 rate5

CHA

Main article: Centaur Technology § CNS core

  • Announced 2019.678 Discontinued in 2021 with the sales of Centaur to Intel.9
  • 8 cores + "NCORE" neural processor for AI acceleration.
  • supports: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AES AVX AVX2 FMA3 SHA AVX512 AVX512F AVX512CD AVX512BW AVX512DQ AVX512VL AVX512IFMA AVX512VBMI.
MarketingnameCode nameCoreNumber of coresFrequencyMicroarchitectureL1 cacheL2 cacheL3 cacheAnnouncedExpected ReleaseProcessSocket TypePipeline stagesPCIe Lanes
unknownCHACNS82.5 GHzCNS1032 KiB256 KiB16 MB20192H 20201116 nmLGA20-224412

See also

References

  1. "IA-32 implementation: VIA Cyrix III". sandpile.org. Archived from the original on 2007-07-09. Retrieved 2007-07-23. https://web.archive.org/web/20070709200826/http://www.sandpile.org/impl/m2c3.htm ↩

  2. "IA-32 implementation: VIA C3". sandpile.org. Archived from the original on 2007-07-17. Retrieved 2007-07-23. https://web.archive.org/web/20070717014946/http://www.sandpile.org/impl/c5.htm ↩

  3. "IA-32 implementation: VIA C7". sandpile.org. Archived from the original on 2007-06-30. Retrieved 2007-07-23. https://web.archive.org/web/20070630151130/http://www.sandpile.org/impl/c5xl.htm ↩

  4. "VIA QuadCore Processor". Via.com. Retrieved 2014-02-03. http://www.via.com.tw/en/products/processors/quadcore/index.jsp ↩

  5. "VIA Nano X2 Whitepaper" (PDF). Via.com. Archived from the original (PDF) on 27 May 2012. Retrieved 3 February 2014. https://web.archive.org/web/20120527051549/http://www.via.com.tw/en/downloads/whitepapers/processors/NanoX2_whitepaper_201107.pdf ↩

  6. "VIA CenTaur Develops a Multi-core x86 Processor for Enterprise with in-built AI Hardware". TechPowerUp. November 18, 2019h. Retrieved 2020-07-28. https://www.techpowerup.com/261274/via-centaur-develops-a-multi-core-x86-processor-for-enterprise-with-in-built-ai-hardware ↩

  7. "VIA CenTaur CHA NCORE AI CPU Pictured, a Socketed LGA Package". TechPowerUp. February 18, 2020. Retrieved 2020-07-28. https://www.techpowerup.com/263978/via-centaur-cha-ncore-ai-cpu-pictured-a-socketed-lga-package ↩

  8. "CHA - Microarchitectures - Centaur Technology - WikiChip". en.wikichip.org. Retrieved 2020-07-28. https://en.wikichip.org/wiki/centaur/microarchitectures/cha ↩

  9. "The Last x86 Via Chip: Unreleased Next-Gen Centaur CNS Saved From Trash Bin, Tested". TomsHardware. 22 February 2022. https://www.tomshardware.com/news/last-x86-via-chip-centuar-cns-cpu-tested ↩

  10. "VIA x86 AI processor architecture, performance announcement: comparable to Intel 32 core". Small Tech News. December 11, 2019. https://www.smalltechnews.com/archives/36581 ↩

  11. "Centaur Releases In-Depth Analysis from The Linley Group for its NCORE-Equipped x86 Processor". TechPowerUp. December 9, 2019. Retrieved 2020-08-30. https://www.techpowerup.com/261979/centaur-releases-in-depth-analysis-from-the-linley-group-for-its-ncore-equipped-x86-processor ↩

  12. "World's First High-Performancex86 SoCwithIntegrated AI Coprocessor" (PDF). centtech. p. 4. Archived from the original on November 19, 2019. https://web.archive.org/web/20191119163412/https://centtech.com/wp-content/uploads/PRSlides_1118_Release.pdf ↩