Second Level Address Translation

Second Level Address Translation (SLAT), also known as nested paging, is a <a href="/facts/Hardware-assisted_virtualization/n4kjJLqA">hardware-assisted virtualization</a> technology which makes it possible to avoid the overhead associated with software-managed <a href="/facts/Shadow_page_tables/utQwmdY3">shadow page tables</a>.
<a href="/facts/AMD/CB1G7QTb">AMD</a> has supported SLAT through the Rapid Virtualization Indexing (RVI) technology since the introduction of its third-generation <a href="/facts/Opteron/IF1ueyIJ">Opteron</a> processors (code name Barcelona). <a href="/facts/Intel/SMF0gJJX">Intel</a>'s implementation of SLAT, known as Extended Page Table (EPT), was introduced in the <a href="/facts/Nehalem_(microarchitecture)/UPsI457h">Nehalem microarchitecture</a> found in certain <a href="/facts/Core_i7/5qT6deUr">Core i7</a>, <a href="/facts/Core_i5/YYnBYKoR">Core i5</a>, and <a href="/facts/Core_i3/WzEJtfJd">Core i3</a> processors. 
<a href="/facts/ARM_architecture/SALsYA79">ARM</a>'s virtualization extensions support SLAT, known as Stage-2 page-tables provided by a Stage-2 <a href="/facts/Memory_management_unit/tJQtAQzI">MMU</a>. The guest uses the Stage-1 MMU. Support was added as optional in the ARMv7ve architecture and is also supported in the ARMv8 (32-bit and 64-bit) architectures.

Second Level Address Translation open-in-new

Second Level Address Translation