Unicore is a computer instruction set architecture designed by the Microprocessor Research and Development Center (MPRC) of Peking University in the PRC. The computer built on this architecture is called the Unity-863. The CPU is integrated into a fully functional SoC to make a PC-like system.
The processor is very similar to the ARM architecture, but uses a different instruction set.[better source needed]
It is supported by the Linux kernel as of version 2.6.39. Support will be removed in Linux kernel version 5.9 as nobody seems to maintain it and the code is falling behind the rest of the kernel code and compiler requirements.
Instruction set
The instructions are almost identical to the standard ARM formats, except that conditional execution has been removed, and the bits reassigned to expand all the register specifiers to 5 bits.67 Likewise, the immediate format is 9 bits rotated by a 5-bit amount (rather than 8 bit rotated by 4), the load/store offset sizes are 14 bits for byte/word and 10 bits for signed byte or half-word. Conditional moves are provided by encoding the condition in the (unused by ARM) second source register field Rn for MOV and MVN instructions.
Unicore32 instruction set overview8| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Description |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | opcode | S | Rn | Rd | shift | 0 | Sh | 0 | Rm | ALU operation, Rd = Rn op Rm shift #shift | ||||||||||||||||||||
| 0 | 0 | 0 | opcode | S | Rn | Rd | Rs | 0 | Sh | 1 | Rm | ALU operation, Rd = Rn op Rm shift Rs | ||||||||||||||||||||
| 0 | 0 | 1 | opcode | S | Rn | Rd | shift | imm9 | ALU operation, Rd = Rn op #imm9 ROTL #shift | |||||||||||||||||||||||
| 0 | 1 | 0 | P | U | B | W | L | Rn | Rd | shift | 0 | Sh | 0 | Rm | Load/store Rd to address Rn ± Rm shift #shift | |||||||||||||||||
| 0 | 1 | 1 | P | U | B | W | L | Rn | Rd | offset14 | Load/store Rd to address Rn ± offset14 | |||||||||||||||||||||
| 1 | 0 | 0 | P | U | S | W | L | Rn | Bitmap high | 0 | 0 | H | Bitmap low | Load/store multiple registers | ||||||||||||||||||
| 1 | 0 | 1 | cond | L | offset24 | Branch (and link) if condition true | ||||||||||||||||||||||||||
| 1 | 1 | 0 | Coprocessor (FPU) instructions | |||||||||||||||||||||||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | Trap number | Software interrupt | |||||||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | A | S | Rn | Rd | Rs | 1 | 0 | 0 | 1 | Rm | Multiply, Rd = Rm * Rs (+ Rn) | ||||||||||||||||
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | L | 11111 | 11111 | 00000 | 1 | 0 | 0 | 1 | Rm | Branch and exchange (BX, BLX) | ||||||||||||||||
| 0 | 1 | 0 | P | U | 0 | W | L | Rn | Rd | 00000 | 1 | S | H | 1 | Rm | Load/store Rd to address Rn ± Rm (16-bit) | ||||||||||||||||
| 0 | 1 | 0 | P | U | 1 | W | L | Rn | Rd | imm_hi | 1 | S | H | 1 | imm_lo | Load/store Rd to address Rn ± #imm10 (16-bit) | ||||||||||||||||
The meaning of various flag bits (such as S=1 enables setting the condition codes) is identical to the ARM instruction set. The load/store multiple instruction can only access half of the register set, depending on the H bit. If H=0, the 16 bits indicate R0–R15; if H=1, R16–R31.
References
"Introduction to MPRC". Microprocessor Research and Develop Center, Peking University. http://mprc.pku.cn/eng/intro.html ↩
Xu Cheng; Xiaoyin Wang; Junlin Lu; Jiangfang Yi; Dong Tong; Xuetao Guan; Feng Liu; Xianhua Liu; Chun Yang; Yi Feng (March 2010), "Research Progress of UniCore CPUs and PKUnity SoCs" (PDF), Journal of Computer Science and Technology, 25 (2): 200–213, doi:10.1007/s11390-010-9317-1, S2CID 7083916, retrieved 2012-07-11 http://mprc.pku.edu.cn/~guanxuetao/publications/2010-JCST-CX.pdf ↩
Bergmann, Arnd (2012-07-09). "Re: [PATCH 00/36] AArch64 Linux kernel port". linux-kernel (Mailing list). Retrieved 2012-07-11. Another interesting example is unicore32, which actually shares more code with arch/arm than the proposed arch/aarch64 does. I think the unicore32 code base would benefit from being merged back into arch/arm as a third instruction set, but the additional maintenance cost for everyone working on ARM makes that unrealistic. https://marc.info/?l=linux-kernel&m=134184818409286 ↩
"Merge window closed - 2.6.39-rc1 out". Linus Torvalds. https://lkml.org/lkml/2011/3/29/351 ↩
"remove unicore32 support". Mike Rapoport. https://lkml.org/lkml/2020/8/3/232 ↩
Hsu-Hung Chiang; Huang-Jia Cheng; Yuan-Shin Hwan (2012-02-25), "Doubling the Number of Registers on ARM Processors" (PDF), 16th Workshop on Interaction between Compilers and Computer Architectures (INTERACT), pp. 1–8, doi:10.1109/INTERACT.2012.6339620, ISBN 978-1-4673-2613-1, S2CID 6832041 978-1-4673-2613-1 ↩
Unicore processor simulator source code. Instruction formats are in decode.c, disassembly in interpret.c, and emulation in instEx.c. https://code.google.com/p/minic/source/browse/trunk/simulator/ ↩
QEMU Unicore32 emulator source code https://github.com/qemu/qemu/blob/HEAD/target/unicore32/translate.c ↩