Menu
Home
People
Places
Arts
History
Plants & Animals
Science
Life & Culture
Technology
Reference.org
Socket FS1
open-in-new
<h2 id="feature-overview-for-amd-apus">Feature overview for AMD APUs</h2> <p>The following table shows features of <a href="/facts/AMD/CB1G7QTb">AMD</a>'s processors with 3D graphics, including <a href="/facts/AMD_APU/hdApEUQw">APUs</a> (see also: <a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">List of AMD processors with 3D graphics</a>). </p> [ <a href="https://en.wikipedia.org/w/index.php?title=Template:Features_of_AMD_Processors_with_3D_Graphics&veaction=edit">VisualEditor</a> ] <ul><li>view</li><li>talk</li><li>edit</li></ul> <table><tbody><tr><th colspan="3">Platform</th><th colspan="14">High, standard and low power</th><th colspan="9">Low and ultra-low power</th></tr><tr><th rowspan="11">Codename</th><th rowspan="2">Server</th><th>Basic</th><th colspan="5"></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Toronto</a></th><th colspan="8"></th><th colspan="9"></th></tr><tr><th>Micro</th><th colspan="14"></th><th></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Kyoto</a></th><th colspan="7"></th></tr><tr><th rowspan="4">Desktop</th><th>Performance</th><th colspan="12"></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Raphael</a></th><th rowspan="3"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Phoenix</a></th><th colspan="9" rowspan="3"></th></tr><tr><th>Mainstream</th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Llano</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Trinity</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Richland</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Kaveri</a></th><th rowspan="2"><a href="/facts/Steamroller_(microarchitecture)/SxtLaauz">Kaveri Refresh (Godavari)</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Carrizo</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Bristol Ridge</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Raven Ridge</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Picasso</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Renoir</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Cezanne</a></th><th></th></tr><tr><th>Entry</th><th colspan="2"></th></tr><tr><th>Basic</th><th colspan="14"></th><th></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Kabini</a></th><th colspan="3"></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Dalí</a></th><th colspan="3"></th></tr><tr><th rowspan="4">Mobile</th><th>Performance</th><th colspan="9"></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Renoir</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Cezanne</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Rembrandt</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Dragon Range</a></th><th></th><th rowspan="2" colspan="9"></th></tr><tr><th>Mainstream</th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Llano</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Trinity</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Richland</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Kaveri</a></th><th rowspan="2"></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Carrizo</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Bristol Ridge</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Raven Ridge</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Picasso</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Renoir</a><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Lucienne</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Cezanne</a><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Barceló</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Phoenix</a></th></tr><tr><th>Entry</th><th colspan="6"></th><th colspan="5"></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Dalí</a></th><th colspan="2"></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Mendocino</a></th></tr><tr><th>Basic</th><th colspan="14"></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Desna, Ontario, Zacate</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Kabini, Temash</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Beema, Mullins</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Carrizo-L</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Stoney Ridge</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Pollock</a></th><th></th></tr><tr><th colspan="2">Embedded</th><th></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Trinity</a></th><th></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Bald Eagle</a></th><th></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Merlin Falcon</a>,<a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Brown Falcon</a></th><th></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Great Horned Owl</a></th><th></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Grey Hawk</a></th><th colspan="4"></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Ontario, Zacate</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Kabini</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Steppe Eagle</a>, <a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Crowned Eagle</a>, <a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">LX-Family</a></th><th></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Prairie Falcon</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Banded Kestrel</a></th><th></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">River Hawk</a></th><th></th></tr><tr><td colspan="3">Released</td><td>Aug 2011</td><td>Oct 2012</td><td>Jun 2013</td><td>Jan 2014</td><td>2015</td><td>Jun 2015</td><td>Jun 2016</td><td>Oct 2017</td><td>Jan 2019</td><td>Mar 2020</td><td>Jan 2021</td><td>Jan 2022</td><td>Sep 2022</td><td>Jan 2023</td><td>Jan 2011</td><td>May 2013</td><td>Apr 2014</td><td>May 2015</td><td>Feb 2016</td><td>Apr 2019</td><td>Jul 2020</td><td>Jun 2022</td><td>Nov 2022</td></tr><tr><td colspan="3">CPU <a href="/facts/Microarchitecture/NFRd4NUL">microarchitecture</a></td><td><a href="/facts/AMD_10h/2hQAazep">K10</a></td><td colspan="2"><a href="/facts/Piledriver_(microarchitecture)/Fhxly06H">Piledriver</a></td><td colspan="2"><a href="/facts/Steamroller_(microarchitecture)/SxtLaauz">Steamroller</a></td><td><a href="/facts/Excavator_(microarchitecture)/Bzj9WKGV">Excavator</a></td><td>"<a href="/facts/Excavator_(microarchitecture)/Bzj9WKGV">Excavator+</a>"<a class="footnote-ref" id="fnref:1" href="#fn:1"><sup>1</sup></a></td><td><a href="/facts/Zen_(first_generation)/oChXIp3y">Zen</a></td><td><a href="/facts/Zen%2B/1bJfQtRR">Zen+</a></td><td><a href="/facts/Zen_2/pdL7I80c">Zen 2</a></td><td><a href="/facts/Zen_3/szGTAfyB">Zen 3</a></td><td><a href="/facts/Zen_3%2B/szGTAfyB">Zen 3+</a></td><td colspan="2"><a href="/facts/Zen_4/UJXLYNuq">Zen 4</a></td><td><a href="/facts/Bobcat_(microarchitecture)/EweFKE9J">Bobcat</a></td><td><a href="/facts/Jaguar_(microarchitecture)/PkCbNj9a">Jaguar</a></td><td><a href="/facts/Puma_(microarchitecture)/ujJ1MBg1">Puma</a></td><td><a href="/facts/Puma_(microarchitecture)/ujJ1MBg1">Puma+</a><a class="footnote-ref" id="fnref:2" href="#fn:2"><sup>2</sup></a></td><td>"<a href="/facts/Excavator_(microarchitecture)/Bzj9WKGV">Excavator+</a>"</td><td colspan="2"><a href="/facts/Zen_(first_generation)/oChXIp3y">Zen</a></td><td><a href="/facts/Zen%2B/1bJfQtRR">Zen+</a></td><td>"<a href="/facts/Zen_2/pdL7I80c">Zen 2+</a>"</td></tr><tr><td colspan="3"><a href="/facts/Instruction_set_architecture/8p8vwUeE">ISA</a></td><td><a href="/facts/X86-64/cyWvUFlP">x86-64</a> v1</td><td colspan="4"><a href="/facts/X86-64/cyWvUFlP">x86-64</a> v2</td><td colspan="7"><a href="/facts/X86-64/cyWvUFlP">x86-64</a> v3</td><td colspan="2"><a href="/facts/X86-64/cyWvUFlP">x86-64</a> v4</td><td><a href="/facts/X86-64/cyWvUFlP">x86-64</a> v1</td><td colspan="3"><a href="/facts/X86-64/cyWvUFlP">x86-64</a> v2</td><td colspan="5"><a href="/facts/X86-64/cyWvUFlP">x86-64</a> v3</td></tr><tr><td rowspan="5">Socket</td><td rowspan="4">Desktop</td><td>Performance</td><td colspan="12">—</td><td rowspan="2"><a href="/facts/Socket_AM5/x4zuI5Ck">AM5</a></td><td>—</td><td rowspan="3" colspan="9">—</td></tr><tr><td>Mainstream</td><td colspan="5">—</td><td colspan="6"><a href="/facts/Socket_AM4/MuNKCgeF">AM4</a></td><td>—</td><th>—</th></tr><tr><td>Entry</td><td><a href="/facts/Socket_FM1/vrA6VVSD">FM1</a></td><td colspan="2"><a href="/facts/Socket_FM2/olCXfpAL">FM2</a></td><td colspan="2"><a href="/facts/Socket_FM2%2B/GQlcTMJW">FM2+</a></td><td><a href="/facts/Socket_FM2%2B/GQlcTMJW">FM2+</a><a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a>, <a href="/facts/Socket_AM4/MuNKCgeF">AM4</a></td><td colspan="5"><a href="/facts/Socket_AM4/MuNKCgeF">AM4</a></td><td colspan="3">—</td></tr><tr><td>Basic</td><td colspan="14">—</td><td>—</td><td><a href="/facts/Socket_AM1/43Q9guVD">AM1</a></td><td colspan="3">—</td><td>FP5</td><td colspan="3">—</td></tr><tr><td colspan="2">Other</td><td>FS1</td><td colspan="2"><a href="/facts/Socket_FS1r2/GGxHBYCC">FS1+</a>, <a href="/facts/Socket_FP2/c8WeE1u8">FP2</a></td><td colspan="2"><a href="/facts/Socket_FP3/7vDcpQfR">FP3</a></td><td colspan="2">FP4</td><td colspan="2">FP5</td><td colspan="2">FP6</td><td>FP7</td><td>FL1</td><td>FP7 FP7r2 FP8</td><td><a href="/facts/Socket_FT1/IuvuQVPW">FT1</a></td><td><a href="/facts/Socket_FT3/PC1tK41m">FT3</a></td><td colspan="2"><a href="/facts/Socket_FT3b/PC1tK41m">FT3b</a></td><td>FP4</td><td>FP5</td><td>FT5</td><td>FP5</td><td>FT6</td></tr><tr><td colspan="3"><a href="/facts/PCI_Express/ADhsLCUK">PCI Express</a> version</td><td colspan="3">2.0</td><td colspan="8">3.0</td><td>4.0</td><td>5.0</td><td>4.0</td><td colspan="4">2.0</td><td colspan="5">3.0</td></tr><tr><td colspan="3"><a href="/facts/Compute_Express_Link/YSJGcCMx">CXL</a></td><td colspan="14">—</td><td colspan="9">—</td></tr><tr><td colspan="3"><a href="/facts/Semiconductor_device_fabrication/Jd23Mu1z">Fab.</a> (<a href="/facts/Nanometre/a98sjHyu">nm</a>)</td><td colspan="3"><a href="/facts/GlobalFoundries/lFTS5fbT">GF</a> <a href="/facts/32_nm_process/CsdohJVh">32SHP</a>(<a href="/facts/HKMG/4E8qtXmp">HKMG</a> <a href="/facts/Silicon_on_insulator/fxSkXYmw">SOI</a>)</td><td colspan="4">GF <a href="/facts/32_nm_process/CsdohJVh">28SHP</a>(HKMG bulk)</td><td>GF <a href="/facts/14_nm_process/lQYsD92n">14LPP</a>(<a href="/facts/FinFET/xox63kP7">FinFET</a> bulk)</td><td>GF <a href="/facts/14_nm_process/lQYsD92n">12LP</a>(FinFET bulk)</td><td colspan="2"><a href="/facts/TSMC/B4BdojRk">TSMC</a> <a href="/facts/7_nm_process/7UatqvR9">N7</a>(FinFET bulk)</td><td>TSMC <a href="/facts/7_nm_process/7UatqvR9">N6</a> (FinFET bulk)</td><td>CCD: TSMC <a href="/facts/5_nm_process/5NndITJ3">N5</a> (FinFET bulk)cIOD: TSMC <a href="/facts/7_nm_process/7UatqvR9">N6</a>(FinFET bulk)</td><td>TSMC <a href="/facts/5_nm_process/5NndITJ3">4nm</a> (FinFET bulk)</td><td>TSMC <a href="/facts/45_nm_process/hlbmxAme">N40</a>(bulk)</td><td>TSMC <a href="/facts/32_nm_process/CsdohJVh">N28</a>(HKMG bulk)</td><td colspan="3">GF 28SHP(HKMG bulk)</td><td colspan="2">GF <a href="/facts/14_nm_process/lQYsD92n">14LPP</a>(<a href="/facts/FinFET/xox63kP7">FinFET</a> bulk)</td><td>GF <a href="/facts/14_nm_process/lQYsD92n">12LP</a>(FinFET bulk)</td><td>TSMC <a href="/facts/7_nm_process/7UatqvR9">N6</a> (FinFET bulk)</td></tr><tr><td colspan="3"><a href="/facts/Die_(integrated_circuit)/XWvdlltE">Die</a> area (mm2)</td><td>228</td><td colspan="2">246</td><td colspan="2">245</td><td>245</td><td>250</td><td colspan="2">210<a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a></td><td>156</td><td>180</td><td>210</td><td>CCD: (2x) 70cIOD: 122</td><td>178</td><td>75 (+ 28 <a href="/facts/List_of_AMD_chipsets/AesBnfxQ">FCH</a>)</td><td colspan="2">107</td><td>?</td><td>125</td><td>149</td><td></td><td></td><td>~100</td></tr><tr><td colspan="3">Min <a href="/facts/Thermal_Design_Power/Idcy26tM">TDP</a> (W)</td><td>35</td><td colspan="4">17</td><td colspan="4">12</td><td colspan="2">10</td><td>15</td><td>65</td><td>35</td><td>4.5</td><td>4</td><td>3.95</td><td>10</td><td colspan="3">6</td><td>12</td><td>8</td></tr><tr><td colspan="3">Max APU <a href="/facts/Thermal_Design_Power/Idcy26tM">TDP</a> (W)</td><td colspan="3">100</td><td colspan="2">95</td><td colspan="6">65</td><td>45</td><td>170</td><td>54</td><td>18</td><td colspan="5">25</td><td>6</td><td>54</td><td>15</td></tr><tr><td colspan="3">Max stock APU base clock (GHz)</td><td>3</td><td>3.8</td><td>4.1</td><td colspan="2">4.1</td><td>3.7</td><td>3.8</td><td>3.6</td><td>3.7</td><td>3.8</td><td>4.0</td><td>3.3</td><td>4.7</td><td>4.3</td><td>1.75</td><td>2.2</td><td>2</td><td>2.2</td><td>3.2</td><td>2.6</td><td>1.2</td><td>3.35</td><td>2.8</td></tr><tr><td colspan="3">Max APUs per node<a class="footnote-ref" id="fnref:5" href="#fn:5"><sup>5</sup></a></td><td colspan="14">1</td><td colspan="9">1</td></tr><tr><td colspan="3">Max core dies per CPU</td><td colspan="12">1</td><td>2</td><td>1</td><td colspan="9">1</td></tr><tr><td colspan="3">Max CCX per core die</td><td colspan="9">1</td><td>2</td><td colspan="4">1</td><td colspan="9">1</td></tr><tr><td colspan="3">Max cores per CCX</td><td colspan="10">4</td><td colspan="4">8</td><td>2</td><td colspan="3">4</td><td colspan="3">2</td><td colspan="2">4</td></tr><tr><td colspan="3">Max <a href="/facts/Central_processing_unit/Jxp1bqMV">CPU</a><a class="footnote-ref" id="fnref:6" href="#fn:6"><sup>6</sup></a> <a href="/facts/Multi-core_processor/ABNb65hQ">cores</a> per APU</td><td colspan="9">4</td><td colspan="3">8</td><td>16</td><td>8</td><td>2</td><td colspan="3">4</td><td colspan="3">2</td><td colspan="2">4</td></tr><tr><td colspan="3">Max <a href="/facts/Thread_(computing)/hh8WHyPd">threads</a> per CPU core</td><td colspan="7">1</td><td colspan="7">2</td><td colspan="5">1</td><td colspan="4">2</td></tr><tr><td colspan="3">Integer pipeline structure</td><td>3+3</td><td colspan="6">2+2</td><td colspan="2">4+2</td><td>4+2+1</td><td colspan="4">1+3+3+1+2</td><td colspan="4">1+1+1+1</td><td>2+2</td><td colspan="3">4+2</td><td>4+2+1</td></tr><tr><td colspan="3">i386, i486, i586, CMOV, NOPL, i686, <a href="/facts/Physical_Address_Extension/aEr4tj4x">PAE</a>, <a href="/facts/NX_bit/MnBB93BK">NX bit</a>, CMPXCHG16B, <a href="/facts/AMD-V/utQwmdY3">AMD-V</a>, <a href="/facts/Second_Level_Address_Translation/WY0j2dRv">RVI</a>, <a href="/facts/Bit_Manipulation_Instruction_Sets/LJAm1LWC">ABM</a>, and 64-bit LAHF/SAHF</td><td colspan="14"></td><td colspan="9"></td></tr><tr><td colspan="3"><a href="/facts/IOMMU/lvVkzUyw">IOMMU</a><a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a></td><td rowspan="2">—</td><td colspan="13">v2</td><td colspan="2">v1</td><td colspan="7">v2</td></tr><tr><td colspan="3"><a href="/facts/Bit_Manipulation_Instruction_Sets/LJAm1LWC">BMI1</a>, <a href="/facts/AES_instruction_set/NomFEB4w">AES-NI</a>, <a href="/facts/CLMUL/UzzxBF65">CLMUL</a>, and <a href="/facts/F16C/v6G70oa7">F16C</a></td><td colspan="13"></td><td rowspan="2">—</td><td colspan="9" rowspan="2"></td></tr><tr><td colspan="3">MOVBE</td><td colspan="5" rowspan="2">—</td><td rowspan="2" colspan="9"></td></tr><tr><td colspan="3"><a href="/facts/X86_virtualization/utQwmdY3">AVIC</a>, <a href="/facts/Bit_Manipulation_Instruction_Sets/LJAm1LWC">BMI2</a>, <a href="/facts/RDRAND/IdeN4y36">RDRAND</a>, and MWAITX/MONITORX</td><td colspan="4">—</td><td colspan="5"></td></tr><tr><td colspan="3">SME<a class="footnote-ref" id="fnref:8" href="#fn:8"><sup>8</sup></a>, TSME<a class="footnote-ref" id="fnref:9" href="#fn:9"><sup>9</sup></a>, <a href="/facts/Intel_ADX/7I3KDzYA">ADX</a>, <a href="/facts/Intel_SHA_extensions/qDzy2N70">SHA</a>, <a href="/facts/RDSEED/IdeN4y36">RDSEED</a>, <a href="/facts/Supervisor_Mode_Access_Prevention/H8RSCNy2">SMAP</a>, <a href="/facts/Control_register/9VGRHh3f">SMEP</a>, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing</td><td colspan="7">—</td><td colspan="7"></td><td colspan="5">—</td><td colspan="4"></td></tr><tr><td colspan="3"><a href="/facts/Second_Level_Address_Translation/WY0j2dRv">GMET</a>, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT</td><td colspan="9">—</td><td colspan="5"></td><td colspan="8">—</td><td></td></tr><tr><td colspan="3"><a href="/facts/Memory_protection/3zDwN2SG">MPK</a>, VAES</td><td colspan="10">—</td><td colspan="4"></td><td colspan="9">—</td></tr><tr><td colspan="3"><a href="/facts/Software_Guard_Extensions/HcgbyB5P">SGX</a></td><td colspan="14">—</td><td colspan="9">—</td></tr><tr><td colspan="3"><a href="/facts/Floating-point_unit/XWTW2AbF">FPUs</a> per <a href="/facts/Multi-core_processor/ABNb65hQ">core</a></td><td>1</td><td colspan="6">0.5</td><td colspan="7">1</td><td colspan="4">1</td><td>0.5</td><td colspan="4">1</td></tr><tr><td colspan="3">Pipes per FPU</td><td colspan="14">2</td><td colspan="9">2</td></tr><tr><td colspan="3">FPU pipe width</td><td colspan="9">128-bit</td><td colspan="5">256-bit</td><td>80-bit</td><td colspan="7">128-bit</td><td>256-bit</td></tr><tr><td colspan="3">CPU <a href="/facts/Instruction_set/8p8vwUeE">instruction set</a> <a href="/facts/Single_instruction,_multiple_data/gQHWQSpo">SIMD</a> level</td><td><a href="/facts/SSE4a/Tnxrl7Ph">SSE4a</a><a class="footnote-ref" id="fnref:10" href="#fn:10"><sup>10</sup></a></td><td colspan="4"><a href="/facts/Advanced_Vector_Extensions/znDpc6Vt">AVX</a></td><td colspan="7"><a href="/facts/Advanced_Vector_Extensions/znDpc6Vt">AVX2</a></td><td colspan="2"><a href="/facts/AVX-512/2KpGqI8t">AVX-512</a></td><td><a href="/facts/SSSE3/xlRTcz4I">SSSE3</a></td><td colspan="3"><a href="/facts/Advanced_Vector_Extensions/znDpc6Vt">AVX</a></td><td colspan="5"><a href="/facts/Advanced_Vector_Extensions/znDpc6Vt">AVX2</a></td></tr><tr><td colspan="3"><a href="/facts/3DNow!/QYJL2HBt">3DNow!</a></td><td><a href="/facts/3DNow!/QYJL2HBt">3DNow!+</a></td><td colspan="13">—</td><td colspan="9">—</td></tr><tr><td colspan="3"><a href="/facts/PREFETCHW/QYJL2HBt">PREFETCH/PREFETCHW</a></td><td colspan="14"></td><td colspan="9"></td></tr><tr><td colspan="3">GFNI</td><td colspan="12">—</td><td colspan="2"></td><td rowspan="2" colspan="9">—</td></tr><tr><td colspan="3"><a href="/facts/Advanced_Matrix_Extensions/qkDBQbBE">AMX</a></td><td colspan="14">—</td></tr><tr><td colspan="3"><a href="/facts/FMA4/mqglSHqk">FMA4</a>, LWP, <a href="/facts/Bit_Manipulation_Instruction_Sets/LJAm1LWC">TBM</a>, and <a href="/facts/XOP_instruction_set/Xey2cAGM">XOP</a></td><td rowspan="2">—</td><td colspan="6"></td><td colspan="7">—</td><td rowspan="2" colspan="4">—</td><td></td><td colspan="4">—</td></tr><tr><td colspan="3"><a href="/facts/FMA3/mqglSHqk">FMA3</a></td><td colspan="13"></td><td colspan="5"></td></tr><tr><td colspan="3"><a href="/facts/AMD_XDNA/Yafyvy2F">AMD XDNA</a></td><td colspan="13">—</td><td></td><td colspan="9">—</td></tr><tr><td colspan="3"><a href="/facts/L1_cache/x8BYFcdv">L1</a> data cache per core (KiB)</td><td>64</td><td colspan="4">16</td><td colspan="9">32</td><td colspan="9">32</td></tr><tr><td colspan="3">L1 data cache <a href="/facts/Cache_placement_policies/MuBjrreM">associativity</a> (ways)</td><td>2</td><td colspan="4">4</td><td colspan="9">8</td><td colspan="9">8</td></tr><tr><td colspan="3">L1 instruction caches per <a href="/facts/Multi-core_processor/ABNb65hQ">core</a></td><td>1</td><td colspan="6">0.5</td><td colspan="7">1</td><td colspan="4">1</td><td>0.5</td><td colspan="4">1</td></tr><tr><td colspan="3">Max APU total L1 instruction cache (KiB)</td><td>256</td><td colspan="2">128</td><td colspan="4">192</td><td colspan="5">256</td><td>512</td><td>256</td><td colspan="2">64</td><td colspan="2">128</td><td>96</td><td colspan="4">128</td></tr><tr><td colspan="3">L1 instruction cache <a href="/facts/Cache_placement_policies/MuBjrreM">associativity</a> (ways)</td><td colspan="3">2</td><td colspan="4">3</td><td colspan="2">4</td><td colspan="5">8</td><td colspan="4">2</td><td>3</td><td colspan="3">4</td><td>8</td></tr><tr><td colspan="3"><a href="/facts/L2_cache/x8BYFcdv">L2 caches</a> per <a href="/facts/Multi-core_processor/ABNb65hQ">core</a></td><td>1</td><td colspan="6">0.5</td><td colspan="7">1</td><td colspan="4">1</td><td>0.5</td><td colspan="4">1</td></tr><tr><td colspan="3">Max APU total L2 cache (MiB)</td><td colspan="5">4</td><td colspan="4">2</td><td colspan="3">4</td><td>16</td><td></td><td>1</td><td colspan="3">2</td><td colspan="3">1</td><td colspan="2">2</td></tr><tr><td colspan="3">L2 cache <a href="/facts/Cache_placement_policies/MuBjrreM">associativity</a> (ways)</td><td colspan="7">16</td><td colspan="7">8</td><td colspan="5">16</td><td colspan="4">8</td></tr><tr><td colspan="3">Max on-die <a href="/facts/L3_cache/x8BYFcdv">L3 cache</a> per CCX (MiB)</td><td colspan="7" rowspan="8">—</td><td colspan="3">4</td><td colspan="2">16</td><td>32</td><td></td><td colspan="6" rowspan="8">—</td><td colspan="4">4</td></tr><tr><td colspan="3">Max 3D V-Cache per CCD (MiB)</td><td colspan="5">—</td><td>64</td><td>—</td><td colspan="4">—</td></tr><tr><td colspan="3">Max total in-CCD <a href="/facts/L3_cache/x8BYFcdv">L3 cache</a> per APU (MiB)</td><td colspan="2">4</td><td>8</td><td colspan="2">16</td><td>64</td><td></td><td colspan="4">4</td></tr><tr><td colspan="3">Max. total 3D V-Cache per APU (MiB)</td><td colspan="5">—</td><td>64</td><td>—</td><td colspan="4">—</td></tr><tr><td colspan="3">Max. board <a href="/facts/L3_cache/x8BYFcdv">L3 cache</a> per APU (MiB)</td><td colspan="7">—</td><td colspan="4">—</td></tr><tr><td colspan="3">Max total <a href="/facts/L3_cache/x8BYFcdv">L3 cache</a> per APU (MiB)</td><td colspan="2">4</td><td>8</td><td colspan="2">16</td><td>128</td><td></td><td colspan="4">4</td></tr><tr><td colspan="3">APU L3 cache <a href="/facts/Cache_placement_policies/MuBjrreM">associativity</a> (ways)</td><td colspan="7">16</td><td colspan="4">16</td></tr><tr><td colspan="3">L3 cache scheme</td><td colspan="7"><a href="/facts/Victim_cache/7efuQ3PY">Victim</a></td><td colspan="4"><a href="/facts/Victim_cache/7efuQ3PY">Victim</a></td></tr><tr><td colspan="3">Max. <a href="/facts/L4_cache/x8BYFcdv">L4 cache</a></td><td colspan="14">—</td><td colspan="9">—</td></tr><tr><td colspan="3">Max stock <a href="/facts/Dynamic_random-access_memory/koI9FGo5">DRAM</a> support</td><td colspan="2"><a href="/facts/DDR3_SDRAM/1R1CTNv3">DDR3</a>-1866</td><td colspan="3">DDR3-2133</td><td>DDR3-2133, <a href="/facts/DDR4_SDRAM/70r37baX">DDR4</a>-2400</td><td>DDR4-2400</td><td colspan="2">DDR4-2933</td><td colspan="2">DDR4-3200, <a href="/facts/LPDDR/2XdLrg47">LPDDR4</a>-4266</td><td><a href="/facts/DDR5_SDRAM/N3XSGE40">DDR5</a>-4800, <a href="/facts/LPDDR/2XdLrg47">LPDDR5</a>-6400</td><td><a href="/facts/DDR5_SDRAM/N3XSGE40">DDR5</a>-5200</td><td><a href="/facts/DDR5_SDRAM/N3XSGE40">DDR5</a>-5600, <a href="/facts/LPDDR/2XdLrg47">LPDDR5x</a>-7500</td><td><a href="/facts/DDR3L/1R1CTNv3">DDR3L</a>-1333</td><td>DDR3L-1600</td><td colspan="2">DDR3L-1866</td><td>DDR3-1866, <a href="/facts/DDR4_SDRAM/70r37baX">DDR4</a>-2400</td><td>DDR4-2400</td><td>DDR4-1600</td><td>DDR4-3200</td><td>LPDDR5-5500</td></tr><tr><td colspan="3">Max <a href="/facts/Dynamic_random-access_memory/koI9FGo5">DRAM</a> channels per APU</td><td colspan="14">2</td><td colspan="5">1</td><td>2</td><td>1</td><td colspan="2">2</td></tr><tr><td colspan="3">Max stock <a href="/facts/Dynamic_random-access_memory/koI9FGo5">DRAM</a> <a href="/facts/Bandwidth_(computing)/lY6Tb4gX">bandwidth</a> (GB/s) per APU</td><td colspan="2">29.866</td><td colspan="3">34.132</td><td colspan="2">38.400</td><td colspan="2">46.932</td><td colspan="2">68.256</td><td>102.400</td><td>83.200</td><td>120.000</td><td>10.666</td><td>12.800</td><td colspan="2">14.933</td><td>19.200</td><td>38.400</td><td>12.800</td><td>51.200</td><td>88.000</td></tr><tr><td colspan="3">GPU <a href="/facts/Microarchitecture/NFRd4NUL">microarchitecture</a></td><td><a href="/facts/TeraScale_(microarchitecture)/Yt6jwq9b">TeraScale 2 (VLIW5)</a></td><td colspan="2"><a href="/facts/TeraScale_(microarchitecture)/Yt6jwq9b">TeraScale 3 (VLIW4)</a></td><td colspan="2"><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN 2nd gen</a></td><td colspan="2"><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN 3rd gen</a></td><td colspan="4"><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN 5th gen</a><a class="footnote-ref" id="fnref:11" href="#fn:11"><sup>11</sup></a></td><td colspan="2"><a href="/facts/RDNA_2/tplgu8A1">RDNA 2</a></td><td><a href="/facts/RDNA_3/tCrEHPQu">RDNA 3</a></td><td><a href="/facts/TeraScale_(microarchitecture)/Yt6jwq9b">TeraScale 2 (VLIW5)</a></td><td colspan="3"><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN 2nd gen</a></td><td><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN 3rd gen</a><a class="footnote-ref" id="fnref:12" href="#fn:12"><sup>12</sup></a></td><td colspan="3"><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN 5th gen</a></td><td><a href="/facts/RDNA_2/tplgu8A1">RDNA 2</a></td></tr><tr><td colspan="3">GPU <a href="/facts/Instruction_set/8p8vwUeE">instruction set</a></td><td colspan="3"><a href="/facts/TeraScale_(microarchitecture)/Yt6jwq9b">TeraScale</a> instruction set</td><td colspan="8"><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN instruction set</a></td><td colspan="3"><a href="/facts/RDNA_(microarchitecture)/tplgu8A1">RDNA instruction set</a></td><td><a href="/facts/TeraScale_(microarchitecture)/Yt6jwq9b">TeraScale</a> instruction set</td><td colspan="7"><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN instruction set</a></td><td><a href="/facts/RDNA_(microarchitecture)/tplgu8A1">RDNA instruction set</a></td></tr><tr><td colspan="3">Max stock GPU base clock (MHz)</td><td>600</td><td>800</td><td>844</td><td colspan="2">866</td><td colspan="2">1108</td><td>1250</td><td>1400</td><td colspan="2">2100</td><td>2400</td><td>400</td><td></td><td>538</td><td>600</td><td>?</td><td>847</td><td>900</td><td>1200</td><td>600</td><td>1300</td><td>1900</td></tr><tr><td colspan="3">Max stock GPU base <a href="/facts/GFLOPS/6zYlH68F">GFLOPS</a><a class="footnote-ref" id="fnref:13" href="#fn:13"><sup>13</sup></a></td><td>480</td><td>614.4</td><td>648.1</td><td colspan="2">886.7</td><td colspan="2">1134.5</td><td>1760</td><td>1971.2</td><td colspan="2">2150.4</td><td>3686.4</td><td>102.4</td><td></td><td>86</td><td>?</td><td>?</td><td>?</td><td>345.6</td><td>460.8</td><td>230.4</td><td>1331.2</td><td>486.4</td></tr><tr><td rowspan="2" colspan="3">3D engine<a class="footnote-ref" id="fnref:14" href="#fn:14"><sup>14</sup></a></td><td>Up to 400:20:8</td><td colspan="2">Up to 384:24:6</td><td colspan="4">Up to 512:32:8</td><td colspan="2">Up to 704:44:16<a class="footnote-ref" id="fnref:15" href="#fn:15"><sup>15</sup></a></td><td colspan="2">Up to 512:32:8</td><td>768:48:8</td><td>128:8:4</td><td></td><td>80:8:4</td><td colspan="3">128:8:4</td><td>Up to 192:12:8</td><td>Up to 192:12:4</td><td>192:12:4</td><td>Up to 512:?:?</td><td>128:?:?</td></tr><tr><td colspan="3">IOMMUv1</td><td colspan="11"><a href="/facts/Heterogeneous_Memory_Management/uwayMPnT">IOMMUv2</a></td><td colspan="2">IOMMUv1</td><td colspan="2">?</td><td colspan="5">IOMMUv2</td></tr><tr><td colspan="3">Video decoder</td><td colspan="3"><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD 3.0</a></td><td colspan="2"><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD 4.2</a></td><td colspan="2"><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD 6.0</a></td><td rowspan="2" colspan="2"><a href="/facts/Video_Core_Next/I0GL8eMR">VCN</a> 1.0<a class="footnote-ref" id="fnref:16" href="#fn:16"><sup>16</sup></a></td><td rowspan="2">VCN 2.1<a class="footnote-ref" id="fnref:17" href="#fn:17"><sup>17</sup></a></td><td rowspan="2">VCN 2.2<a class="footnote-ref" id="fnref:18" href="#fn:18"><sup>18</sup></a></td><td colspan="2" rowspan="2">VCN 3.1</td><td rowspan="2">?</td><td><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD 3.0</a></td><td><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD 4.0</a></td><td colspan="2"><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD 4.2</a></td><td><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD 6.2</a></td><td rowspan="2" colspan="3"><a href="/facts/Video_Core_Next/I0GL8eMR">VCN 1.0</a></td><td rowspan="2">VCN 3.1</td></tr><tr><td colspan="3">Video encoder</td><td>—</td><td colspan="2"><a href="/facts/Video_Coding_Engine/4L5MLb6K">VCE 1.0</a></td><td colspan="2"><a href="/facts/Video_Coding_Engine/4L5MLb6K">VCE 2.0</a></td><td colspan="2"><a href="/facts/Video_Coding_Engine/4L5MLb6K">VCE 3.1</a></td><td>—</td><td colspan="3"><a href="/facts/Video_Coding_Engine/4L5MLb6K">VCE 2.0</a></td><td><a href="/facts/Video_Coding_Engine/4L5MLb6K">VCE 3.4</a></td></tr><tr><td colspan="3">AMD Fluid Motion</td><td colspan="3"></td><td colspan="4"></td><td colspan="7"></td><td colspan="2"></td><td colspan="3"></td><td colspan="4"></td></tr><tr><td colspan="3">GPU power saving</td><td><a href="/facts/AMD_PowerPlay/By12rf5S">PowerPlay</a></td><td colspan="13"><a href="/facts/AMD_PowerTune/NMNAqExx">PowerTune</a></td><td><a href="/facts/AMD_PowerPlay/By12rf5S">PowerPlay</a></td><td colspan="8"><a href="/facts/AMD_PowerTune/NMNAqExx">PowerTune</a><a class="footnote-ref" id="fnref:19" href="#fn:19"><sup>19</sup></a></td></tr><tr><td colspan="3"><a href="/facts/AMD_TrueAudio/085nbPwY">TrueAudio</a></td><td colspan="3" rowspan="2">—</td><td colspan="7"><a class="footnote-ref" id="fnref:20" href="#fn:20"><sup>20</sup></a></td><td colspan="4">?</td><td rowspan="2">—</td><td colspan="8"></td></tr><tr><td colspan="3"><a href="/facts/FreeSync/UzEbg48y">FreeSync</a></td><td colspan="11">12</td><td colspan="88">12</td></tr><tr><td colspan="3"><a href="/facts/HDCP/zYhpvdCz">HDCP</a><a class="footnote-ref" id="fnref:21" href="#fn:21"><sup>21</sup></a></td><td colspan="3">?</td><td colspan="4">1.4</td><td colspan="4">2.2</td><td colspan="3">2.3</td><td>?</td><td colspan="4">1.4</td><td colspan="3">2.2</td><td>2.3</td></tr><tr><td colspan="3"><a href="/facts/PlayReady/Cc0XStVx">PlayReady</a><a class="footnote-ref" id="fnref:22" href="#fn:22"><sup>22</sup></a></td><td colspan="7">—</td><td colspan="7">3.0 not yet</td><td colspan="5">—</td><td colspan="4">3.0 not yet</td></tr><tr><td colspan="3"><a href="/facts/AMD_Eyefinity/Rnw8Qk1v">Supported displays</a><a class="footnote-ref" id="fnref:23" href="#fn:23"><sup>23</sup></a></td><td>2–3</td><td colspan="4">2–4</td><td colspan="2">3</td><td colspan="2">3 (desktop)4 (mobile, embedded)</td><td colspan="5">4</td><td colspan="4">2</td><td>3</td><td>4</td><td></td><td colspan="2">4</td></tr><tr><td colspan="3">/drm/radeon<a class="footnote-ref" id="fnref:24" href="#fn:24"><sup>24</sup></a><a class="footnote-ref" id="fnref:25" href="#fn:25"><sup>25</sup></a><a class="footnote-ref" id="fnref:26" href="#fn:26"><sup>26</sup></a></td><td colspan="6"></td><td colspan="8">—</td><td colspan="4"></td><td colspan="5">—</td></tr><tr><td colspan="3">/drm/amdgpu<a class="footnote-ref" id="fnref:27" href="#fn:27"><sup>27</sup></a><a class="footnote-ref" id="fnref:28" href="#fn:28"><sup>28</sup></a></td><td colspan="3">—</td><td colspan="11"><a class="footnote-ref" id="fnref:29" href="#fn:29"><sup>29</sup></a></td><td>—</td><td colspan="8"><a class="footnote-ref" id="fnref:30" href="#fn:30"><sup>30</sup></a></td></tr></tbody></table> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">List of AMD processors with 3D graphics</a></li> <li><a href="/facts/List_of_AMD_mobile_processors/XTDTRHX5">List of AMD mobile processors</a></li></ul> <h2 id="external-links">External links</h2> <ul><li><a href="http://support.amd.com/us/Processor_TechDocs/44455.pdf">Socket FS1 Design Specification</a></li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>"AMD Announces the 7th Generation APU: Excavator mk2 in Bristol Ridge and Stoney Ridge for Notebooks". 31 May 2016. Retrieved 3 January 2020. <a href="https://www.anandtech.com/show/10362/amd-7th-generation-apu-bristol-ridge-stoney-ridge-for-notebooks" target="_blank">https://www.anandtech.com/show/10362/amd-7th-generation-apu-bristol-ridge-stoney-ridge-for-notebooks</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>"AMD Mobile "Carrizo" Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015" (Press release). 20 November 2014. Retrieved 16 February 2015. <a href="https://www.amd.com/en-us/press-releases/Pages/amd-mobile-carrizo-2014nov20.aspx" target="_blank">https://www.amd.com/en-us/press-releases/Pages/amd-mobile-carrizo-2014nov20.aspx</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>For FM2+ Excavator models: A8-7680, A6-7480 & Athlon X4 845. <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>"The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List". TechARP.com. Retrieved 13 December 2017. <a href="https://www.techarp.com/guides/mobile-cpu-comparison-guide/5/" target="_blank">https://www.techarp.com/guides/mobile-cpu-comparison-guide/5/</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>A PC would be one node. <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>An APU combines a CPU and a GPU. Both have cores. <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>Requires firmware support. <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> <li id="fn:8"><p>Requires firmware support. <a href="#fnref:8" class="footnote-back-ref">↩</a></p></li> <li id="fn:9"><p>Requires firmware support. <a href="#fnref:9" class="footnote-back-ref">↩</a></p></li> <li id="fn:10"><p>No SSE4. No SSSE3. <a href="#fnref:10" class="footnote-back-ref">↩</a></p></li> <li id="fn:11"><p>"AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver". VideoCardz.com. Retrieved 6 June 2017. <a href="http://videocardz.com/62250/amd-vega10-and-vega11-gpus-spotted-in-opencl-driver/" target="_blank">http://videocardz.com/62250/amd-vega10-and-vega11-gpus-spotted-in-opencl-driver/</a> <a href="#fnref:11" class="footnote-back-ref">↩</a></p></li> <li id="fn:12"><p>"AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver". VideoCardz.com. Retrieved 6 June 2017. <a href="http://videocardz.com/62250/amd-vega10-and-vega11-gpus-spotted-in-opencl-driver/" target="_blank">http://videocardz.com/62250/amd-vega10-and-vega11-gpus-spotted-in-opencl-driver/</a> <a href="#fnref:12" class="footnote-back-ref">↩</a></p></li> <li id="fn:13"><p>Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation. <a href="/wiki/Single-precision_floating-point_format" target="_blank">/wiki/Single-precision_floating-point_format</a> <a href="#fnref:13" class="footnote-back-ref">↩</a></p></li> <li id="fn:14"><p>Unified shaders : texture mapping units : render output units <a href="/wiki/Unified_shader_model" target="_blank">/wiki/Unified_shader_model</a> <a href="#fnref:14" class="footnote-back-ref">↩</a></p></li> <li id="fn:15"><p>Cutress, Ian (1 February 2018). "Zen Cores and Vega: Ryzen APUs for AM4 – AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm". Anandtech. Retrieved 7 February 2018. <a href="https://www.anandtech.com/show/12233/amd-tech-day-at-ces-2018-roadmap-revealed-with-ryzen-apus-zen-on-12nm-vega-on-7nm/3" target="_blank">https://www.anandtech.com/show/12233/amd-tech-day-at-ces-2018-roadmap-revealed-with-ryzen-apus-zen-on-12nm-vega-on-7nm/3</a> <a href="#fnref:15" class="footnote-back-ref">↩</a></p></li> <li id="fn:16"><p>Larabel, Michael (17 November 2017). "Radeon VCN Encode Support Lands in Mesa 17.4 Git". Phoronix. Retrieved 20 November 2017. <a href="https://www.phoronix.com/scan.php?page=news_item&px=Radeon-VCN-Encode-Lands" target="_blank">https://www.phoronix.com/scan.php?page=news_item&px=Radeon-VCN-Encode-Lands</a> <a href="#fnref:16" class="footnote-back-ref">↩</a></p></li> <li id="fn:17"><p>"AMD Ryzen 5000G 'Cezanne' APU Gets First High-Res Die Shots, 10.7 Billion Transistors In A 180mm2 Package". wccftech. Aug 12, 2021. Retrieved August 25, 2021. <a href="https://wccftech.com/amd-ryzen-5000g-cezanne-apu-first-high-res-die-shots-10-7-billion-transistors/" target="_blank">https://wccftech.com/amd-ryzen-5000g-cezanne-apu-first-high-res-die-shots-10-7-billion-transistors/</a> <a href="#fnref:17" class="footnote-back-ref">↩</a></p></li> <li id="fn:18"><p>"AMD Ryzen 5000G 'Cezanne' APU Gets First High-Res Die Shots, 10.7 Billion Transistors In A 180mm2 Package". wccftech. Aug 12, 2021. Retrieved August 25, 2021. <a href="https://wccftech.com/amd-ryzen-5000g-cezanne-apu-first-high-res-die-shots-10-7-billion-transistors/" target="_blank">https://wccftech.com/amd-ryzen-5000g-cezanne-apu-first-high-res-die-shots-10-7-billion-transistors/</a> <a href="#fnref:18" class="footnote-back-ref">↩</a></p></li> <li id="fn:19"><p>Tony Chen; Jason Greaves, "AMD's Graphics Core Next (GCN) Architecture" (PDF), AMD, retrieved 13 August 2016 <a href="http://meseec.ce.rit.edu/551-projects/fall2014/3-4.pdf" target="_blank">http://meseec.ce.rit.edu/551-projects/fall2014/3-4.pdf</a> <a href="#fnref:19" class="footnote-back-ref">↩</a></p></li> <li id="fn:20"><p>"A technical look at AMD's Kaveri architecture". Semi Accurate. Retrieved 6 July 2014. <a href="http://semiaccurate.com/2014/01/15/technical-look-amds-kaveri-architecture/" target="_blank">http://semiaccurate.com/2014/01/15/technical-look-amds-kaveri-architecture/</a> <a href="#fnref:20" class="footnote-back-ref">↩</a></p></li> <li id="fn:21"><p>To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup. <a href="#fnref:21" class="footnote-back-ref">↩</a></p></li> <li id="fn:22"><p>To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup. <a href="#fnref:22" class="footnote-back-ref">↩</a></p></li> <li id="fn:23"><p>To feed more than two displays, the additional panels must have native DisplayPort support.[10] Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed. <a href="/wiki/DisplayPort" target="_blank">/wiki/DisplayPort</a> <a href="#fnref:23" class="footnote-back-ref">↩</a></p></li> <li id="fn:24"><p>DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version. <a href="/wiki/Direct_Rendering_Manager" target="_blank">/wiki/Direct_Rendering_Manager</a> <a href="#fnref:24" class="footnote-back-ref">↩</a></p></li> <li id="fn:25"><p>Airlie, David (26 November 2009). "DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33". Retrieved 16 January 2016. <a href="http://airlied.livejournal.com/68805.html" target="_blank">http://airlied.livejournal.com/68805.html</a> <a href="#fnref:25" class="footnote-back-ref">↩</a></p></li> <li id="fn:26"><p>"Radeon feature matrix". freedesktop.org. Retrieved 10 January 2016. <a href="http://xorg.freedesktop.org/wiki/RadeonFeature/" target="_blank">http://xorg.freedesktop.org/wiki/RadeonFeature/</a> <a href="#fnref:26" class="footnote-back-ref">↩</a></p></li> <li id="fn:27"><p>DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version. <a href="/wiki/Direct_Rendering_Manager" target="_blank">/wiki/Direct_Rendering_Manager</a> <a href="#fnref:27" class="footnote-back-ref">↩</a></p></li> <li id="fn:28"><p>Deucher, Alexander (16 September 2015). "XDC2015: AMDGPU" (PDF). Retrieved 16 January 2016. <a href="http://www.x.org/wiki/Events/XDC2015/Program/deucher_zhou_amdgpu.pdf" target="_blank">http://www.x.org/wiki/Events/XDC2015/Program/deucher_zhou_amdgpu.pdf</a> <a href="#fnref:28" class="footnote-back-ref">↩</a></p></li> <li id="fn:29"><p>Michel Dänzer (17 November 2016). "[ANNOUNCE] xf86-video-amdgpu 1.2.0". lists.x.org. <a href="https://lists.x.org/archives/xorg-announce/2016-November/002741.html" target="_blank">https://lists.x.org/archives/xorg-announce/2016-November/002741.html</a> <a href="#fnref:29" class="footnote-back-ref">↩</a></p></li> <li id="fn:30"><p>Michel Dänzer (17 November 2016). "[ANNOUNCE] xf86-video-amdgpu 1.2.0". lists.x.org. <a href="https://lists.x.org/archives/xorg-announce/2016-November/002741.html" target="_blank">https://lists.x.org/archives/xorg-announce/2016-November/002741.html</a> <a href="#fnref:30" class="footnote-back-ref">↩</a></p></li> </ol>