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CPUID
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<h2 id="history">History</h2> <p>Prior to the general availability of the CPUID instruction, programmers would write esoteric <a href="/facts/Machine_code/bgdQ1Fxf">machine code</a> which exploited minor differences in CPU behavior in order to determine the processor make and model.<a class="footnote-ref" id="fnref:2" href="#fn:2"><sup>2</sup></a><a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a><a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a><a class="footnote-ref" id="fnref:5" href="#fn:5"><sup>5</sup></a> With the introduction of the 80386 processor, EDX on reset indicated the revision but this was only readable after reset and there was no standard way for applications to read the value. </p><p>Outside the x86 family, developers are mostly still required to use esoteric processes (involving instruction timing or CPU fault triggers) to determine the variations in CPU design that are present. </p><p>For example, in the <a href="/facts/Motorola_68000_series/jxd7VPlW">Motorola 68000 series</a> — which never had a CPUID instruction of any kind — certain specific instructions required elevated privileges. These could be used to tell various CPU family members apart. In the <a href="/facts/Motorola_68010/tSoQFndh">Motorola 68010</a> the instruction <i>MOVE from SR</i> became privileged. Because the <a href="/facts/Motorola_68000/3p2wt2D6">68000</a> offered an unprivileged <i>MOVE from SR</i> the two different CPUs could be told apart by a CPU error condition being triggered. </p><p>While the CPUID instruction is specific to the x86 architecture, other architectures (like ARM) often provide on-chip registers which can be read in prescribed ways to obtain the same sorts of information provided by the x86 CPUID instruction. </p> <h2 id="calling-cpuid">Calling CPUID</h2> <p>The CPUID opcode is 0F A2. </p><p>In <a href="/facts/Assembly_language/7XuV0cla">assembly language</a>, the CPUID instruction takes no parameters as CPUID implicitly uses the EAX register to determine the main category of information returned. In Intel's more recent terminology, this is called the CPUID leaf. CPUID should be called with EAX = 0 first, as this will store in the EAX register the highest EAX calling parameter (leaf) that the CPU implements. </p><p>To obtain extended function information CPUID should be called with the most significant bit of EAX set. To determine the highest extended function calling parameter, call CPUID with EAX = 80000000h. </p><p>CPUID leaves greater than 3 but less than 80000000 are accessible only when the <a href="/facts/Model-specific_register/uzoD3Ynm">model-specific registers</a> have IA32_MISC_ENABLE.BOOT_NT4 [bit 22] = 0 (which is so by default). As the name suggests, <a href="/facts/Windows_NT_4.0/EcKYxrkx">Windows NT 4.0</a> until SP6 did not boot properly unless this bit was set,<a class="footnote-ref" id="fnref:6" href="#fn:6"><sup>6</sup></a> but later versions of Windows do not need it, so basic leaves greater than 4 can be assumed visible on current Windows systems. As of April 2024, basic valid leaves go up to 23h, but the information returned by some leaves are not disclosed in the publicly available documentation, i.e. they are "reserved". </p><p>Some of the more recently added leaves also have sub-leaves, which are selected via the ECX register before calling CPUID. </p> <h2 id="eax0-highest-function-parameter-and-manufacturer-id">EAX=0: Highest Function Parameter and Manufacturer ID</h2> <p>This returns the CPU's manufacturer ID string – a twelve-character <a href="/facts/ASCII/vGUI33Qu">ASCII</a> string stored in EBX, EDX, ECX (in that order). The highest basic calling parameter (the largest value that EAX can be set to before calling CPUID) is returned in EAX. </p><p>Here is a list of processors and the highest function implemented. </p> Highest Function Parameter<table><tbody><tr><th>Processors</th><th>Basic</th><th>Extended</th></tr><tr><td>Earlier <a href="/facts/Intel_80486/2zfEAXAw">Intel 486</a></td><td colspan="2"><i>CPUID Not Implemented</i></td></tr><tr><td>Later Intel 486 and <a href="/facts/Pentium/czINY469">Pentium</a></td><td>0x01</td><td><i>Not Implemented</i></td></tr><tr><td><a href="/facts/Pentium_Pro/mTAN64fo">Pentium Pro</a>, <a href="/facts/Pentium_II/VoHQLV1s">Pentium II</a> and <a href="/facts/Celeron/kX00LpnM">Celeron</a></td><td>0x02</td><td><i>Not Implemented</i></td></tr><tr><td><a href="/facts/Pentium_III/sV1v2Frq">Pentium III</a></td><td>0x03</td><td><i>Not Implemented</i></td></tr><tr><td><a href="/facts/Pentium_4/6tIFuHIF">Pentium 4</a></td><td>0x02</td><td>0x8000 0004</td></tr><tr><td><a href="/facts/Xeon/j1M8Hp6D">Xeon</a></td><td>0x02</td><td>0x8000 0004</td></tr><tr><td><a href="/facts/Pentium_M/TwKtPHcm">Pentium M</a></td><td>0x02</td><td>0x8000 0004</td></tr><tr><td>Pentium 4 with <a href="/facts/Hyper-Threading/hjqGgK8V">Hyper-Threading</a></td><td>0x05</td><td>0x8000 0008</td></tr><tr><td><a href="/facts/Pentium_D/rLD9pQ8F">Pentium D</a> (8xx)</td><td>0x05</td><td>0x8000 0008</td></tr><tr><td>Pentium D (9xx)</td><td>0x06</td><td>0x8000 0008</td></tr><tr><td><a href="/facts/Intel_Core/lwa8VSdT">Core Duo</a></td><td>0x0A</td><td>0x8000 0008</td></tr><tr><td><a href="/facts/Intel_Core/lwa8VSdT">Core 2 Duo</a></td><td>0x0A</td><td>0x8000 0008</td></tr><tr><td>Xeon <a href="/facts/List_of_Intel_Nehalem-based_Xeon_microprocessors/dNIkR6Qh">3000</a>, 5100, 5200, 5300, 5400 (<a href="/facts/List_of_Intel_Nehalem-based_Xeon_microprocessors/dNIkR6Qh">5000 series</a>)</td><td>0x0A</td><td>0x8000 0008</td></tr><tr><td>Core 2 Duo <a href="/facts/Wolfdale_(microprocessor)/m9aFgKmz">8000 series</a></td><td>0x0D</td><td>0x8000 0008</td></tr><tr><td>Xeon 5200, 5400 series</td><td>0x0A</td><td>0x8000 0008</td></tr><tr><td><a href="/facts/Intel_Atom/1rB5zJyz">Atom</a></td><td>0x0A</td><td>0x8000 0008</td></tr><tr><td><a href="/facts/Nehalem_(microarchitecture)/UPsI457h">Nehalem</a>-based processors</td><td>0x0B</td><td>0x8000 0008</td></tr><tr><td><a href="/facts/Ivy_Bridge_(microarchitecture)/VklHpEK1">Ivy Bridge</a>-based processors</td><td>0x0D</td><td>0x8000 0008</td></tr><tr><td><a href="/facts/Skylake_(microarchitecture)/qpcDcebM">Skylake</a>-based processors (proc base & max freq; Bus ref. freq)</td><td>0x16</td><td>0x8000 0008</td></tr><tr><td><a href="/facts/System_on_a_chip/1RVvVe6N">System-On-Chip</a> Vendor Attribute Enumeration Main Leaf</td><td>0x17</td><td>0x8000 0008</td></tr><tr><td><a href="/facts/Meteor_Lake/6kounHDU">Meteor Lake</a>-based processors</td><td>0x23</td><td>0x8000 0008</td></tr></tbody></table> <p>The following are known processor manufacturer ID strings: </p> <ul><li>"AuthenticAMD" – <a href="/facts/Advanced_Micro_Devices/CB1G7QTb">AMD</a></li> <li>"CentaurHauls" – <a href="/facts/Integrated_Device_Technology/vuXjhG5H">IDT</a> WinChip/<a href="/facts/Centaur_Technology/blY0qw55">Centaur</a> (Including some VIA and Zhaoxin CPUs)</li> <li>"CyrixInstead" – <a href="/facts/Cyrix/zPI6NhTm">Cyrix</a>/early <a href="/facts/STMicroelectronics/4gbGJTVr">STMicroelectronics</a> and <a href="/facts/IBM/QszA7nwd">IBM</a></li> <li>"GenuineIntel" – <a href="/facts/Intel/SMF0gJJX">Intel</a></li> <li>"GenuineIotel" – Intel (rare)<a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a><a class="footnote-ref" id="fnref:8" href="#fn:8"><sup>8</sup></a></li> <li>"TransmetaCPU" – <a href="/facts/Transmeta/RmnrADmX">Transmeta</a></li> <li>"GenuineTMx86" – <a href="/facts/Transmeta/RmnrADmX">Transmeta</a></li> <li>"Geode by NSC" – <a href="/facts/National_Semiconductor/xeAD8doA">National Semiconductor</a></li> <li>"NexGenDriven" – <a href="/facts/NexGen/7WWCsBnP">NexGen</a></li> <li>"RiseRiseRise" – <a href="/facts/Rise_Technology/37xhy7Vf">Rise</a></li> <li>"SiS SiS SiS " – <a href="/facts/Silicon_Integrated_Systems/KFLvP1No">SiS</a></li> <li>"UMC UMC UMC " – <a href="/facts/United_Microelectronics_Corporation/yWTN3oDV">UMC</a></li> <li>"Vortex86 SoC" – DM&P <a href="/facts/Vortex86/EbQ03bc5">Vortex86</a></li> <li>" Shanghai " – <a href="/facts/Zhaoxin/2wpVktlp">Zhaoxin</a></li> <li>"HygonGenuine" – <a href="/facts/AMD%25E2%2580%2593Chinese_joint_venture/U3J8x7zT">Hygon</a></li> <li>"Genuine RDC" – RDC Semiconductor Co. Ltd.<a class="footnote-ref" id="fnref:9" href="#fn:9"><sup>9</sup></a></li> <li>"E2K MACHINE" – <a href="/facts/Elbrus_(computer)/cFAIaDlB">MCST Elbrus</a><a class="footnote-ref" id="fnref:10" href="#fn:10"><sup>10</sup></a></li> <li>"VIA VIA VIA " – <a href="/facts/VIA_Technologies/g6REHNFE">VIA</a></li> <li>"AMD ISBETTER" – early engineering samples of <a href="/facts/AMD_K5/IPMKlDsR">AMD K5</a> processor<a class="footnote-ref" id="fnref:11" href="#fn:11"><sup>11</sup></a><a class="footnote-ref" id="fnref:12" href="#fn:12"><sup>12</sup></a>[<i>better source needed</i>]</li></ul> <p>The following are ID strings used by open source <a href="/facts/Soft_microprocessor/pCmb601M">soft CPU cores</a>: </p> <ul><li>"GenuineAO486" – ao486 CPU (old)<a class="footnote-ref" id="fnref:13" href="#fn:13"><sup>13</sup></a><a class="footnote-ref" id="fnref:14" href="#fn:14"><sup>14</sup></a></li> <li>"MiSTer AO486" – ao486 CPU (new)<a class="footnote-ref" id="fnref:15" href="#fn:15"><sup>15</sup></a><a class="footnote-ref" id="fnref:16" href="#fn:16"><sup>16</sup></a></li> <li>"GenuineIntel" – v586 core<a class="footnote-ref" id="fnref:17" href="#fn:17"><sup>17</sup></a> (this is identical to the Intel ID string)</li></ul> <p>The following are known ID strings from virtual machines: </p> <ul><li>"MicrosoftXTA" – Microsoft x86-to-ARM<a class="footnote-ref" id="fnref:18" href="#fn:18"><sup>18</sup></a></li> <li>"GenuineIntel" – <a href="/facts/Rosetta_(software)/9snj5mV4">Apple Rosetta 2</a><a class="footnote-ref" id="fnref:19" href="#fn:19"><sup>19</sup></a></li> <li>"VirtualApple" – Newer versions of Apple Rosetta 2</li> <li>"PowerVM Lx86" – <a href="/facts/PowerVM_Lx86/4LMJ6mKD">PowerVM Lx86</a> (x86 emulator for IBM <a href="/facts/POWER5/bvj1ELch">POWER5</a>/<a href="/facts/POWER6/GqfSuMVM">POWER6</a> processors)<a class="footnote-ref" id="fnref:20" href="#fn:20"><sup>20</sup></a></li> <li>"Neko Project" – Neko Project II (<a href="/facts/PC-98/b0br6zGu">PC-98</a> emulator) (used when the CPU to emulate is set to "Neko Processor II")<a class="footnote-ref" id="fnref:21" href="#fn:21"><sup>21</sup></a><a class="footnote-ref" id="fnref:22" href="#fn:22"><sup>22</sup></a></li></ul> <p>For instance, on a GenuineIntel processor, values returned in EBX is 0x756e6547, EDX is 0x49656e69 and ECX is 0x6c65746e. The following example code displays the vendor ID string as well as the highest calling parameter that the CPU implements. </p> .intel_syntax noprefix .text .m0: .string "CPUID: %x\n" .m1: .string "Largest basic function number implemented: %i\n" .m2: .string "Vendor ID: %s\n" .globl main main: push r12 mov eax, 1 sub rsp, 16 cpuid lea rdi, .m0[rip] mov esi, eax call printf mov eax, 0 cpuid lea rdi, .m1[rip] mov esi, eax mov r12d, edx mov ebp, ecx call printf mov 3[rsp], ebx lea rsi, 3[rsp] lea rdi, .m2[rip] mov 7[rsp], r12d mov 11[rsp], ebp call printf add rsp, 16 pop r12 ret .section .note.GNU-stack,"",@progbits <p>On some processors, it is possible to modify the Manufacturer ID string reported by CPUID.(EAX=0) by writing a new ID string to particular MSRs (<a href="/facts/Model-specific_register/uzoD3Ynm">Model-specific registers</a>) using the WRMSR instruction. This has been used on non-Intel processors to enable features and optimizations that have been disabled in software for CPUs that don't return the GenuineIntel ID string.<a class="footnote-ref" id="fnref:23" href="#fn:23"><sup>23</sup></a> Processors that are known to possess such MSRs include: </p> Processors with Manufacturer ID MSRs<table><tbody><tr><th>Processor</th><th>MSRs</th></tr><tr><td>IDT <a href="/facts/WinChip/mslaY86X">WinChip</a></td><td>108h-109h<a class="footnote-ref" id="fnref:24" href="#fn:24"><sup>24</sup></a></td></tr><tr><td><a href="/facts/VIA_C3/Y4IQ8VCd">VIA C3</a>, <a href="/facts/VIA_C7/a4nqwGyr">C7</a></td><td>1108h-1109h<a class="footnote-ref" id="fnref:25" href="#fn:25"><sup>25</sup></a></td></tr><tr><td><a href="/facts/VIA_Nano/82nYJeBy">VIA Nano</a></td><td>1206h-1207h<a class="footnote-ref" id="fnref:26" href="#fn:26"><sup>26</sup></a></td></tr><tr><td><a href="/facts/Transmeta_Crusoe/gHy6WQRg">Transmeta Crusoe</a>, <a href="/facts/Transmeta_Efficeon/nCNXoEHv">Efficeon</a></td><td>80860001h-80860003h<a class="footnote-ref" id="fnref:27" href="#fn:27"><sup>27</sup></a><a class="footnote-ref" id="fnref:28" href="#fn:28"><sup>28</sup></a></td></tr><tr><td>AMD <a href="/facts/Geode_(processor)/uIL9401N">Geode</a> GX, LX</td><td>3000h-3001h<a class="footnote-ref" id="fnref:29" href="#fn:29"><sup>29</sup></a></td></tr><tr><td>DM&P <a href="/facts/Vortex86/EbQ03bc5">Vortex86</a>EX2</td><td>52444300h-52444301h<a class="footnote-ref" id="fnref:30" href="#fn:30"><sup>30</sup></a></td></tr></tbody></table> <h2 id="eax1-processor-info-and-feature-bits">EAX=1: Processor Info and Feature Bits</h2> <p>This returns the CPU's <a href="/facts/Stepping_(version_numbers)/L72oFc8s">stepping</a>, model, and family information in register EAX (also called the <i>signature</i> of a CPU), feature flags in registers EDX and ECX, and additional feature info in register EBX.<a class="footnote-ref" id="fnref:31" href="#fn:31"><sup>31</sup></a> </p> CPUID EAX=1: Processor Version Information in EAX<table><tbody><tr><th colspan="32">EAX</th></tr><tr><th>31</th><th>30</th><th>29</th><th>28</th><th>27</th><th>26</th><th>25</th><th>24</th><th>23</th><th>22</th><th>21</th><th>20</th><th>19</th><th>18</th><th>17</th><th>16</th><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th></tr><tr><td colspan="4">Reserved</td><td colspan="8">Extended Family ID</td><td colspan="4">Extended Model ID</td><td colspan="2">Reserved</td><td colspan="2">Processor Type</td><td colspan="4">Family ID</td><td colspan="4">Model</td><td colspan="4">Stepping ID</td></tr></tbody></table> <ul><li>Stepping ID is a product revision number assigned due to fixed <a href="/facts/Errata/8zhGTlMe">errata</a> or other changes.</li> <li>The actual processor model is derived from the Model, Extended Model ID and Family ID fields. If the Family ID field is either 6 or 15, the model is equal to the sum of the Extended Model ID field shifted left by 4 bits and the Model field. Otherwise, the model is equal to the value of the Model field.</li> <li>The actual processor family is derived from the Family ID and Extended Family ID fields. If the Family ID field is equal to 15, the family is equal to the sum of the Extended Family ID and the Family ID fields. Otherwise, the family is equal to the value of the Family ID field.</li> <li>The meaning of the Processor Type field is given in the table below.</li></ul> Processor Type<table><tbody><tr><th>Type</th><th>Encoding in <a href="/facts/Binary_number/a6JDSRPs">Binary</a></th></tr><tr><td>Original equipment manufacturer (<a href="/facts/Original_equipment_manufacturer/hmUhIWaS">OEM</a>) Processor</td><td>00</td></tr><tr><td><a href="/facts/Pentium_OverDrive/dq5xG2mt">Intel Overdrive Processor</a></td><td>01</td></tr><tr><td>Dual processor (applicable to Intel <a href="/facts/Pentium_(original)/dqChAmxz">P5 Pentium</a> processors only)<a class="footnote-ref" id="fnref:32" href="#fn:32"><sup>32</sup></a></td><td>10</td></tr><tr><td>Reserved value</td><td>11</td></tr></tbody></table> <p>As of October 2023, the following x86 processor family IDs are known:<a class="footnote-ref" id="fnref:33" href="#fn:33"><sup>33</sup></a> </p> CPUID EAX=1: Processor Family IDs<table><tbody><tr><th>Family ID +Extended Family ID</th><th>Intel</th><th>AMD</th><th>Other</th></tr><tr><th>0h</th><td>—</td><td>—</td><td>—</td></tr><tr><th>1h</th><td>—</td><td>—</td><td>—</td></tr><tr><th>2h</th><td>—</td><td>—</td><td>—</td></tr><tr><th>3h</th><td><a class="footnote-ref" id="fnref:34" href="#fn:34"><sup>34</sup></a></td><td>—</td><td>—</td></tr><tr><th>4h</th><td><a href="/facts/I486/2zfEAXAw">486</a></td><td><a href="/facts/Am486/XNm27388">486</a>,<a class="footnote-ref" id="fnref:35" href="#fn:35"><sup>35</sup></a><a href="/facts/Am5x86/gEkcuv5V">5x86</a>,<a href="/facts/AMD_%25C3%2589lan/sbDsGlmx">Élan</a> SC4xx/5xx<a class="footnote-ref" id="fnref:36" href="#fn:36"><sup>36</sup></a></td><td><a href="/facts/Cyrix_5x86/UatSfAUo">Cyrix 5x86</a>,<a class="footnote-ref" id="fnref:37" href="#fn:37"><sup>37</sup></a>Cyrix <a href="/facts/MediaGX/d1BYh1Am">MediaGX</a>,<a class="footnote-ref" id="fnref:38" href="#fn:38"><sup>38</sup></a><a href="/facts/UMC_Green_CPU/WGcWVsrG">UMC Green CPU</a>,<a class="footnote-ref" id="fnref:39" href="#fn:39"><sup>39</sup></a><a href="/facts/MCST/CCL36FC6">MCST</a> Elbrus (most models),<a class="footnote-ref" id="fnref:40" href="#fn:40"><sup>40</sup></a><a href="/facts/MiSTer/RPl00z2N">MiSTer</a> ao486<a class="footnote-ref" id="fnref:41" href="#fn:41"><sup>41</sup></a></td></tr><tr><th>5h</th><td><a href="/facts/Pentium_(original)/dqChAmxz">Pentium</a>,<a href="/facts/Pentium_MMX/dqChAmxz">Pentium MMX</a>,<a href="/facts/Intel_Quark/rbSHugev">Quark X1000</a></td><td><a href="/facts/AMD_K5/IPMKlDsR">K5</a>,<a href="/facts/AMD_K6/VSDY3GcM">K6</a></td><td><a href="/facts/Cyrix_6x86/q43nNY14">Cyrix 6x86</a>,Cyrix <a href="/facts/MediaGX/d1BYh1Am">MediaGXm</a>,<a class="footnote-ref" id="fnref:42" href="#fn:42"><sup>42</sup></a><a href="/facts/Geode_(processor)/uIL9401N">Geode</a> (except NX),<a href="/facts/NexGen/7WWCsBnP">NexGen</a> Nx586,<a class="footnote-ref" id="fnref:43" href="#fn:43"><sup>43</sup></a>IDT <a href="/facts/WinChip/mslaY86X">WinChip</a>,IDT WinChip 2,IDT WinChip 3,<a href="/facts/Transmeta_Crusoe/gHy6WQRg">Transmeta Crusoe</a>,Rise <a href="/facts/MP6/zMK09BPP">mP6</a>,<a href="/facts/Silicon_Integrated_Systems/KFLvP1No">SiS</a> 550,DM&P <a href="/facts/Vortex86/EbQ03bc5">Vortex86</a> (early),<a class="footnote-ref" id="fnref:44" href="#fn:44"><sup>44</sup></a>RDC IAD 100,<a href="/facts/MCST/CCL36FC6">MCST</a> Elbrus-8C2<a class="footnote-ref" id="fnref:45" href="#fn:45"><sup>45</sup></a></td></tr><tr><th>6h</th><td><a href="/facts/Pentium_Pro/mTAN64fo">Pentium Pro</a>,<a href="/facts/Pentium_II/VoHQLV1s">Pentium II</a>,<a href="/facts/Pentium_III/sV1v2Frq">Pentium III</a>,<a href="/facts/Pentium_M/TwKtPHcm">Pentium M</a>,<a href="/facts/Intel_Core/lwa8VSdT">Intel Core</a> (all variants),<a href="/facts/Intel_Atom/1rB5zJyz">Intel Atom</a> (all variants),<a href="/facts/Xeon/j1M8Hp6D">Xeon</a> (except NetBurst <a href="/facts/List_of_Intel_Xeon_processors_(NetBurst-based)/WthwFvBH">variants</a>),<a href="/facts/Xeon_Phi/Fv5dhyKc">Xeon Phi</a> (except KNC)</td><td>K7: <a href="/facts/Athlon/3BFQu05f">Athlon</a>,<a href="/facts/Athlon_XP/3BFQu05f">Athlon XP</a></td><td><a href="/facts/Cyrix_6x86/q43nNY14">Cyrix 6x86</a>MX/MII,<a href="/facts/VIA_C3/Y4IQ8VCd">VIA C3</a>,<a href="/facts/VIA_C7/a4nqwGyr">VIA C7</a>,<a href="/facts/VIA_Nano/82nYJeBy">VIA Nano</a>,DM&P <a href="/facts/Vortex86/EbQ03bc5">Vortex86</a> (DX3,EX2<a class="footnote-ref" id="fnref:46" href="#fn:46"><sup>46</sup></a>),<a href="/facts/Zhaoxin/2wpVktlp">Zhaoxin</a> ZX-A/B/C/C+,(<a href="/facts/Centaur_Technology/blY0qw55">Centaur CNS</a><a class="footnote-ref" id="fnref:47" href="#fn:47"><sup>47</sup></a>),<a href="/facts/MCST/CCL36FC6">MCST</a> Elbrus-12C/16C/2C3<a class="footnote-ref" id="fnref:48" href="#fn:48"><sup>48</sup></a></td></tr><tr><th>7h</th><td><a href="/facts/Itanium/0wkjSDpe">Itanium</a>(in IA-32 mode)</td><td>—</td><td><a href="/facts/Zhaoxin/2wpVktlp">Zhaoxin</a> KaiXian,<a href="/facts/Zhaoxin/2wpVktlp">Zhaoxin</a> KaisHeng</td></tr><tr><th>8h</th><td><a class="footnote-ref" id="fnref:49" href="#fn:49"><sup>49</sup></a></td><td>—</td><td>—</td></tr><tr><th>9h</th><td>—</td><td>—</td><td>—</td></tr><tr><th>0Ah</th><td>—</td><td>—</td><td>—</td></tr><tr><th>0Bh</th><td><a href="/facts/Xeon_Phi/Fv5dhyKc">Xeon Phi</a> (Knights Corner)<a class="footnote-ref" id="fnref:50" href="#fn:50"><sup>50</sup></a></td><td>—</td><td>—</td></tr><tr><th>0Ch</th><td>—</td><td>—</td><td>—</td></tr><tr><th>0Dh</th><td>—</td><td>—</td><td>—</td></tr><tr><th>0Eh</th><td>—</td><td>—</td><td>—</td></tr><tr><th>0Fh</th><td><a href="/facts/NetBurst/QIkVG48W">NetBurst</a> (Pentium 4)</td><td>K8/Hammer(<a href="/facts/Athlon_64/3JLpVnQd">Athlon 64</a>)</td><td><a href="/facts/Transmeta_Efficeon/nCNXoEHv">Transmeta Efficeon</a></td></tr><tr><th>10h</th><td>—</td><td><a href="/facts/AMD_10h/2hQAazep">K10</a>: <a href="/facts/AMD_Phenom/TaGxakcd">Phenom</a></td><td>—</td></tr><tr><th>11h</th><td><a href="/facts/Itanium_2/0wkjSDpe">Itanium 2</a><a class="footnote-ref" id="fnref:51" href="#fn:51"><sup>51</sup></a>(in IA-32 mode)</td><td><a href="/facts/AMD_10h/2hQAazep">Turion X2</a></td><td>—</td></tr><tr><th>12h</th><td>—</td><td><a href="/facts/AMD_10h/2hQAazep">Llano</a></td><td>—</td></tr><tr><th>13h</th><td><a href="/facts/Intel_Core/lwa8VSdT">Intel Core</a> (Panther Cove and up)<a class="footnote-ref" id="fnref:52" href="#fn:52"><sup>52</sup></a></td><td>—</td><td>—</td></tr><tr><th>14h</th><td>—</td><td><a href="/facts/Bobcat_(microarchitecture)/EweFKE9J">Bobcat</a></td><td>—</td></tr><tr><th>15h</th><td>—</td><td><a href="/facts/Bulldozer_(microarchitecture)/fUPzoGrd">Bulldozer</a>,<a href="/facts/Piledriver_(microarchitecture)/Fhxly06H">Piledriver</a>,<a href="/facts/Steamroller_(microarchitecture)/SxtLaauz">Steamroller</a>,<a href="/facts/Excavator_(microarchitecture)/Bzj9WKGV">Excavator</a></td><td>—</td></tr><tr><th>16h</th><td>—</td><td><a href="/facts/Jaguar_(microarchitecture)/PkCbNj9a">Jaguar</a>,<a href="/facts/Puma_(microarchitecture)/ujJ1MBg1">Puma</a></td><td>—</td></tr><tr><th>17h</th><td>—</td><td><a href="/facts/Zen_(first_generation)/oChXIp3y">Zen 1</a>,<a href="/facts/Zen_2/pdL7I80c">Zen 2</a></td><td>—</td></tr><tr><th>18h</th><td>—</td><td colspan="2"><a href="/facts/AMD%25E2%2580%2593Chinese_joint_venture/U3J8x7zT">Hygon Dhyana</a></td></tr><tr><th>19h</th><td>—</td><td><a href="/facts/Zen_3/szGTAfyB">Zen 3</a>,<a href="/facts/Zen_4/UJXLYNuq">Zen 4</a></td><td>—</td></tr><tr><th>1Ah</th><td>—</td><td><a href="/facts/Zen_5/UJXLYNuq">Zen 5</a></td><td>—</td></tr></tbody></table> CPUID EAX=1: Additional Information in EBX<table><tbody><tr><th>Bits</th><th>EBX</th><th>Valid</th></tr><tr><th>7:0</th><td>Brand Index</td><td></td></tr><tr><th>15:8</th><td>CLFLUSH line size (Value * 8 = cache line size in bytes)</td><td>if CLFLUSH feature flag is set.<p>CPUID.01.EDX.CLFSH [bit 19]= 1</p></td></tr><tr><th>23:16</th><td>Maximum number of addressable IDs for logical processors in this physical package;<p>The nearest power-of-2 integer that is not smaller than this value is the number of unique initial APIC IDs reserved for addressing different logical processors in a physical package.<a class="footnote-ref" id="fnref:53" href="#fn:53"><sup>53</sup></a></p><p>Former use: Number of logical processors per physical processor; two for the Pentium 4 processor with Hyper-Threading Technology.<a class="footnote-ref" id="fnref:54" href="#fn:54"><sup>54</sup></a></p></td><td>if <a href="/facts/Hyper-threading/hjqGgK8V">Hyper-threading</a> feature flag is set.<p>CPUID.01.EDX.HTT [bit 28]= 1</p></td></tr><tr><th>31:24</th><td>Local APIC ID: The initial APIC-ID is used to identify the executing logical processor.<a class="footnote-ref" id="fnref:55" href="#fn:55"><sup>55</sup></a></td><td>Pentium 4 and subsequent processors.</td></tr></tbody></table> <p>The processor info and feature flags are manufacturer specific but usually, the Intel values are used by other manufacturers for the sake of compatibility. </p> CPUID EAX=1: Feature Information in EDX and ECX<table><tbody><tr><th rowspan="2">Bit</th><th colspan="2">EDX</th><th scope="col" rowspan="34"></th><th colspan="2">ECX<a class="footnote-ref" id="fnref:56" href="#fn:56"><sup>56</sup></a></th><th rowspan="2">Bit</th></tr><tr><th>Short</th><th>Feature</th><th>Short</th><th>Feature</th></tr><tr><th>0</th><td>fpu</td><td>Onboard <a href="/facts/X87/y8X9HnLL">x87</a> FPU</td><td>sse3</td><td>SSE3 (<a href="/facts/Prescott_New_Instructions/Ch9oP4oh">Prescott New Instructions</a> - PNI)</td><th>0</th></tr><tr><th>1</th><td>vme</td><td><a href="/facts/Virtual_8086_Mode_Extensions/f4fjXWdU">Virtual 8086 mode extensions</a> (such as VIF, VIP, PVI)</td><td>pclmulqdq</td><td><a href="/facts/CLMUL_instruction_set/UzzxBF65">PCLMULQDQ</a> (carry-less multiply) instruction</td><th>1</th></tr><tr><th>2</th><td>de</td><td>Debugging extensions (<a href="/facts/Control_register/9VGRHh3f">CR4</a> bit 3)</td><td>dtes64</td><td>64-bit debug store (edx bit 21)</td><th>2</th></tr><tr><th>3</th><td>pse</td><td><a href="/facts/Page_Size_Extension/V35daBet">Page Size Extension</a> (4 MB pages)</td><td>monitor</td><td>MONITOR and MWAIT instructions (<a href="/facts/Prescott_New_Instructions/Ch9oP4oh">PNI</a>)</td><th>3</th></tr><tr><th>4</th><td>tsc</td><td><a href="/facts/Time_Stamp_Counter/THy8g17s">Time Stamp Counter</a> and RDTSC instruction</td><td>ds-cpl</td><td>CPL qualified debug store</td><th>4</th></tr><tr><th>5</th><td>msr</td><td><a href="/facts/Model-specific_register/uzoD3Ynm">Model-specific registers</a> and RDMSR/WRMSR instructions</td><td>vmx</td><td><a href="/facts/X86_virtualization/utQwmdY3">Virtual Machine eXtensions</a></td><th>5</th></tr><tr><th>6</th><td>pae</td><td><a href="/facts/Physical_Address_Extension/aEr4tj4x">Physical Address Extension</a></td><td>smx</td><td>Safer Mode Extensions (<a href="/facts/LaGrande/ELjv2uVt">LaGrande</a>) (GETSEC instruction)</td><th>6</th></tr><tr><th>7</th><td>mce</td><td><a href="/facts/Machine_Check_Exception/8aLxkI6W">Machine Check Exception</a></td><td>est</td><td>Enhanced <a href="/facts/SpeedStep/kbjhM3Wz">SpeedStep</a></td><th>7</th></tr><tr><th>8</th><td>cx8<a class="footnote-ref" id="fnref:57" href="#fn:57"><sup>57</sup></a></td><td>CMPXCHG8B (<a href="/facts/Compare-and-swap/7mJkkycd">compare-and-swap</a>) instruction</td><td>tm2</td><td><a href="/facts/Thermal_Monitor_2/t3XA8KBB">Thermal Monitor 2</a></td><th>8</th></tr><tr><th>9</th><td>apic<a class="footnote-ref" id="fnref:58" href="#fn:58"><sup>58</sup></a></td><td>Onboard <a href="/facts/Advanced_Programmable_Interrupt_Controller/40lXS8r6">Advanced Programmable Interrupt Controller</a></td><td>ssse3</td><td><a href="/facts/SSSE3/xlRTcz4I">Supplemental SSE3</a> instructions</td><th>9</th></tr><tr><th>10</th><td>(mtrr)<a class="footnote-ref" id="fnref:59" href="#fn:59"><sup>59</sup></a></td><td><i>(reserved)</i></td><td>cnxt-id</td><td>L1 Context ID</td><th>10</th></tr><tr><th>11</th><td>sep<a class="footnote-ref" id="fnref:60" href="#fn:60"><sup>60</sup></a></td><td>SYSENTER and SYSEXIT fast system call instructions</td><td>sdbg</td><td>Silicon Debug interface</td><th>11</th></tr><tr><th>12</th><td>mtrr</td><td><a href="/facts/Memory_Type_Range_Registers/gMC50p6b">Memory Type Range Registers</a><a class="footnote-ref" id="fnref:61" href="#fn:61"><sup>61</sup></a></td><td>fma</td><td><a href="/facts/FMA_instruction_set/mqglSHqk">Fused multiply-add</a> (FMA3)</td><th>12</th></tr><tr><th>13</th><td>pge</td><td><a href="/facts/Page_table/0IBU5cwg">Page</a> Global Enable bit in <a href="/facts/Control_register/9VGRHh3f">CR4</a></td><td>cx16</td><td>CMPXCHG16B instruction<a class="footnote-ref" id="fnref:62" href="#fn:62"><sup>62</sup></a></td><th>13</th></tr><tr><th>14</th><td>mca</td><td><a href="/facts/Machine_check_architecture/zLk8GyQW">Machine check architecture</a></td><td>xtpr</td><td>Can disable sending task priority messages</td><th>14</th></tr><tr><th>15</th><td>cmov</td><td>Conditional move: CMOV, <a href="/facts/FCMOV/2WgVBPK4">FCMOV</a> and FCOMI instructions<a class="footnote-ref" id="fnref:63" href="#fn:63"><sup>63</sup></a></td><td>pdcm</td><td>Perfmon & debug capability</td><th>15</th></tr><tr><th>16</th><td>pat</td><td><a href="/facts/Page_Attribute_Table/wY8u28fc">Page Attribute Table</a></td><td colspan="2"><i>(reserved)</i><a class="footnote-ref" id="fnref:64" href="#fn:64"><sup>64</sup></a></td><th>16</th></tr><tr><th>17</th><td>pse-36</td><td><a href="/facts/PSE-36/UG8myR82">36-bit page size extension</a></td><td>pcid</td><td><a href="/facts/Process_context_identifiers/vvwGkfvD">Process context identifiers</a> (<a href="/facts/Control_register/9VGRHh3f">CR4</a> bit 17)</td><th>17</th></tr><tr><th>18</th><td>psn</td><td><a href="/facts/Processor_Serial_Number/sV1v2Frq">Processor Serial Number</a> supported and enabled<a class="footnote-ref" id="fnref:65" href="#fn:65"><sup>65</sup></a></td><td>dca</td><td>Direct cache access for DMA writes<a class="footnote-ref" id="fnref:66" href="#fn:66"><sup>66</sup></a><a class="footnote-ref" id="fnref:67" href="#fn:67"><sup>67</sup></a></td><th>18</th></tr><tr><th>19</th><td>clfsh</td><td>CLFLUSH cache line flush instruction (<a href="/facts/SSE2/cheNDPSK">SSE2</a>)</td><td>sse4.1</td><td><a href="/facts/SSE4.1/Tnxrl7Ph">SSE4.1</a> instructions</td><th>19</th></tr><tr><th>20</th><td>(nx)</td><td><a href="/facts/NX_bit/MnBB93BK">No-execute (NX) bit</a> (<a href="/facts/Itanium/0wkjSDpe">Itanium</a> only, reserved on other CPUs)<a class="footnote-ref" id="fnref:68" href="#fn:68"><sup>68</sup></a><a class="footnote-ref" id="fnref:69" href="#fn:69"><sup>69</sup></a></td><td>sse4.2</td><td><a href="/facts/SSE4.2/Tnxrl7Ph">SSE4.2</a> instructions</td><th>20</th></tr><tr><th>21</th><td>ds</td><td>Debug store: save trace of executed jumps</td><td>x2apic</td><td><a href="/facts/X2APIC/40lXS8r6">x2APIC</a> (enhanced APIC)</td><th>21</th></tr><tr><th>22</th><td>acpi</td><td>Onboard thermal control MSRs for <a href="/facts/Advanced_Configuration_and_Power_Interface/GnLLzfyr">ACPI</a></td><td>movbe</td><td>MOVBE instruction (<a href="/facts/Big-endian/wbrQnyu3">big-endian</a>)</td><th>22</th></tr><tr><th>23</th><td>mmx</td><td><a href="/facts/MMX_(instruction_set)/8o3JJhns">MMX</a> instructions (64-bit SIMD)</td><td>popcnt</td><td><a href="/facts/Popcnt/dJIW7qg4">POPCNT</a> instruction</td><th>23</th></tr><tr><th>24</th><td>fxsr</td><td>FXSAVE, FXRSTOR instructions, <a href="/facts/Control_register/9VGRHh3f">CR4</a> bit 9</td><td>tsc-deadline</td><td>APIC implements one-shot operation using a TSC deadline value</td><th>24</th></tr><tr><th>25</th><td>sse</td><td><a href="/facts/Streaming_SIMD_Extensions/mMa6EFyB">Streaming SIMD Extensions</a> (SSE) instructions(aka "<a href="/facts/Katmai_(microprocessor)/sV1v2Frq">Katmai</a> New Instructions"; 128-bit SIMD)</td><td>aes-ni</td><td><a href="/facts/AES_instruction_set/NomFEB4w">AES instruction set</a></td><th>25</th></tr><tr><th>26</th><td>sse2</td><td><a href="/facts/SSE2/cheNDPSK">SSE2</a> instructions</td><td>xsave</td><td>Extensible processor state save/restore:XSAVE, XRSTOR, XSETBV, XGETBV instructions</td><th>26</th></tr><tr><th>27</th><td>ss</td><td>CPU cache implements self-<a href="/facts/Cache_snooping/NUxKS0mb">snoop</a></td><td>osxsave</td><td>XSAVE enabled by OS</td><th>27</th></tr><tr><th>28</th><td>htt</td><td>Max APIC IDs reserved field is Valid<a class="footnote-ref" id="fnref:70" href="#fn:70"><sup>70</sup></a></td><td>avx</td><td><a href="/facts/Advanced_Vector_Extensions/znDpc6Vt">Advanced Vector Extensions</a> (256-bit SIMD)</td><th>28</th></tr><tr><th>29</th><td>tm</td><td>Thermal monitor automatically limits temperature</td><td>f16c</td><td>Floating-point conversion instructions to/from <a href="/facts/FP16/7xPj7B3w">FP16</a> format</td><th>29</th></tr><tr><th>30</th><td>ia64</td><td><a href="/facts/IA64/m6egpGno">IA64</a> processor emulating x86<a class="footnote-ref" id="fnref:71" href="#fn:71"><sup>71</sup></a></td><td>rdrnd</td><td><a href="/facts/RDRAND/IdeN4y36">RDRAND</a> (on-chip random number generator) feature</td><th>30</th></tr><tr><th>31</th><td>pbe</td><td>Pending Break Enable (PBE# pin) wakeup capability</td><td>hypervisor</td><td><a href="/facts/Hypervisor/3gX9fKlH">Hypervisor</a> present (always zero on physical CPUs)<a class="footnote-ref" id="fnref:72" href="#fn:72"><sup>72</sup></a><a class="footnote-ref" id="fnref:73" href="#fn:73"><sup>73</sup></a><a class="footnote-ref" id="fnref:74" href="#fn:74"><sup>74</sup></a></td><th>31</th></tr></tbody></table> <p>Reserved fields should be masked before using them for processor identification purposes. </p> <h2 id="eax2-cache-and-tlb-descriptor-information">EAX=2: Cache and TLB Descriptor Information</h2> <p>This returns a list of descriptors indicating cache and <a href="/facts/Translation_Lookaside_Buffer/vvwGkfvD">TLB</a> capabilities in EAX, EBX, ECX and EDX registers. </p><p>On processors that support this leaf, calling CPUID with EAX=2 will cause the bottom byte of EAX to be set to 01h<a class="footnote-ref" id="fnref:75" href="#fn:75"><sup>75</sup></a> and the remaining 15 bytes of EAX/EBX/ECX/EDX to be filled with 15 descriptors, one byte each. These descriptors provide information about the processor's caches, TLBs and prefetch. This is typically one cache or TLB per descriptor, but some descriptor-values provide other information as well - in particular, 00h is used for an empty descriptor, FFh indicates that the leaf does not contain valid cache information and that leaf 4h should be used instead, and FEh indicates that the leaf does not contain valid TLB information and that leaf 18h should be used instead. The descriptors may appear in any order. </p><p>For each of the four registers (EAX,EBX,ECX,EDX), if bit 31 is set, then the register should not be considered to contain valid descriptors (e.g. on Itanium in IA-32 mode, CPUID(EAX=2) returns 80000000h in EDX - this should be interpreted to mean that EDX contains no valid information, not that it contains a descriptor for a 512K L2 cache.) </p> <p>The table below provides, for known descriptor values, a condensed description of the cache or TLB indicated by that descriptor value (or other information, where that applies). The suffixes used in the table are: </p> <ul><li>K,M,G : binary kilobyte, megabyte, gigabyte (capacity for caches, page-size for TLBs)</li> <li>E : entries (for TLBs; e.g. 64E = 64 entries)</li> <li>p : page-size (e.g. 4Kp for TLBs where each entry describes one 4 KB <a href="/facts/Page_(computer_memory)/CNGruG1H">page</a>, 4K/2Mp for TLBs where each entry can describe either one 4 KB page or one 2 MB hugepage)</li> <li>L : cache-line size (e.g. 32L = 32-byte cache line size)</li> <li>S : cache sector size (e.g. 2S means that the cache uses sectors of 2 cache-lines each)</li> <li>A : associativity (e.g. 6A = 6-way <a href="/facts/Cache_placement_policies/MuBjrreM">set-associative</a>, FA = fully-associative)</li></ul> Legend for cache/TLB descriptor byte encodings<table><tbody><tr><td rowspan="1">Level-1instructionor data cache</td><td rowspan="1">Level-2cache</td><td rowspan="1">Level-3cache</td><td rowspan="1">Instructionor data TLB</td><td rowspan="1">Level-2sharedTLB</td><td>Otherinformation</td><td>(reserved)</td></tr></tbody></table> CPUID EAX=2: Cache/TLB descriptor byte encodings<table><tbody><tr><th></th><th>x0</th><th>x1</th><th>x2</th><th>x3</th><th>x4</th><th>x5</th><th>x6</th><th>x7</th><th></th><th>x8</th><th>x9</th><th>xA</th><th>xB</th><th>xC</th><th>xD</th><th>xE</th><th>xF</th><th></th></tr><tr><th>0x</th><td>nulldescriptor</td><td rowspan="1">ITLB: 32E,4Kp, 4A</td><td rowspan="1">ITLB: 2E,4Mp, FA</td><td rowspan="1">DTLB: 64E,4Kp, 4A</td><td rowspan="1">DTLB: 8E,4Mp, 4A</td><td rowspan="1">DTLB: 32E,4Mp, 4A</td><td rowspan="1">L1I: 8K,4A, 32L</td><td></td><th>0x</th><td rowspan="1">L1I: 16K,4A, 32L</td><td rowspan="1">L1I: 32K,4A, 64L</td><td rowspan="1">L1D: 8K,2A, 32L</td><td rowspan="1">ITLB: 4E,4Mp, FA</td><td rowspan="1">L1D: 16K,4A, 32L</td><td rowspan="1">L1D: 16K,4A, 64L<a class="footnote-ref" id="fnref:76" href="#fn:76"><sup>76</sup></a></td><td rowspan="1">L1D: 24K,6A, 64L<a class="footnote-ref" id="fnref:77" href="#fn:77"><sup>77</sup></a></td><td></td><th>0x</th></tr><tr><th>1x</th><td rowspan="1">(L1D: 16K,4A, 32L)<a class="footnote-ref" id="fnref:78" href="#fn:78"><sup>78</sup></a></td><td></td><td></td><td></td><td></td><td rowspan="1">(L1I: 16K,4A, 32L)<a class="footnote-ref" id="fnref:79" href="#fn:79"><sup>79</sup></a></td><td></td><td></td><th>1x</th><td></td><td></td><td rowspan="1">(L2C: 96K,6A, 64L)<a class="footnote-ref" id="fnref:80" href="#fn:80"><sup>80</sup></a></td><td></td><td></td><td rowspan="1">L2C: 128K,2A, 64L</td><td></td><td></td><th>1x</th></tr><tr><th>2x</th><td></td><td rowspan="1">L2C: 256K,8A, 64L<a class="footnote-ref" id="fnref:81" href="#fn:81"><sup>81</sup></a></td><td rowspan="1">L3C: 512K,4A, 64L, 2S</td><td rowspan="1">L3C: 1M,8A, 64L, 2S</td><td rowspan="1">L2C: 1M,16A, 64L</td><td rowspan="1">L3C: 2M,8A, 64L, 2S</td><td>(128-byteprefetch)<a class="footnote-ref" id="fnref:82" href="#fn:82"><sup>82</sup></a></td><td>(128-byteprefetch)<a class="footnote-ref" id="fnref:83" href="#fn:83"><sup>83</sup></a></td><th>2x</th><td>(128-byteprefetch)<a class="footnote-ref" id="fnref:84" href="#fn:84"><sup>84</sup></a></td><td rowspan="1">L3C: 4M,8A, 64L, 2S</td><td></td><td></td><td rowspan="1">L1D: 32K,8A, 64L</td><td></td><td></td><td></td><th>2x</th></tr><tr><th>3x</th><td rowspan="1">L1I: 32K,8A, 64L</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><th>3x</th><td></td><td rowspan="1">L2C: 128K,4A, 64L, 2S<a class="footnote-ref" id="fnref:85" href="#fn:85"><sup>85</sup></a></td><td rowspan="1">L2C: 192K,6A, 64L, 2S<a class="footnote-ref" id="fnref:86" href="#fn:86"><sup>86</sup></a></td><td rowspan="1">L2C: 128K,2A, 64L, 2S<a class="footnote-ref" id="fnref:87" href="#fn:87"><sup>87</sup></a></td><td rowspan="1">L2C: 256K,4A, 64L, 2S<a class="footnote-ref" id="fnref:88" href="#fn:88"><sup>88</sup></a></td><td rowspan="1">L2C: 384K,6A, 64L, 2S<a class="footnote-ref" id="fnref:89" href="#fn:89"><sup>89</sup></a></td><td rowspan="1">L2C: 512K,4A, 64L, 2S<a class="footnote-ref" id="fnref:90" href="#fn:90"><sup>90</sup></a></td><td rowspan="1">L2C: 256K,2A, 64L<a class="footnote-ref" id="fnref:91" href="#fn:91"><sup>91</sup></a></td><th>3x</th></tr><tr><th>4x</th><td>no L3 cachepresent</td><td rowspan="1">L2C: 128K,4A, 32L</td><td rowspan="1">L2C: 256K,4A, 32L<a class="footnote-ref" id="fnref:92" href="#fn:92"><sup>92</sup></a></td><td rowspan="1">L2C: 512K,4A, 32L</td><td rowspan="1">L2C: 1M,4A, 32L</td><td rowspan="1">L2C: 2M,4A, 32L</td><td rowspan="1">L3C: 4M,4A, 64L</td><td rowspan="1">L3C: 8M,8A, 64L</td><th>4x</th><td rowspan="1">L2C: 3M,12A, 64L</td><td>L2C/L3C:<a class="footnote-ref" id="fnref:93" href="#fn:93"><sup>93</sup></a>4M, 16A, 64L</td><td rowspan="1">L3C: 6M,12A, 64L</td><td rowspan="1">L3C: 8M,16A, 64L</td><td rowspan="1">L3C: 12M,12A, 64L</td><td rowspan="1">L3C: 16M,16A, 64L</td><td rowspan="1">L2C: 6M,24A, 64L</td><td rowspan="1">ITLB: 32E,4Kp<a class="footnote-ref" id="fnref:94" href="#fn:94"><sup>94</sup></a></td><th>4x</th></tr><tr><th>5x</th><td rowspan="1">ITLB: 64E,FA,4K/2M/4Mp</td><td rowspan="1">ITLB: 128E,FA,4K/2M/4Mp</td><td rowspan="1">ITLB: 256E,FA,4K/2M/4Mp</td><td></td><td></td><td rowspan="1">ITLB: 7E,2M/4Mp, FA</td><td rowspan="1">DTLB: 16E,4Mp, 4A</td><td rowspan="1">DTLB: 16E,4Kp, 4A</td><th>5x</th><td></td><td rowspan="1">DTLB: 16E,4Kp, FA</td><td rowspan="1">DTLB: 32E,2M/4Mp, 4A</td><td rowspan="1">DTLB: 64E4K/4Mp, FA</td><td rowspan="1">DTLB: 128E,4K/4Mp, FA</td><td rowspan="1">DTLB: 256E,4K/4Mp, FA</td><td></td><td></td><th>5x</th></tr><tr><th>6x</th><td rowspan="1">L1D: 16K,8A, 64L</td><td rowspan="1">ITLB: 48E,4Kp, FA</td><td></td><td rowspan="1">Two DTLBs:32E, 2M/4Mp, 4A+ 4E, 1Gp, FA</td><td rowspan="1">DTLB: 512E,4Kp, 4A</td><td></td><td rowspan="1">L1D: 8K,4A, 64L</td><td rowspan="1">L1D: 16K,4A, 64L</td><th>6x</th><td rowspan="1">L1D: 32K,4A, 64L</td><td></td><td rowspan="1">DTLB: 64E,4Kp, 8A</td><td rowspan="1">DTLB: 256E,4Kp, 8A</td><td rowspan="1">DTLB: 128E,2M/4Mp, 8A</td><td rowspan="1">DTLB: 16E,1Gp, FA</td><td></td><td></td><th>6x</th></tr><tr><th>7x</th><td rowspan="1"><a href="/facts/Trace_cache/U5XtXmwq">Trace cache</a>,12K-μop, 8A<a class="footnote-ref" id="fnref:95" href="#fn:95"><sup>95</sup></a></td><td rowspan="1">Trace cache,16K-μop, 8A</td><td rowspan="1">Trace cache,32K-μop, 8A</td><td rowspan="1">Trace cache,64K-μop, 8A<a class="footnote-ref" id="fnref:96" href="#fn:96"><sup>96</sup></a></td><td><a class="footnote-ref" id="fnref:97" href="#fn:97"><sup>97</sup></a></td><td></td><td rowspan="1">ITLB: 8E,2M/4Mp, FA<a class="footnote-ref" id="fnref:98" href="#fn:98"><sup>98</sup></a></td><td rowspan="1">(L1I: 16K,4A, 64L)<a class="footnote-ref" id="fnref:99" href="#fn:99"><sup>99</sup></a><a class="footnote-ref" id="fnref:100" href="#fn:100"><sup>100</sup></a></td><th>7x</th><td rowspan="1">L2C: 1M,4A, 64L</td><td rowspan="1">L2C: 128K,8A, 64L, 2S</td><td rowspan="1">L2C: 256K,8A, 64L, 2S</td><td rowspan="1">L2C: 512K,8A, 64L, 2S</td><td rowspan="1">L2C: 1M,8A, 64L, 2S</td><td rowspan="1">L2C: 2M,8A, 64L</td><td rowspan="1">(L2C: 256K,8A, 128L)<a class="footnote-ref" id="fnref:101" href="#fn:101"><sup>101</sup></a></td><td rowspan="1">L2C: 512K,2A, 64L</td><th>7x</th></tr><tr><th>8x</th><td rowspan="1">L2C: 512K,8A, 64L<a class="footnote-ref" id="fnref:102" href="#fn:102"><sup>102</sup></a></td><td rowspan="1">(L2C: 128K,8A, 32L)<a class="footnote-ref" id="fnref:103" href="#fn:103"><sup>103</sup></a></td><td rowspan="1">L2C: 256K,8A, 32L<a class="footnote-ref" id="fnref:104" href="#fn:104"><sup>104</sup></a></td><td rowspan="1">L2C: 512K,8A, 32L</td><td rowspan="1">L2C: 1M,8A, 32L</td><td rowspan="1">L2C: 2M,8A, 32L</td><td rowspan="1">L2C: 512K,4A, 64L</td><td rowspan="1">L2C: 1M,8A, 64L</td><th>8x</th><td rowspan="1">(L3C: 2M,4A, 64L)<a class="footnote-ref" id="fnref:105" href="#fn:105"><sup>105</sup></a></td><td rowspan="1">(L3C: 4M,4A, 64L)<a class="footnote-ref" id="fnref:106" href="#fn:106"><sup>106</sup></a></td><td rowspan="1">(L3C: 8M,4A, 64L)<a class="footnote-ref" id="fnref:107" href="#fn:107"><sup>107</sup></a></td><td></td><td></td><td rowspan="1">(L3C: 3M,12A, 128L)<a class="footnote-ref" id="fnref:108" href="#fn:108"><sup>108</sup></a><a class="footnote-ref" id="fnref:109" href="#fn:109"><sup>109</sup></a></td><td></td><td></td><th>8x</th></tr><tr><th>9x</th><td rowspan="1">(ITLB: 64E,FA,4K-256Mp)<a class="footnote-ref" id="fnref:110" href="#fn:110"><sup>110</sup></a></td><td></td><td></td><td></td><td></td><td></td><td rowspan="1">(DTLB: 32E,FA,4K-256Mp)<a class="footnote-ref" id="fnref:111" href="#fn:111"><sup>111</sup></a></td><td></td><th>9x</th><td></td><td></td><td></td><td rowspan="1">(DTLB: 96E,FA,4K-256Mp)<a class="footnote-ref" id="fnref:112" href="#fn:112"><sup>112</sup></a></td><td></td><td></td><td></td><td></td><th>9x</th></tr><tr><th>Ax</th><td rowspan="1">DTLB: 32E,4Kp, FA</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><th>Ax</th><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><th>Ax</th></tr><tr><th>Bx</th><td rowspan="1">ITLB: 128E,4Kp, 4A</td><td rowspan="1">ITLB: 8E,2M/4Mp, 4A<a class="footnote-ref" id="fnref:113" href="#fn:113"><sup>113</sup></a></td><td rowspan="1">ITLB: 64E,4Kp, 4A</td><td rowspan="1">DTLB: 128E,4Kp, 4A</td><td rowspan="1">DTLB: 256E,4Kp, 4A</td><td rowspan="1">ITLB: 64E,4Kp, 8A</td><td rowspan="1">ITLB: 128E,4Kp, 8A</td><td></td><th>Bx</th><td></td><td></td><td rowspan="1">DTLB: 64E,4Kp, 4A</td><td></td><td></td><td></td><td></td><td></td><th>Bx</th></tr><tr><th>Cx</th><td rowspan="1">DTLB: 8E,4K/4Mp, 4A</td><td rowspan="1">L2TLB: 1024E,4K/2Mp, 8A</td><td rowspan="1">DTLB: 16E,2M/4Mp, 4A<a class="footnote-ref" id="fnref:114" href="#fn:114"><sup>114</sup></a></td><td rowspan="1">Two L2 STLBs:1536E, 4K/2Mp, 6A<a class="footnote-ref" id="fnref:115" href="#fn:115"><sup>115</sup></a>+ 16E, 1Gp, 4A</td><td rowspan="1">DTLB: 32E,2M/4Mp, 4A</td><td></td><td></td><td></td><th>Cx</th><td></td><td></td><td rowspan="1">L2TLB: 512E,4Kp, 4A</td><td></td><td></td><td></td><td></td><td></td><th>Cx</th></tr><tr><th>Dx</th><td rowspan="1">L3C: 512K,4A, 64L</td><td rowspan="1">L3C: 1M,4A, 64L</td><td rowspan="1">L3C: 2M,4A, 64L</td><td></td><td></td><td></td><td rowspan="1">L3C: 1M,8A, 64L</td><td rowspan="1">L3C: 2M,8A, 64L</td><th>Dx</th><td rowspan="1">L3C: 4M,8A, 64L</td><td></td><td></td><td></td><td rowspan="1">L3C: 1.5M,12A, 64L</td><td rowspan="1">L3C: 3M,12A, 64L</td><td rowspan="1">L3C: 6M,12A, 64L</td><td></td><th>Dx</th></tr><tr><th>Ex</th><td></td><td></td><td rowspan="1">L3C: 2M,16A, 64L</td><td rowspan="1">L3C: 4M,16A, 64L</td><td rowspan="1">L3C: 8M,16A, 64L</td><td></td><td></td><td></td><th>Ex</th><td></td><td></td><td rowspan="1">L3C: 12M,24A, 64L</td><td rowspan="1">L3C: 18M,24A, 64L<a class="footnote-ref" id="fnref:116" href="#fn:116"><sup>116</sup></a></td><td rowspan="1">L3C: 24M,24A, 64L</td><td></td><td></td><td></td><th>Ex</th></tr><tr><th>Fx</th><td>64-byteprefetch<a class="footnote-ref" id="fnref:117" href="#fn:117"><sup>117</sup></a></td><td>128-byteprefetch<a class="footnote-ref" id="fnref:118" href="#fn:118"><sup>118</sup></a></td><td></td><td></td><td></td><td></td><td></td><td></td><th>Fx</th><td></td><td></td><td></td><td></td><td></td><td></td><td>Leaf 2 hasno TLB info,use leaf 18h</td><td>Leaf 2 hasno cache info,use leaf 4</td><th>Fx</th></tr><tr><th></th><th>x0</th><th>x1</th><th>x2</th><th>x3</th><th>x4</th><th>x5</th><th>x6</th><th>x7</th><th></th><th>x8</th><th>x9</th><th>xA</th><th>xB</th><th>xC</th><th>xD</th><th>xE</th><th>xF</th><th></th></tr></tbody></table> <h2 id="eax3-processor-serial-number">EAX=3: Processor Serial Number</h2> <p class="note">See also: <a href="/facts/Pentium_III/sV1v2Frq">Pentium III § Controversy about privacy issues</a></p> <p>This returns the processor's serial number. The processor serial number was introduced on Intel <a href="/facts/Pentium_III/sV1v2Frq">Pentium III</a>, but due to privacy concerns, this feature is no longer implemented on later models (the PSN feature bit is always cleared). <a href="/facts/Transmeta/RmnrADmX">Transmeta's</a> Efficeon and Crusoe processors also provide this feature. AMD CPUs however, do not implement this feature in any CPU models. </p><p>For Intel Pentium III CPUs, the serial number is returned in the EDX:ECX registers. For Transmeta Efficeon CPUs, it is returned in the EBX:EAX registers. And for Transmeta Crusoe CPUs, it is returned in the EBX register only. </p><p>Note that the processor serial number feature must be enabled in the <a href="/facts/BIOS/2RY3dzQe">BIOS</a> setting in order to function. </p> <h2 id="eax4-and-eax8000001dh-cache-hierarchy-and-topology">EAX=4 and EAX=8000'001Dh: Cache Hierarchy and Topology</h2> <p>These two leaves are used to provide information about the <a href="/facts/Cache_hierarchy/9lGPQ5r6">cache hierarchy</a> levels available to the processor core on which the CPUID instruction is run. Leaf 4 is used on Intel processors and leaf 8000'001Dh is used on AMD processors - they both return data in EAX, EBX, ECX and EDX, using the same data format except that leaf 4 returns a few additional fields that are considered "reserved" for leaf 8000'001Dh. They both provide CPU cache information in a series of sub-leaves selected by ECX - to get information about all the cache levels, it is necessary to invoke CPUID repeatedly, with EAX=4 or 8000'001Dh and ECX set to increasing values starting from 0 (0,1,2,...) until a sub-leaf not describing any caches (EAX[4:0]=0) is found. The sub-leaves that do return cache information may appear in any order, but all of them will appear before the first sub-leaf not describing any caches. </p><p>In the below table, fields that are defined for leaf 4 but not for leaf 8000'001Dh are highlighted with yellow cell coloring and a (#4) item. </p> CPUID EAX=4 and 8000'001Dh: Cache property information in EAX, EBX and EDX<table><tbody><tr><th>Bit</th><th>EAX</th><th scope="col" rowspan="15"></th><th>EBX</th><th scope="col" rowspan="15"></th><th>EDX<a class="footnote-ref" id="fnref:119" href="#fn:119"><sup>119</sup></a></th><th>Bit</th></tr><tr><th>0</th><td rowspan="5">Cache Type:<ul><li>0: (No more caches)</li><li>1: Data Cache</li><li>2: Instruction Cache</li><li>3: Unified Cache</li><li>4-31: (reserved)</li></ul></td><td rowspan="10">System <a href="/facts/False_sharing/wwUJqNqT">coherency line size</a> in bytes, minus 1</td><td>WBINVD cache invalidation execution scope.A value of 0 indicates that the INVD/WBINVD instructions will invalidate all lower-levels caches of this cache, including caches that belong to sibling processors sharing this cache. A value of 1 indicates that lower-level caches of sibling processors that are sharing this cache are not guaranteed to be all cleared.</td><th>0</th></tr><tr><th>1</th><td>Cache inclusiveness. If 1, then cache is inclusive of lower-level caches.</td><th>1</th></tr><tr><th>2</th><td>Complex cache indexing. If 1, then cache uses a complex function for cache indexing, else the cache is direct-mapped. (#4)</td><th>2</th></tr><tr><th>3</th><td><i>(reserved)</i></td><th>3</th></tr><tr><th>4</th><td><i>(reserved)</i></td><th>4</th></tr><tr><th>7:5</th><td>Cache Level (starting from 1)</td><td><i>(reserved)</i></td><th>7:5</th></tr><tr><th>8</th><td>Self initializing cache level (1=doesn't need software initialization after reset)</td><td><i>(reserved)</i></td><th>8</th></tr><tr><th>9</th><td>Fully Associative Cache</td><td><i>(reserved)</i></td><th>9</th></tr><tr><th>10</th><td>(WBINVD cache invalidation execution scope)<a class="footnote-ref" id="fnref:120" href="#fn:120"><sup>120</sup></a> (#4)</td><td><i>(reserved)</i></td><th>10</th></tr><tr><th>11</th><td>(Cache Inclusiveness)<a class="footnote-ref" id="fnref:121" href="#fn:121"><sup>121</sup></a> (#4)</td><td><i>(reserved)</i></td><th>11</th></tr><tr><th>13:12</th><td><i>(reserved)</i></td><td rowspan="2">Physical line partitions (number of cache lines that share a cache address tag), minus 1</td><td><i>(reserved)</i></td><th>13:12</th></tr><tr><th>21:14</th><td rowspan="2">Maximum number of addressable IDs for logical processors sharing this cache, minus 1</td><td><i>(reserved)</i></td><th>21:14</th></tr><tr><th>25:22</th><td rowspan="2">Ways of <a href="/facts/Cache_placement_policies/MuBjrreM">cache associativity</a>, minus 1</td><td><i>(reserved)</i></td><th>25:22</th></tr><tr><th>31:26</th><td>Maximum number of addressable IDs for processor cores in physical package, minus 1 (#4)</td><td><i>(reserved)</i></td><th>31:26</th></tr></tbody></table> <p>For any caches that are valid and not fully-associative, the value returned in ECX is the number of sets in the cache minus 1. (For fully-associative caches, ECX should be treated as if it return the value 0.) For any given cache described by a sub-leaf of CPUID leaf 4 or 8000'001Dh, the total cache size in bytes can be computed as: </p><p>CacheSize = (EBX[11:0]+1) * (EBX[21:12]+1) * (EBX[31:22]+1) * (ECX+1) </p><p>For example, on Intel <a href="/facts/Crystalwell/p87h2lSE">Crystalwell</a> CPUs, executing CPUID with EAX=4 and ECX=4 will cause the processor to return the following size information for its level-4 cache in EBX and ECX: EBX=03C0F03F and ECX=00001FFF - this should be taken to mean that this cache has a cache line size of 64 bytes (EBX[11:0]+1), has 16 cache lines per tag (EBX[21:12]+1), is 16-way set-associative (EBX[31:22]+1) with 8192 sets (ECX+1), for a total size of 64*16*16*8192=134217728 bytes, or 128 binary megabytes. </p> <h2 id="eax4-and-eaxbh-intel-threadcore-and-cache-topology">EAX=4 and EAX=Bh: Intel Thread/Core and Cache Topology</h2> <p>These two leaves are used for processor topology (thread, core, package) and cache hierarchy enumeration in Intel multi-core (and hyperthreaded) processors.<a class="footnote-ref" id="fnref:122" href="#fn:122"><sup>122</sup></a> As of 2013 AMD does not use these leaves but has alternate ways of doing the core enumeration.<a class="footnote-ref" id="fnref:123" href="#fn:123"><sup>123</sup></a> </p><p>Unlike most other CPUID leaves, leaf Bh will return different values in EDX depending on which logical processor the CPUID instruction runs; the value returned in EDX is actually the <a href="/facts/X2APIC/40lXS8r6">x2APIC</a> id of the logical processor. The x2APIC id space is not continuously mapped to logical processors, however; there can be gaps in the mapping, meaning that some intermediate x2APIC ids don't necessarily correspond to any logical processor. Additional information for mapping the x2APIC ids to cores is provided in the other registers. Although the leaf Bh has sub-leaves (selected by ECX as described further below), the value returned in EDX is only affected by the logical processor on which the instruction is running but not by the subleaf. </p><p>The processor(s) topology exposed by leaf Bh is a hierarchical one, but with the strange caveat that the order of (logical) levels in this hierarchy doesn't necessarily correspond to the order in the physical hierarchy (<a href="/facts/Simultaneous_multithreading/bk8ec9yn">SMT</a>/core/package). However, every logical level can be queried as an ECX subleaf (of the Bh leaf) for its correspondence to a "level type", which can be either SMT, core, or "invalid". The level id space starts at 0 and is continuous, meaning that if a level id is invalid, all higher level ids will also be invalid. The level type is returned in bits 15:08 of ECX, while the number of logical processors at the level queried is returned in EBX. Finally, the connection between these levels and x2APIC ids is returned in EAX[4:0] as the number of bits that the x2APIC id must be shifted in order to obtain a unique id at the next level. </p><p>As an example, a dual-core <a href="/facts/Westmere_(microarchitecture)/yB4HcYdY">Westmere</a> processor capable of <a href="/facts/Hyperthreading/hjqGgK8V">hyperthreading</a> (thus having two cores and four threads in total) could have x2APIC ids 0, 1, 4 and 5 for its four logical processors. Leaf Bh (=EAX), subleaf 0 (=ECX) of CPUID could for instance return 100h in ECX, meaning that level 0 describes the SMT (hyperthreading) layer, and return 2 in EBX because there are two logical processors (SMT units) per physical core. The value returned in EAX for this 0-subleaf should be 1 in this case, because shifting the aforementioned x2APIC ids to the right by one bit gives a unique core number (at the next level of the level id hierarchy) and erases the SMT id bit inside each core. A simpler way to interpret this information is that the last bit (bit number 0) of the x2APIC id identifies the SMT/hyperthreading unit inside each core in our example. Advancing to subleaf 1 (by making another call to CPUID with EAX=Bh and ECX=1) could for instance return 201h in ECX, meaning that this is a core-type level, and 4 in EBX because there are 4 logical processors in the package; EAX returned could be any value greater than 3, because it so happens that bit number 2 is used to identify the core in the x2APIC id. Note that bit number 1 of the x2APIC id is not used in this example. However, EAX returned at this level could well be 4 (and it happens to be so on a Clarkdale Core i3 5x0) because that also gives a unique id at the package level (=0 obviously) when shifting the x2APIC id by 4 bits. Finally, you may wonder what the EAX=4 leaf can tell us that we didn't find out already. In EAX[31:26] it returns the APIC mask bits <i>reserved</i> for a package; that would be 111b in our example because bits 0 to 2 are used for identifying logical processors inside this package, but bit 1 is also reserved although not used as part of the logical processor identification scheme. In other words, APIC ids 0 to 7 are reserved for the package, even though half of these values don't map to a logical processor. </p><p>The cache hierarchy of the processor is explored by looking at the sub-leaves of leaf 4. The APIC ids are also used in this hierarchy to convey information about how the different levels of cache are shared by the SMT units and cores. To continue our example, the L2 cache, which is shared by SMT units of the same core but not between physical cores on the Westmere is indicated by EAX[26:14] being set to 1, while the information that the L3 cache is shared by the whole package is indicated by setting those bits to (at least) 111b. The cache details, including cache type, size, and associativity are communicated via the other registers on leaf 4. </p><p>Beware that older versions of the Intel app note 485 contain some misleading information, particularly with respect to identifying and counting cores in a multi-core processor;<a class="footnote-ref" id="fnref:124" href="#fn:124"><sup>124</sup></a> errors from misinterpreting this information have even been incorporated in the Microsoft sample code for using CPUID, even for the 2013 edition of Visual Studio,<a class="footnote-ref" id="fnref:125" href="#fn:125"><sup>125</sup></a> and also in the sandpile.org page for CPUID,<a class="footnote-ref" id="fnref:126" href="#fn:126"><sup>126</sup></a> but the Intel code sample for identifying processor topology<a class="footnote-ref" id="fnref:127" href="#fn:127"><sup>127</sup></a> has the correct interpretation, and the current Intel Software Developer's Manual has a more clear language. The (open source) cross-platform production code<a class="footnote-ref" id="fnref:128" href="#fn:128"><sup>128</sup></a> from <a href="/facts/Wildfire_Games/P8lUpDVd">Wildfire Games</a> also implements the correct interpretation of the Intel documentation. </p><p>Topology detection examples involving older (pre-2010) Intel processors that lack x2APIC (thus don't implement the EAX=Bh leaf) are given in a 2010 Intel presentation.<a class="footnote-ref" id="fnref:129" href="#fn:129"><sup>129</sup></a> Beware that using that older detection method on 2010 and newer Intel processors may overestimate the number of cores and logical processors because the old detection method assumes there are no gaps in the APIC id space, and this assumption is violated by some newer processors (starting with the Core i3 5x0 series), but these newer processors also come with an x2APIC, so their topology can be correctly determined using the EAX=Bh leaf method. </p> <h2 id="eax5-monitormwait-features">EAX=5: MONITOR/MWAIT Features</h2> <p>This returns feature information related to the MONITOR and MWAIT instructions in the EAX, EBX, ECX and EDX registers. </p> CPUID EAX=5: MONITOR/MWAIT feature information in EAX, EBX, EDX<table><tbody><tr><th>Bit</th><th>EAX</th><th scope="col" rowspan="9"></th><th>EBX</th><th scope="col" rowspan="9"></th><th>EDX</th><th>Bit</th></tr><tr><th>3:0</th><td rowspan="4">Smallest monitor-line size in bytes</td><td rowspan="4">Largest monitor-line size in bytes</td><td>Number of C0<a class="footnote-ref" id="fnref:130" href="#fn:130"><sup>130</sup></a> sub-states supported for MWAIT</td><th>3:0</th></tr><tr><th>7:4</th><td>Number of C1 sub-states supported for MWAIT</td><th>7:4</th></tr><tr><th>11:8</th><td>Number of C2 sub-states supported for MWAIT</td><th>11:8</th></tr><tr><th>15:12</th><td>Number of C3 sub-states supported for MWAIT</td><th>15:12</th></tr><tr><th>19:16</th><td rowspan="4"><i>(reserved)</i></td><td rowspan="4"><i>(reserved)</i></td><td>Number of C4 sub-states supported for MWAIT</td><th>19:16</th></tr><tr><th>23:20</th><td>Number of C5 sub-states supported for MWAIT</td><th>23:20</th></tr><tr><th>27:24</th><td>Number of C6 sub-states supported for MWAIT</td><th>27:24</th></tr><tr><th>31:28</th><td>Number of C7 sub-states supported for MWAIT</td><th>31:28</th></tr></tbody></table> CPUID EAX=5: MONITOR/MWAIT extension enumeration in ECX<table><tbody><tr><th rowspan="2">Bit</th><th colspan="2">ECX</th></tr><tr><th>Short</th><th>Feature</th></tr><tr><th>0</th><td>EMX</td><td>Enumeration of MONITOR/MWAIT extensions in ECX and EDX supported</td></tr><tr><th>1</th><td>IBE</td><td>Supports treating interrupts as break-events for MWAIT even when interrupts are disabled</td></tr><tr><th>2</th><td colspan="2"><i>(reserved)</i></td></tr><tr><th>3</th><td>Monitorless_MWAIT</td><td>Allow MWAIT to be used for power management without setting up memory monitoring with MONITOR<a class="footnote-ref" id="fnref:131" href="#fn:131"><sup>131</sup></a></td></tr><tr><th>31:4 </th><td colspan="2"><i>(reserved)</i></td></tr></tbody></table> <h2 id="eax6-thermal-and-power-management">EAX=6: Thermal and Power Management</h2> <p>This returns feature bits in the EAX register and additional information in the EBX, ECX and EDX registers. </p> CPUID EAX=6: Thermal/power management feature bits in EAX<table><tbody><tr><th rowspan="2">Bit</th><th colspan="2">EAX</th></tr><tr><th>Short</th><th>Feature</th></tr><tr><th>0</th><td>DTS</td><td>Digital Thermal Sensor capability</td></tr><tr><th>1</th><td></td><td><a href="/facts/Intel_Turbo_Boost/W9I2PUcg">Intel Turbo Boost</a> Technology capability</td></tr><tr><th>2</th><td>ARAT<a class="footnote-ref" id="fnref:132" href="#fn:132"><sup>132</sup></a></td><td>Always Running <a href="/facts/Advanced_Programmable_Interrupt_Controller/40lXS8r6">APIC</a> Timer capability</td></tr><tr><th>3</th><td colspan="2"><i>(reserved)</i></td></tr><tr><th>4</th><td>PLN</td><td>Power Limit Notification capability</td></tr><tr><th>5</th><td>ECMD</td><td>Extended Clock Modulation Duty capability</td></tr><tr><th>6</th><td>PTM</td><td>Package Thermal Management capability</td></tr><tr><th>7</th><td>HWP</td><td>Hardware-controlled <a href="/facts/ACPI/GnLLzfyr">Performance States</a>. MSRs added:<ul><li>IA32_PM_ENABLE(770h)</li><li>IA32_HWP_CAPABILITIES(771h)</li><li>IA32_HWP_REQUEST(774h)</li><li>IA32_HWP_STATUS(777h</li></ul></td></tr><tr><th>8</th><td>HWP_Notification</td><td>HWP notification of dynamic guaranteed performance change - IA32_HWP_INTERRUPT(773h) MSR</td></tr><tr><th>9</th><td>HWP_Activity_Window</td><td>HWP Activity Window control - bits 41:32 of IA32_HWP_REQUEST MSR</td></tr><tr><th>10</th><td>HWP_Energy_Performance_Preference</td><td>HWP Energy/performance preference control - bits 31:24 of IA32_HWP_REQUEST MSR</td></tr><tr><th>11</th><td>HWP_Package_Level_Request</td><td>HWP Package-level control - IA32_HWP_REQUEST_PKG(772h) MSR</td></tr><tr><th>12</th><td colspan="2"><i>(reserved)</i></td></tr><tr><th>13</th><td>HDC</td><td>Hardware <a href="/facts/Duty_cycle/B2tbtXTh">Duty Cycling</a> supported. MSRs added:<ul><li>IA32_PKG_HDC_CTL (DB0h)</li><li>IA32_PM_CTL1 (DB1h)</li><li>IA32_THREAD_STALL (DB2h)</li></ul></td></tr><tr><th>14</th><td></td><td><a href="/facts/Intel_Turbo_Boost/W9I2PUcg">Intel Turbo Boost</a> Max Technology 3.0 available</td></tr><tr><th>15</th><td></td><td>Interrupts upon changes to IA32_HWP_CAPABILITIES.Highest_Performance (bits 7:0) supported</td></tr><tr><th>16</th><td></td><td>HWP <a href="/facts/Platform_Environment_Control_Interface/ghuc4fxP">PECI</a> override supported - bits 63:60 of IA32_HWP_PECI_REQUEST_INFO(775h) MSR</td></tr><tr><th>17</th><td></td><td>Flexible HWP - bits 63:59 of IA32_HWP_REQUEST MSR</td></tr><tr><th>18</th><td>Fast Access Mode</td><td>Fast access mode for IA32_HWP_REQUEST MSR supported<a class="footnote-ref" id="fnref:133" href="#fn:133"><sup>133</sup></a></td></tr><tr><th>19</th><td>HW_FEEDBACK</td><td>Hardware Feedback Interface. Added MSRs:<ul><li>IA32_HW_FEEDBACK_PTR(17D0h)</li><li>IA32_HW_FEEDBACK_CONFIG(17D1h) (bit 0 enables HFI, bit 1 enables Intel Thread Director)</li></ul></td></tr><tr><th>20</th><td></td><td>IA32_HWP_REQUEST of idle logical processor ignored when only one of two logical processors that <a href="/facts/Hyper-Threading/hjqGgK8V">share a physical processor</a> is active.</td></tr><tr><th>21</th><td colspan="2"><i>(reserved)</i></td></tr><tr><th>22</th><td>HWP Control MSR</td><td>IA32_HWP_CTL(776h) MSR supported<a class="footnote-ref" id="fnref:134" href="#fn:134"><sup>134</sup></a></td></tr><tr><th>23</th><td></td><td>Intel Thread Director supported. Added MSRs:<ul><li>IA32_THREAD_FEEDBACK_CHAR(17D2h)</li><li>IA32_HW_FEEDBACK_THREAD_CONFIG(17D4h)</li></ul></td></tr><tr><th>24</th><td></td><td>IA32_THERM_INTERRUPT MSR bit 25 supported</td></tr><tr><th>31:25 </th><td colspan="2"><i>(reserved)</i></td></tr></tbody></table> CPUID EAX=6: Thermal/power management feature fields in EBX, ECX and EDX<table><tbody><tr><th>Bit</th><th>EBX</th><th scope="col" rowspan="9"></th><th>ECX</th><th scope="col" rowspan="9"></th><th>EDX</th><th>Bit</th></tr><tr><th>0</th><td rowspan="4">Number of Interrupt Thresholds in Digital Thermal Sensor</td><td>Effective frequency interface supported - IA32_MPERF(0E7h) and IA32_APERF(0E8h) MSRs</td><td>Hardware Feedback reporting: Performance Capability Reporting supported</td><th>0</th></tr><tr><th>1</th><td>(ACNT2 Capability)<a class="footnote-ref" id="fnref:135" href="#fn:135"><sup>135</sup></a></td><td>Hardware Feedback reporting: Efficiency Capability Reporting supported</td><th>1</th></tr><tr><th>2</th><td><i>(reserved)</i></td><td rowspan="3"><i>(reserved)</i></td><th>2</th></tr><tr><th>3</th><td>Performance-Energy Bias capability - IA32_ENERGY_PERF_BIAS(1B0h) MSR</td><th>3</th></tr><tr><th>7:4</th><td rowspan="4"><i>(reserved)</i></td><td><i>(reserved)</i></td><th>7:4</th></tr><tr><th>11:8</th><td rowspan="2">Number of Intel Thread Director classes supported by hardware</td><td>Size of Hardware Feedback interface structure (in units of 4 KB) minus 1</td><th>11:8</th></tr><tr><th>15:12</th><td><i>(reserved)</i></td><th>15:12</th></tr><tr><th>31:16 </th><td><i>(reserved)</i></td><td>Index of this logical processor's row in hardware feedback interface structure</td><th>31:16 </th></tr></tbody></table> <h2 id="eax7-ecx0-extended-features">EAX=7, ECX=0: Extended Features</h2> <p>This returns extended feature flags in EBX, ECX, and EDX. Returns the maximum ECX value for EAX=7 in EAX. </p> CPUID EAX=7,ECX=0: Extended feature bits in EBX, ECX and EDX<table><tbody><tr><th rowspan="2">Bit</th><th colspan="2">EBX</th><th scope="col" rowspan="34"></th><th colspan="2">ECX</th><th scope="col" rowspan="34"></th><th colspan="2">EDX</th><th rowspan="2">Bit</th></tr><tr><th>Short</th><th>Feature</th><th>Short</th><th>Feature</th><th>Short</th><th>Feature</th></tr><tr><th>0</th><td>fsgsbase</td><td>Access to base of %fs and %gs</td><td>prefetchwt1</td><td>PREFETCHWT1 instruction</td><td>(sgx-tem)<a class="footnote-ref" id="fnref:136" href="#fn:136"><sup>136</sup></a></td><td>?</td><th>0</th></tr><tr><th>1</th><td></td><td>IA32_TSC_ADJUST MSR</td><td>avx512-vbmi</td><td><a href="/facts/AVX-512/2KpGqI8t">AVX-512</a> Vector Bit Manipulation Instructions</td><td>sgx-keys</td><td>Attestation Services for <a href="/facts/Software_Guard_Extensions/HcgbyB5P">Intel SGX</a></td><th>1</th></tr><tr><th>2</th><td>sgx</td><td><a href="/facts/Software_Guard_Extensions/HcgbyB5P">Software Guard Extensions</a></td><td>umip</td><td>User-mode Instruction Prevention</td><td>avx512-4vnniw</td><td><a href="/facts/AVX-512/2KpGqI8t">AVX-512</a> 4-register Neural Network Instructions</td><th>2</th></tr><tr><th>3</th><td>bmi1</td><td><a href="/facts/Bit_Manipulation_Instruction_Sets/LJAm1LWC">Bit Manipulation Instruction Set 1</a></td><td>pku</td><td>Memory Protection Keys for User-mode pages</td><td>avx512-4fmaps</td><td><a href="/facts/AVX-512/2KpGqI8t">AVX-512</a> 4-register Multiply Accumulation Single precision</td><th>3</th></tr><tr><th>4</th><td>hle</td><td><a href="/facts/Transactional_Synchronization_Extensions/j1CYdvFP">TSX</a> Hardware Lock Elision</td><td>ospke</td><td>PKU enabled by OS</td><td>fsrm</td><td>Fast Short REP MOVSB</td><th>4</th></tr><tr><th>5</th><td>avx2</td><td><a href="/facts/Advanced_Vector_Extensions_2/znDpc6Vt">Advanced Vector Extensions 2</a></td><td>waitpkg</td><td>Timed pause and user-level monitor/wait instructions (TPAUSE, UMONITOR, UMWAIT)</td><td>uintr</td><td>User Inter-processor Interrupts</td><th>5</th></tr><tr><th>6</th><td>fdp-excptn-only</td><td><a href="/facts/X87/y8X9HnLL">x87</a> FPU data pointer register updated on exceptions only</td><td>avx512-vbmi2</td><td><a href="/facts/AVX-512/2KpGqI8t">AVX-512</a> Vector Bit Manipulation Instructions 2</td><td colspan="2"><i>(reserved)</i></td><th>6</th></tr><tr><th>7</th><td>smep</td><td><a href="/facts/Supervisor_Mode_Execution_Prevention/9VGRHh3f">Supervisor Mode Execution Prevention</a></td><td>cet_ss/shstk</td><td>Control flow enforcement (CET): shadow stack (SHSTK alternative name)</td><td colspan="2"><i>(reserved)</i></td><th>7</th></tr><tr><th>8</th><td>bmi2</td><td><a href="/facts/Bit_Manipulation_Instruction_Sets/LJAm1LWC">Bit Manipulation Instruction Set 2</a></td><td>gfni</td><td>Galois Field instructions</td><td>avx512-vp2intersect</td><td><a href="/facts/AVX-512/2KpGqI8t">AVX-512</a> vector intersection instructions on 32/64-bit integers</td><th>8</th></tr><tr><th>9</th><td>erms</td><td>Enhanced REP MOVSB/STOSB</td><td>vaes</td><td>Vector <a href="/facts/AES_instruction_set/NomFEB4w">AES instruction set</a> (VEX-256/EVEX)</td><td>srbds-ctrl</td><td>Special Register Buffer Data Sampling Mitigations</td><th>9</th></tr><tr><th>10</th><td>invpcid</td><td>INVPCID instruction</td><td>vpclmulqdq</td><td><a href="/facts/CLMUL_instruction_set/UzzxBF65">CLMUL instruction set</a> (VEX-256/EVEX)</td><td>md-clear</td><td>VERW instruction clears CPU buffers</td><th>10</th></tr><tr><th>11</th><td>rtm</td><td><a href="/facts/Transactional_Synchronization_Extensions/j1CYdvFP">TSX</a> Restricted Transactional Memory</td><td>avx512-vnni</td><td><a href="/facts/AVX-512/2KpGqI8t">AVX-512</a> Vector Neural Network Instructions</td><td>rtm-always-abort<a class="footnote-ref" id="fnref:137" href="#fn:137"><sup>137</sup></a></td><td>All TSX transactions are aborted</td><th>11</th></tr><tr><th>12</th><td>rdt-m/pqm</td><td>Intel Resource Director (RDT) Monitoring <i>or</i> AMD Platform QOS Monitoring</td><td>avx512-bitalg</td><td><a href="/facts/AVX-512/2KpGqI8t">AVX-512</a> BITALG instructions</td><td colspan="2"><i>(reserved)</i></td><th>12</th></tr><tr><th>13</th><td></td><td><a href="/facts/X87/y8X9HnLL">x87</a> FPU CS and DS deprecated</td><td>tme_en</td><td>Total Memory Encryption MSRs available</td><td>rtm-force-abort<a class="footnote-ref" id="fnref:138" href="#fn:138"><sup>138</sup></a></td><td>TSX_FORCE_ABORT (MSR 0x10f) is available</td><th>13</th></tr><tr><th>14</th><td>mpx</td><td><a href="/facts/Intel_MPX/GI1a54M2">Intel MPX</a> (Memory Protection Extensions)</td><td>avx512-vpopcntdq</td><td>AVX-512 Vector Population Count Double and Quad-word</td><td>serialize</td><td>SERIALIZE instruction</td><th>14</th></tr><tr><th>15</th><td>rdt-a/pqe</td><td>Intel Resource Director (RDT) Allocation <i>or</i> AMD Platform QOS Enforcement</td><td>(fzm)<a class="footnote-ref" id="fnref:139" href="#fn:139"><sup>139</sup></a></td><td>?</td><td>hybrid</td><td>Mixture of CPU types in processor topology (e.g. <a href="/facts/Alder_Lake/q7rtppRT">Alder Lake</a>)</td><th>15</th></tr><tr><th>16</th><td>avx512-f</td><td><a href="/facts/AVX-512/2KpGqI8t">AVX-512</a> Foundation</td><td>la57</td><td><a href="/facts/Intel_5-level_paging/IX6Kk3Qw">5-level paging</a> (57 address bits)</td><td>tsxldtrk</td><td><a href="/facts/Transactional_Synchronization_Extensions/j1CYdvFP">TSX</a> load address tracking suspend/resume instructions (TSUSLDTRK and TRESLDTRK)</td><th>16</th></tr><tr><th>17</th><td>avx512-dq</td><td><a href="/facts/AVX-512/2KpGqI8t">AVX-512</a> Doubleword and Quadword Instructions</td><td rowspan="5">mawau</td><td rowspan="5">The value of userspace MPX Address-Width Adjust used by the BNDLDX and BNDSTX <a href="/facts/Intel_MPX/GI1a54M2">Intel MPX</a> instructions in 64-bit mode</td><td colspan="2"><i>(reserved)</i></td><th>17</th></tr><tr><th>18</th><td>rdseed</td><td><a href="/facts/RDSEED/IdeN4y36">RDSEED</a> instruction</td><td>pconfig</td><td>Platform configuration (Memory Encryption Technologies Instructions)</td><th>18</th></tr><tr><th>19</th><td>adx</td><td><a href="/facts/Intel_ADX/7I3KDzYA">Intel ADX</a> (Multi-Precision Add-Carry Instruction Extensions)</td><td>lbr</td><td>Architectural Last Branch Records</td><th>19</th></tr><tr><th>20</th><td>smap</td><td><a href="/facts/Supervisor_Mode_Access_Prevention/H8RSCNy2">Supervisor Mode Access Prevention</a></td><td>cet-ibt</td><td>Control flow enforcement (CET): indirect branch tracking</td><th>20</th></tr><tr><th>21</th><td>avx512-ifma</td><td><a href="/facts/AVX-512/2KpGqI8t">AVX-512</a> Integer Fused Multiply-Add Instructions</td><td colspan="2"><i>(reserved)</i></td><th>21</th></tr><tr><th>22</th><td>(pcommit)</td><td>(PCOMMIT instruction, deprecated)<a class="footnote-ref" id="fnref:140" href="#fn:140"><sup>140</sup></a></td><td>rdpid</td><td>RDPID (Read Processor ID) instruction and IA32_TSC_AUX MSR</td><td>amx-bf16</td><td><a href="/facts/Advanced_Matrix_Extensions/qkDBQbBE">AMX</a> tile computation on <a href="/facts/Bfloat16_floating-point_format/wo1Q6IJY">bfloat16</a> numbers</td><th>22</th></tr><tr><th>23</th><td>clflushopt</td><td>CLFLUSHOPT instruction</td><td>kl</td><td>AES Key Locker</td><td>avx512-fp16</td><td><a href="/facts/AVX-512/2KpGqI8t">AVX-512</a> <a href="/facts/FP16/7xPj7B3w">half-precision</a> floating-point arithmetic instructions<a class="footnote-ref" id="fnref:141" href="#fn:141"><sup>141</sup></a></td><th>23</th></tr><tr><th>24</th><td>clwb</td><td>CLWB (Cache line writeback) instruction</td><td>bus-lock-detect</td><td>Bus lock debug exceptions</td><td>amx-tile</td><td><a href="/facts/Advanced_Matrix_Extensions/qkDBQbBE">AMX</a> tile load/store instructions</td><th>24</th></tr><tr><th>25</th><td>pt</td><td>Intel Processor Trace</td><td>cldemote</td><td>CLDEMOTE (Cache line demote) instruction</td><td>amx-int8</td><td><a href="/facts/Advanced_Matrix_Extensions/qkDBQbBE">AMX</a> tile computation on 8-bit integers</td><th>25</th></tr><tr><th>26</th><td>avx512-pf</td><td><a href="/facts/AVX-512/2KpGqI8t">AVX-512</a> Prefetch Instructions</td><td>(mprr)<a class="footnote-ref" id="fnref:142" href="#fn:142"><sup>142</sup></a></td><td>?</td><td>ibrs / spec_ctrl</td><td>Speculation Control, part of Indirect Branch Control (IBC):Indirect Branch Restricted Speculation (IBRS) andIndirect Branch Prediction Barrier (IBPB)<a class="footnote-ref" id="fnref:143" href="#fn:143"><sup>143</sup></a><a class="footnote-ref" id="fnref:144" href="#fn:144"><sup>144</sup></a></td><th>26</th></tr><tr><th>27</th><td>avx512-er</td><td><a href="/facts/AVX-512/2KpGqI8t">AVX-512</a> Exponential and Reciprocal Instructions</td><td>movdiri</td><td>MOVDIRI instruction</td><td>stibp</td><td>Single Thread Indirect Branch Predictor, part of IBC<a class="footnote-ref" id="fnref:145" href="#fn:145"><sup>145</sup></a></td><th>27</th></tr><tr><th>28</th><td>avx512-cd</td><td><a href="/facts/AVX-512/2KpGqI8t">AVX-512</a> Conflict Detection Instructions</td><td>movdir64b</td><td>MOVDIR64B (64-byte direct store) instruction</td><td>L1D_FLUSH</td><td>IA32_FLUSH_CMD MSR</td><th>28</th></tr><tr><th>29</th><td>sha</td><td><a href="/facts/Intel_SHA_extensions/qDzy2N70">SHA-1 and SHA-256 extensions</a></td><td>enqcmd</td><td>Enqueue Stores and EMQCMD/EMQCMDS instructions</td><td></td><td>IA32_ARCH_CAPABILITIES MSR (lists speculative side channel mitigations<a class="footnote-ref" id="fnref:146" href="#fn:146"><sup>146</sup></a>)</td><th>29</th></tr><tr><th>30</th><td>avx512-bw</td><td><a href="/facts/AVX-512/2KpGqI8t">AVX-512</a> Byte and Word Instructions</td><td>sgx-lc</td><td><a href="/facts/Software_Guard_Extensions/HcgbyB5P">SGX</a> Launch Configuration</td><td></td><td>IA32_CORE_CAPABILITIES MSR (lists model-specific core capabilities)</td><th>30</th></tr><tr><th>31</th><td>avx512-vl</td><td><a href="/facts/AVX-512/2KpGqI8t">AVX-512</a> Vector Length Extensions</td><td>pks</td><td>Protection keys for supervisor-mode pages</td><td>ssbd</td><td>Speculative Store Bypass Disable,<a class="footnote-ref" id="fnref:147" href="#fn:147"><sup>147</sup></a> as mitigation for <a href="/facts/Speculative_Store_Bypass/foA66VXX">Speculative Store Bypass</a> (IA32_SPEC_CTRL)</td><th>31</th></tr></tbody></table> <h2 id="eax7-ecx1-extended-features">EAX=7, ECX=1: Extended Features</h2> <p>This returns extended feature flags in all four registers. </p> CPUID EAX=7,ECX=1: Extended feature bits in EAX, EBX, ECX, and EDX<table><tbody><tr><th rowspan="2">Bit</th><th colspan="2">EAX</th><th scope="col" rowspan="34"></th><th colspan="2">EBX</th><th scope="col" rowspan="34"></th><th colspan="2">ECX</th><th scope="col" rowspan="34"></th><th colspan="2">EDX</th><th rowspan="2">Bit</th></tr><tr><th>Short</th><th>Feature</th><th>Short</th><th>Feature</th><th>Short</th><th>Feature</th><th>Short</th><th>Feature</th></tr><tr><th>0</th><td>sha512</td><td><a href="/facts/Intel_SHA_extensions/qDzy2N70">SHA-512 extensions</a></td><td></td><td>Intel PPIN (Protected Processor Inventory Number): IA32_PPIN_CTL (04Eh) and IA32_PPIN (04Fh) MSRs.</td><td></td><td>Asymmetric RDT Monitoring capability</td><td colspan="2"><i>(reserved)</i></td><th>0</th></tr><tr><th>1</th><td>sm3</td><td><a href="/facts/SM3_(hash_function)/pdIyJ5jN">SM3 hash extensions</a></td><td>pbndkb</td><td>Total Storage Encryption: PBNDKB instruction and TSE_CAPABILITY (9F1h) MSR.</td><td></td><td>Asymmetric RDT Allocation capability</td><td colspan="2"><i>(reserved)</i></td><th>1</th></tr><tr><th>2</th><td>sm4</td><td><a href="/facts/SM4_(cipher)/05jCyaFf">SM4 cipher extensions</a></td><td colspan="2"><i>(reserved)</i></td><td>(legacy_reduced_isa)</td><td>(X86S,<a class="footnote-ref" id="fnref:148" href="#fn:148"><sup>148</sup></a> cancelled<a class="footnote-ref" id="fnref:149" href="#fn:149"><sup>149</sup></a>)</td><td colspan="2"><i>(reserved)</i></td><th>2</th></tr><tr><th>3</th><td>rao-int</td><td>Remote Atomic Operations on integers: AADD, AAND, AOR, AXOR instructions</td><td>CPUIDMAXVAL_LIM_RMV</td><td>If 1, then bit 22 of IA32_MISC_ENABLE cannot be set to 1 to limit the value returned by CPUID.(EAX=0):EAX[7:0].</td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>3</th></tr><tr><th>4</th><td>avx-vnni</td><td><a href="/facts/Advanced_Vector_Extensions/znDpc6Vt">AVX</a> Vector Neural Network Instructions (VNNI) (VEX encoded)</td><td colspan="2"><i>(reserved)</i></td><td>(sipi64)</td><td>64-bit SIPI (Startup InterProcessor Interrupt) (part of cancelled X86S)</td><td>avx-vnni-int8</td><td>AVX VNNI INT8 instructions</td><th>4</th></tr><tr><th>5</th><td>avx512-bf16</td><td><a href="/facts/AVX-512/2KpGqI8t">AVX-512</a> instructions for <a href="/facts/Bfloat16_floating-point_format/wo1Q6IJY">bfloat16</a> numbers</td><td colspan="2"><i>(reserved)</i></td><td>MSR_IMM</td><td>Immediate forms of the RDMSR and WRMSRNS instructions</td><td>avx-ne-convert</td><td>AVX no-exception FP conversion instructions (<a href="/facts/Bfloat16/wo1Q6IJY">bfloat16</a>↔FP32 and <a href="/facts/FP16/7xPj7B3w">FP16</a>→FP32)</td><th>5</th></tr><tr><th>6</th><td>lass</td><td>Linear Address Space Separation (CR4 bit 27)</td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>6</th></tr><tr><th>7</th><td>cmpccxadd</td><td>CMPccXADD instructions</td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>7</th></tr><tr><th>8</th><td>archperfmonext</td><td>Architectural Performance Monitoring Extended Leaf (EAX=23h)</td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td>amx-complex</td><td><a href="/facts/Advanced_Matrix_Extensions/qkDBQbBE">AMX</a> support for "complex" tiles (TCMMIMFP16PS and TCMMRLFP16PS)</td><th>8</th></tr><tr><th>9</th><td>(dedup)<a class="footnote-ref" id="fnref:150" href="#fn:150"><sup>150</sup></a></td><td>?</td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>9</th></tr><tr><th>10</th><td>fzrm</td><td>Fast zero-length REP MOVSB</td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td>avx-vnni-int16</td><td>AVX VNNI INT16 instructions</td><th>10</th></tr><tr><th>11</th><td>fsrs</td><td>Fast short REP STOSB</td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>11</th></tr><tr><th>12</th><td>rsrcs</td><td>Fast short REP CMPSB and REP SCASB</td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>12</th></tr><tr><th>13</th><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td>utmr</td><td>User-timer events: IA32_UINTR_TIMER (1B00h) MSR</td><th>13</th></tr><tr><th>14</th><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td>prefetchi</td><td>Instruction-cache prefetch instructions (PREFETCHIT0 and PREFETCHIT1)</td><th>14</th></tr><tr><th>15</th><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td>user_msr</td><td>User-mode MSR access instructions (URDMSR and UWRMSR)</td><th>15</th></tr><tr><th>16</th><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>16</th></tr><tr><th>17</th><td>fred</td><td>Flexible Return and Event Delivery<a class="footnote-ref" id="fnref:151" href="#fn:151"><sup>151</sup></a></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td>uiret-uif-from-rflags</td><td>If 1, the UIRET (User Interrupt Return) instruction will set UIF (User Interrupt Flag) to the value of bit 1 of the RFLAGS image popped off the stack.</td><th>17</th></tr><tr><th>18</th><td>lkgs</td><td>LKGS Instruction<a class="footnote-ref" id="fnref:152" href="#fn:152"><sup>152</sup></a></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td>cet-sss</td><td>If 1, then Control-Flow Enforcement (CET) Supervisor Shadow Stacks (SSS) are guaranteed not to become prematurely busy as long as shadow stack switching does not cause page faults on the stack being switched to.<a class="footnote-ref" id="fnref:153" href="#fn:153"><sup>153</sup></a><a class="footnote-ref" id="fnref:154" href="#fn:154"><sup>154</sup></a><a class="footnote-ref" id="fnref:155" href="#fn:155"><sup>155</sup></a></td><th>18</th></tr><tr><th>19</th><td>wrmsrns</td><td>WRMSRNS instruction (non-serializing write to <a href="/facts/Model-specific_register/uzoD3Ynm">MSRs</a>)</td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td>avx10</td><td>AVX10 Converged Vector ISA (see also leaf 24h)<a class="footnote-ref" id="fnref:156" href="#fn:156"><sup>156</sup></a></td><th>19</th></tr><tr><th>20</th><td>nmi_src</td><td><a href="/facts/Non-maskable_interrupt/f7CWJU1B">NMI</a> source reporting<a class="footnote-ref" id="fnref:157" href="#fn:157"><sup>157</sup></a></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>20</th></tr><tr><th>21</th><td>amx-fp16</td><td>AMX instructions for <a href="/facts/Half-precision_floating-point_format/7xPj7B3w">FP16</a> numbers</td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td>APX_F</td><td><a href="/facts/X86/Kypq5fgu">Advanced Performance Extensions</a>, Foundation (adds REX2 and extended <a href="/facts/EVEX_prefix/nakLJuCB">EVEX prefix</a> encodings to support 32 GPRs, as well as some new instructions)<a class="footnote-ref" id="fnref:158" href="#fn:158"><sup>158</sup></a></td><th>21</th></tr><tr><th>22</th><td>hreset</td><td>HRESET instruction, IA32_HRESET_ENABLE (17DAh) MSR, and Processor History Reset Leaf (EAX=20h)</td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>22</th></tr><tr><th>23</th><td>avx-ifma</td><td>AVX IFMA instructions</td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td>mwait</td><td>MWAIT instruction<a class="footnote-ref" id="fnref:159" href="#fn:159"><sup>159</sup></a></td><th>23</th></tr><tr><th>24</th><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>24</th></tr><tr><th>25</th><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>25</th></tr><tr><th>26</th><td>lam</td><td>Linear Address Masking</td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>26</th></tr><tr><th>27</th><td>msrlist</td><td>RDMSRLIST and WRMSRLIST instructions, and the IA32_BARRIER (02Fh) MSR</td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>27</th></tr><tr><th>28</th><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>28</th></tr><tr><th>29</th><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>29</th></tr><tr><th>30</th><td>invd_disable_post_bios_done</td><td>If 1, supports INVD instruction execution prevention after BIOS Done.</td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>30</th></tr><tr><th>31</th><td>MOVRS</td><td>MOVRS and PREFETCHRST2 instructions supported (memory read/prefetch with read-shared hint)</td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>31</th></tr></tbody></table> <h2 id="eax7-ecx2-extended-features">EAX=7, ECX=2: Extended Features</h2> <p>This returns extended feature flags in EDX. </p><p>EAX, EBX and ECX are reserved. </p> CPUID EAX=7,ECX=2: Extended feature bits in EDX<table><tbody><tr><th rowspan="2">Bit</th><th colspan="2">EDX</th></tr><tr><th>Short</th><th>Feature</th></tr><tr><th>0</th><td>psfd</td><td>Fast Store Forwarding Predictor<a class="footnote-ref" id="fnref:160" href="#fn:160"><sup>160</sup></a> disable supported. (SPEC_CTRL (MSR 48h) bit 7)</td></tr><tr><th>1</th><td>ipred_ctrl</td><td>IPRED_DIS controls<a class="footnote-ref" id="fnref:161" href="#fn:161"><sup>161</sup></a> supported. (SPEC_CTRL bits 3 and 4)<p>IPRED_DIS prevents instructions at an indirect branch target from speculatively executing until the branch target address is resolved.</p></td></tr><tr><th>2</th><td>rrsba_ctrl</td><td>RRSBA behavior<a class="footnote-ref" id="fnref:162" href="#fn:162"><sup>162</sup></a><a class="footnote-ref" id="fnref:163" href="#fn:163"><sup>163</sup></a> disable supported. (SPEC_CTRL bits 5 and 6)</td></tr><tr><th>3</th><td>ddpd_u</td><td>Data Dependent Prefetcher<a class="footnote-ref" id="fnref:164" href="#fn:164"><sup>164</sup></a> disable supported. (SPEC_CTRL bit 8)</td></tr><tr><th>4</th><td>bhi_ctrl</td><td>BHI_DIS_S behavior<a class="footnote-ref" id="fnref:165" href="#fn:165"><sup>165</sup></a> enable supported. (SPEC_CTRL bit 10)<p>BHI_DIS_S prevents predicted targets of indirect branches executed in ring0/1/2 from being selected based on branch history from branches executed in ring 3.</p></td></tr><tr><th>5</th><td>mcdt_no</td><td>If set, the processor does not exhibit <a href="/facts/Streaming_SIMD_Extensions/mMa6EFyB">MXCSR</a> configuration dependent timing.</td></tr><tr><th>6</th><td></td><td>UC-lock disable feature supported.</td></tr><tr><th>7</th><td>monitor_mitg_no</td><td>If set, indicates that the MONITOR/UMONITOR instructions are not affected by performance/power issues caused by the instructions exceeding the capacity of an internal monitor tracking table.<a class="footnote-ref" id="fnref:166" href="#fn:166"><sup>166</sup></a></td></tr><tr><th>31:8 </th><td colspan="2"><i>(reserved)</i></td></tr></tbody></table> <h2 id="eax0dh-xsave-features-and-state-components">EAX=0Dh: XSAVE Features and State Components</h2> <p>This leaf is used to enumerate XSAVE features and state components. </p><p>The XSAVE instruction set extension is designed to save/restore CPU extended state (typically for the purpose of <a href="/facts/Context_switch/N0oJQ6CC">context switching</a>) in a manner that can be extended to cover new instruction set extensions without the OS context-switching code needing to understand the specifics of the new extensions. This is done by defining a series of <i>state-components</i>, each with a size and offset within a given save area, and each corresponding to a subset of the state needed for one CPU extension or another. The EAX=0Dh CPUID leaf is used to provide information about which state-components the CPU supports and what their sizes/offsets are, so that the OS can reserve the proper amount of space and set the associated enable-bits. </p><p>The state-components can be subdivided into two groups: user-state (state-items that are visible to the application, e.g. <a href="/facts/AVX-512/2KpGqI8t">AVX-512</a> vector registers), and supervisor-state (state items that affect the application but are not directly user-visible, e.g. user-mode interrupt configuration). The user-state items are enabled by setting their associated bits in the XCR0 control register, while the supervisor-state items are enabled by setting their associated bits in the IA32_XSS (0DA0h) MSR - the indicated state items then become the state-components that can be saved and restored with the XSAVE/XRSTOR family of instructions. </p> <p>The XSAVE mechanism can handle up to 63 state-components in this manner. State-components 0 and 1 (<a href="/facts/X87/y8X9HnLL">x87</a> and <a href="/facts/Streaming_SIMD_Extensions/mMa6EFyB">SSE</a>, respectively) have fixed offsets and sizes - for state-components 2 to 62, their sizes, offsets and a few additional flags can be queried by executing CPUID with EAX=0Dh and ECX set to the index of the state-component. This will return the following items in EAX, EBX and ECX (with EDX being reserved): </p> CPUID EAX=0Dh, ECX≥2: XSAVE state-component information<table><tbody><tr><th>Bit</th><th>EAX</th><th>EBX</th><th>ECX</th><th>Bit</th></tr><tr><th>0</th><td rowspan="3">Size in bytes of state-component</td><td rowspan="3">Offset of state-component from the start of the XSAVE/XRSTOR save area<p>(This offset is 0 for supervisor state-components, since these can only be saved with the XSAVES/XRSTORS instruction, which use compacting.)</p></td><td>User/supervisor state-component:<ul><li>0=user-state (enabled through XCR0)</li><li>1=supervisor-state (enabled through IA32_XSS)</li></ul></td><th>0</th></tr><tr><th>1</th><td>64-byte alignment enable when state save compaction is used.<p>If this bit is set for a state-component, then, when storing state with compaction, padding will be inserted between the preceding state-component and this state-component as needed to provide 64-byte alignment. If this bit is not set, the state-component will be stored directly after the preceding one.</p></td><th>1</th></tr><tr><th>31:2 </th><td><i>(reserved)</i></td><th>31:2</th></tr></tbody></table> <p>Attempting to query an unsupported state-component in this manner results in EAX,EBX,ECX and EDX all being set to 0. </p><p>Sub-leaves 0 and 1 of CPUID leaf 0Dh are used to provide feature information: </p> CPUID EAX=0Dh,ECX=0: XSAVE features<table><tbody><tr><th>EBX</th><th>ECX</th><th>EDX:EAX</th></tr><tr><td>Maximum size (in bytes) of XSAVE save area for the set of state-components currently set in XCR0.</td><td>Maximum size (in bytes) of XSAVE save area if all state-components supported by XCR0 on this CPU were enabled at the same time.</td><td>64-bit bitmap of state-components supported by XCR0 on this CPU.</td></tr></tbody></table> CPUID EAX=0Dh,ECX=1: XSAVE extended features<table><tbody><tr><th>EAX</th><th>EBX</th><th>EDX:ECX</th></tr><tr><td>XSAVE feature flags (see below table)</td><td>Size (in bytes) of XSAVE area containing all the state-components currently set in XCR0 and IA32_XSS combined.</td><td>64-bit bitmap of state-components supported by IA32_XSS on this CPU.</td></tr></tbody></table> EAX=0Dh,ECX=1: XSAVE feature flags in EAX<table><tbody><tr><th rowspan="2">Bit</th><th colspan="2">EAX</th></tr><tr><th>Short</th><th>Feature</th></tr><tr><th>0</th><td>xsaveopt</td><td>XSAVEOPT instruction: save state-components that have been modified since last XRSTOR</td></tr><tr><th>1</th><td>xsavec</td><td>XSAVEC instruction: save/restore state with compaction</td></tr><tr><th>2</th><td>xgetbv_ecx1</td><td>XGETBV with ECX=1 support</td></tr><tr><th>3</th><td>xss</td><td>XSAVES and XRSTORS instructions and IA32_XSS MSR: save/restore state with compaction, including supervisor state.</td></tr><tr><th>4</th><td>xfd</td><td>XFD (Extended Feature Disable) supported</td></tr><tr><th>31:5 </th><td colspan="2"><i>(reserved)</i></td></tr></tbody></table> <p>As of July 2023, the XSAVE state-components that have been architecturally defined are: </p> XSAVE State-components<table><tbody><tr><th>Index</th><th>Description</th><th>Enabled with</th></tr><tr><th>0</th><td><a href="/facts/X87/y8X9HnLL">x87</a> state</td><td>XCR0<a class="footnote-ref" id="fnref:167" href="#fn:167"><sup>167</sup></a></td></tr><tr><th>1</th><td><a href="/facts/Streaming_SIMD_Extensions/mMa6EFyB">SSE</a> state: XMM0-XMM15 and MXCSR</td><td rowspan="7">XCR0</td></tr><tr><th>2</th><td><a href="/facts/Advanced_Vector_Extensions/znDpc6Vt">AVX</a> state: top halves of YMM0 to YMM15</td></tr><tr><th>3</th><td><a href="/facts/Intel_MPX/GI1a54M2">MPX</a> state: BND0-BND3 bounds registers</td></tr><tr><th>4</th><td>MPX state: BNDCFGU and BNDSTATUS registers</td></tr><tr><th>5</th><td><a href="/facts/AVX-512/2KpGqI8t">AVX-512</a> state: opmask registers k0-k7</td></tr><tr><th>6</th><td>AVX-512 "ZMM_Hi256" state: top halves of ZMM0 to ZMM15</td></tr><tr><th>7</th><td>AVX-512 "Hi16_ZMM" state: ZMM16-ZMM31</td></tr><tr><th>8</th><td>Processor Trace state</td><td>IA32_XSS</td></tr><tr><th>9</th><td>PKRU (User Protection Keys) register</td><td>XCR0</td></tr><tr><th>10</th><td>PASID (Process Address Space ID) state</td><td rowspan="7">IA32_XSS</td></tr><tr><th>11</th><td>CET_U state (Control-flow Enforcement Technology: user-mode functionality MSRs)</td></tr><tr><th>12</th><td>CET_S state (CET: shadow stack pointers for rings 0,1,2)</td></tr><tr><th>13</th><td>HDC (Hardware Duty Cycling) state</td></tr><tr><th>14</th><td>UINTR (User-Mode Interrupts) state</td></tr><tr><th>15</th><td>LBR (Last Branch Record) state</td></tr><tr><th>16</th><td>HWP (Hardware P-state control) state</td></tr><tr><th>17</th><td><a href="/facts/Advanced_Matrix_Extensions/qkDBQbBE">AMX</a> tile configuration state: TILECFG</td><td rowspan="3">XCR0</td></tr><tr><th>18</th><td>AMX tile data registers: tmm0-tmm7</td></tr><tr><th>19</th><td><a href="/facts/X86/Kypq5fgu">APX</a> extended general-purpose registers: r16-r31<a class="footnote-ref" id="fnref:168" href="#fn:168"><sup>168</sup></a></td></tr><tr><th>20 to 61 </th><td colspan="2"><i>(reserved)</i></td></tr><tr><th>62</th><td>Lightweight Profiling (LWP) (AMD only)</td><td>XCR0</td></tr><tr><th>63</th><td colspan="2"><i>(reserved)</i><a class="footnote-ref" id="fnref:169" href="#fn:169"><sup>169</sup></a></td></tr></tbody></table> <h2 id="eax12h-sgx-capabilities">EAX=12h: SGX Capabilities</h2> <p>This leaf provides information about the supported capabilities of the Intel <a href="/facts/Software_Guard_Extensions/HcgbyB5P">Software Guard Extensions</a> (SGX) feature. The leaf provides multiple sub-leaves, selected with ECX. </p><p>Sub-leaf 0 provides information about supported SGX leaf functions in EAX and maximum supported SGX enclave sizes in EDX; ECX is reserved. EBX provides a bitmap of bits that can be set in the MISCSELECT field in the SECS (SGX Enclave Control Structure) - this field is used to control information written to the MISC region of the SSA (SGX Save State Area) when an AEX (SGX Asynchronous Enclave Exit) occurs. </p> CPUID EAX=12h,ECX=0: <a href="/facts/Software_Guard_Extensions/HcgbyB5P">SGX</a> leaf functions, MISCSELECT and maximum-sizes<table><tbody><tr><th rowspan="2">Bit</th><th colspan="2">EAX</th><th scope="col" rowspan="19"></th><th colspan="2">EBX</th><th scope="col" rowspan="19"></th><th colspan="2">EDX</th><th rowspan="2">Bit</th></tr><tr><th>Short</th><th>Feature</th><th>Short</th><th>Feature</th><th>Short</th><th>Feature</th></tr><tr><th>0</th><td>sgx1</td><td>SGX1 leaf functions</td><td>EXINFO</td><td>MISCSELECT: report information about page fault and general protection exception that occurred inside enclave</td><td rowspan="8">MaxEnclaveSize_Not64</td><td rowspan="8">Log2 of maximum enclave size supported in non-64-bit mode</td><th>0</th></tr><tr><th>1</th><td>sgx2</td><td>SGX2 leaf functions</td><td>CPINFO</td><td>MISCSELECT: report information about control protection exception that occurred inside enclave</td><th>1</th></tr><tr><th>2</th><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>2</th></tr><tr><th>3</th><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>3</th></tr><tr><th>4</th><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>4</th></tr><tr><th>5</th><td>oss</td><td>ENCLV leaves: EINCVIRTCHILD, EDECVIRTCHILD, and ESETCONTEXT</td><td colspan="2"><i>(reserved)</i></td><th>5</th></tr><tr><th>6</th><td></td><td>ENCLS leaves: ETRACKC, ERDINFO, ELDBC, ELDUC</td><td colspan="2"><i>(reserved)</i></td><th>6</th></tr><tr><th>7</th><td></td><td>ENCLU leaf: EVERIFYREPORT2</td><td colspan="2"><i>(reserved)</i></td><th>7</th></tr><tr><th>8</th><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td rowspan="8">MaxEnclaveSize_64</td><td rowspan="8">Log2 of maximum enclave size supported in 64-bit mode</td><th>8</th></tr><tr><th>9</th><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>9</th></tr><tr><th>10</th><td></td><td>ENCLS leaf: EUPDATESVN</td><td colspan="2"><i>(reserved)</i></td><th>10</th></tr><tr><th>11</th><td></td><td>ENCLU leaf: EDECSSA</td><td colspan="2"><i>(reserved)</i></td><th>11</th></tr><tr><th>12</th><td>256BITSGX</td><td>ENCLU leaf functions EGETKEY256 and EREPORT2</td><td colspan="2"><i>(reserved)</i></td><th>12</th></tr><tr><th>13</th><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>13</th></tr><tr><th>14</th><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>14</th></tr><tr><th>15</th><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>15</th></tr><tr><th>31:16 </th><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>31:16 </th></tr></tbody></table> <p>Sub-leaf 1 provides a bitmap of which bits can be set in the 128-bit ATTRIBUTES field of SECS in EDX:ECX:EBX:EAX (this applies to the SECS copy used as input to the ENCLS[ECREATE] leaf function). The top 64 bits (given in EDX:ECX) are a bitmap of which bits can be set in the XFRM (X-feature request mask) - this mask is a bitmask of which CPU state-components (see leaf 0Dh) will be saved to the SSA in case of an AEX; this has the same layout as the XCR0 control register. The other bits are given in EAX and EBX, as follows: </p> CPUID EAX=12h,ECX=1: <a href="/facts/Software_Guard_Extensions/HcgbyB5P">SGX</a> settable bits in SECS.ATTRIBUTES<table><tbody><tr><th rowspan="2">Bit</th><th colspan="2">EAX</th><th scope="col" rowspan="14"></th><th colspan="2">EBX</th><th rowspan="2">Bit</th></tr><tr><th>Short</th><th>Feature</th><th>Short</th><th>Feature</th></tr><tr><th>0</th><td>(INIT)</td><td><i>(must be 0)</i><a class="footnote-ref" id="fnref:170" href="#fn:170"><sup>170</sup></a></td><td rowspan="12" colspan="2"><i>(reserved)</i></td><th>0</th></tr><tr><th>1</th><td>DEBUG</td><td>Permit debugger to read and write enclave data using EDBGRD and EDBGWR</td><th>1</th></tr><tr><th>2</th><td>MODE64BIT</td><td>64-bit-mode enclave</td><th>2</th></tr><tr><th>3</th><td colspan="2"><i>(reserved)</i></td><th>3</th></tr><tr><th>4</th><td>PROVISIONKEY</td><td>Provisioning key available from EGETKEY</td><th>4</th></tr><tr><th>5</th><td>EINITTOKEN_KEY</td><td>EINIT token key available from EGETKEY</td><th>5</th></tr><tr><th>6</th><td>CET</td><td>CET (Control-Flow Enforcement Technology) attributes enable</td><th>6</th></tr><tr><th>7</th><td>KSS</td><td>Key Separation and Sharing</td><th>7</th></tr><tr><th>8</th><td colspan="2"><i>(reserved)</i></td><th>8</th></tr><tr><th>9</th><td colspan="2"><i>(reserved)</i></td><th>9</th></tr><tr><th>10</th><td>AEXNOTIFY</td><td>Threads inside enclave may receive AEX notifications<a class="footnote-ref" id="fnref:171" href="#fn:171"><sup>171</sup></a></td><th>10</th></tr><tr><th>31:11 </th><td colspan="2"><i>(reserved)</i></td><th>31:11 </th></tr></tbody></table> <p>Sub-leaves 2 and up are used to provide information about which physical memory regions are available for use as EPC (Enclave Page Cache) sections under SGX. </p> CPUID EAX=12h,ECX≥2: <a href="/facts/Software_Guard_Extensions/HcgbyB5P">SGX</a> Enclave Page Cache section information<table><tbody><tr><th>Bits</th><th>EAX</th><th scope="col" rowspan="5"></th><th>EBX</th><th scope="col" rowspan="5"></th><th>ECX</th><th scope="col" rowspan="5"></th><th>EDX</th><th>Bits</th></tr><tr><th>3:0</th><td>Sub-leaf type:<ul><li>0000: Invalid</li><li>0001: EPC section</li><li>other: reserved</li></ul></td><td rowspan="3">Bits 51:32 of physical base address of EPC section</td><td>EPC Section properties:<ul><li>0000: Invalid</li><li>0001: Has confidentiality, integrity, and replay protection</li><li>0010: Has confidentiality protection only</li><li>0011: Has confidentiality and integrity protection</li><li>other: reserved</li></ul></td><td rowspan="3">Bits 51:32 of size of EPC section</td><th>3:0</th></tr><tr><th>11:4 </th><td><i>(reserved)</i></td><td><i>(reserved)</i></td><th>11:4 </th></tr><tr><th>19:12 </th><td rowspan="2">Bits 31:12 of physical base address of EPC section</td><td rowspan="2">Bits 31:12 of size of EPC section</td><th>19:12 </th></tr><tr><th>31:20 </th><td><i>(reserved)</i></td><td><i>(reserved)</i></td><th>31:20 </th></tr></tbody></table> <h2 id="eax14h-ecx0-processor-trace">EAX=14h, ECX=0: Processor Trace</h2> <p>This sub-leaf provides feature information for Intel <a href="/facts/Branch_trace/VqVcYKBl">Processor Trace</a> (also known as Real Time Instruction Trace). </p><p>The value returned in EAX is the index of the highest sub-leaf supported for CPUID with EAX=14h. EBX and ECX provide feature flags, EDX is reserved. </p> CPUID EAX=14h,ECX=0: Processor Trace feature bits in EBX and ECX<table><tbody><tr><th rowspan="2">Bit</th><th colspan="2">EBX</th><th rowspan="14"></th><th colspan="2">ECX</th><th rowspan="2">Bit</th></tr><tr><th>Short</th><th>Feature</th><th>Short</th><th>Feature</th></tr><tr><th>0</th><td></td><td><a href="/facts/Control_register/9VGRHh3f">CR3</a> filtering supported</td><td>topaout</td><td>ToPA (Table of Physical Addresses) output mechanism for trace packets supported</td><th>0</th></tr><tr><th>1</th><td></td><td>Configurable PSB (Packet Stream Boundary) packet rate and Cycle-Accurate Mode (CYC packets) supported</td><td>mentry</td><td>ToPA tables can contain hold multiple output entries</td><th>1</th></tr><tr><th>2</th><td></td><td>IP filtering, TraceStop filtering and preservation of PT MSRs across warm reset supported</td><td>snglrngout</td><td>Single-Range Output scheme supported</td><th>2</th></tr><tr><th>3</th><td></td><td>MTC (Mini Time Counter) timing packets supported, and suppression of COFI (Change of Flow Instructions) packets supported.</td><td></td><td>Output to Trace Transport subsystem supported</td><th>3</th></tr><tr><th>4</th><td>ptwrite</td><td>PTWRITE instruction supported</td><td colspan="2"><i>(reserved)</i></td><th>4</th></tr><tr><th>5</th><td></td><td>Power Event Trace supported</td><td colspan="2"><i>(reserved)</i></td><th>5</th></tr><tr><th>6</th><td></td><td>Preservation of PSB and PMI (performance monitoring interrupt) supported</td><td colspan="2"><i>(reserved)</i></td><th>6</th></tr><tr><th>7</th><td></td><td>Event Trace packet generation supported</td><td colspan="2"><i>(reserved)</i></td><th>7</th></tr><tr><th>8</th><td></td><td>TNT (Branch Taken-Not-Taken) packet generation disable supported.</td><td colspan="2"><i>(reserved)</i></td><th>8</th></tr><tr><th>9</th><td></td><td>PTTT (Processor Trace Trigger Tracing) supported</td><td colspan="2"><i>(reserved)</i></td><th>9</th></tr><tr><th>30:10 </th><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>30:10 </th></tr><tr><th>31</th><td colspan="2"><i>(reserved)</i></td><td></td><td>IP (Instruction Pointer) format for trace packets that contain IP payloads:<ul><li>0=RIP (effective-address IP)</li><li>1=LIP (linear-address IP, with CS base address added)</li></ul></td><th>31</th></tr></tbody></table> <h2 id="eax15h-and-eax16h-cpu-tsc-bus-and-core-crystal-clock-frequencies">EAX=15h and EAX=16h: CPU, TSC, Bus and Core Crystal Clock Frequencies</h2> <p>These two leaves provide information about various frequencies in the CPU in EAX, EBX and ECX (EDX is reserved in both leaves). </p> CPUID EAX=15h: TSC and Core <a href="/facts/Crystal_oscillator/QhhohzPu">Crystal</a> frequency information<table><tbody><tr><th>EAX</th><th>EBX</th><th>ECX</th></tr><tr><td>Ratio of TSC frequency to Core Crystal Clock frequency, denominator</td><td>Ratio of TSC frequency to Core Crystal Clock frequency, numerator<a class="footnote-ref" id="fnref:172" href="#fn:172"><sup>172</sup></a></td><td>Core Crystal Clock frequency, in units of <a href="/facts/Hertz/6Wshj5qm">Hz</a><a class="footnote-ref" id="fnref:173" href="#fn:173"><sup>173</sup></a></td></tr></tbody></table> CPUID EAX=16h: Processor and Bus specification frequencies<a class="footnote-ref" id="fnref:174" href="#fn:174"><sup>174</sup></a><table><tbody><tr><th>Bits</th><th>EAX</th><th>EBX</th><th>ECX</th><th>Bits</th></tr><tr><th>15:0</th><td>Processor Base Frequency (in MHz)<a class="footnote-ref" id="fnref:175" href="#fn:175"><sup>175</sup></a></td><td>Processor Maximum Frequency (in MHz)<a class="footnote-ref" id="fnref:176" href="#fn:176"><sup>176</sup></a></td><td>Bus/Reference frequency (in MHz)<a class="footnote-ref" id="fnref:177" href="#fn:177"><sup>177</sup></a></td><th>15:0</th></tr><tr><th>31:16</th><td><i>(reserved)</i></td><td><i>(reserved)</i></td><td><i>(reserved)</i></td><th>31:16</th></tr></tbody></table> <p>If the returned values in EBX and ECX of leaf 15h are both nonzero, then the TSC (<a href="/facts/Time_Stamp_Counter/THy8g17s">Time Stamp Counter</a>) frequency in Hz is given by TSCFreq = ECX*(EBX/EAX). </p><p>On some processors (e.g. Intel <a href="/facts/Skylake_(microarchitecture)/qpcDcebM">Skylake</a>), CPUID_15h_ECX is zero but CPUID_16h_EAX is present and not zero. On all known processors where this is the case,<a class="footnote-ref" id="fnref:178" href="#fn:178"><sup>178</sup></a> the TSC frequency is equal to the Processor Base Frequency, and the Core Crystal Clock Frequency in Hz can be computed as CoreCrystalFreq = (CPUID_16h_EAX * 10000000) * (CPUID_15h_EAX/CPUID_15h_EBX). </p><p>On processors that enumerate the TSC/Core Crystal Clock ratio in CPUID leaf 15h, the <a href="/facts/Advanced_Programmable_Interrupt_Controller/40lXS8r6">APIC</a> timer frequency will be the Core Crystal Clock frequency divided by the divisor specified by the APIC's Divide Configuration Register.<a class="footnote-ref" id="fnref:179" href="#fn:179"><sup>179</sup></a> </p> <h2 id="eax17h-soc-vendor-attribute-enumeration">EAX=17h: SoC Vendor Attribute Enumeration</h2> <p>This leaf is present in systems where an x86 CPU <a href="/facts/Semiconductor_intellectual_property_core/yx66l6wL">IP core</a> is implemented in an SoC (<a href="/facts/System_on_chip/1RVvVe6N">System on chip</a>) from another vendor - whereas the other leaves of CPUID provide information about the x86 CPU core, this leaf provides information about the SoC. This leaf takes a sub-leaf index in ECX. </p><p>Sub-leaf 0 returns a maximum sub-leaf index in EAX (at least 3), and SoC identification information in EBX/ECX/EDX: </p> CPUID EAX=17h,ECX=0: SoC identification information<table><tbody><tr><th>Bit</th><th>EBX</th><th scope="col" rowspan="4"></th><th>ECX</th><th scope="col" rowspan="4"></th><th>EDX</th><th>Bit</th></tr><tr><th>15:0</th><td>SoC Vendor ID</td><td rowspan="3">SoC Project ID</td><td rowspan="3">SoC Stepping ID within an SoC project</td><th>15:0</th></tr><tr><th>16</th><td>SoC Vendor ID scheme<ul><li>0 : Vendor IDs assigned by Intel<a class="footnote-ref" id="fnref:180" href="#fn:180"><sup>180</sup></a></li><li>1 : Industry standard enumeration scheme<a class="footnote-ref" id="fnref:181" href="#fn:181"><sup>181</sup></a></li></ul></td><th>16</th></tr><tr><th>31:17</th><td><i>(reserved)</i></td><th>31:17</th></tr></tbody></table> <p>Sub-leaves 1 to 3 return a 48-byte SoC vendor brand string in <a href="/facts/UTF-8/xlaVHSyf">UTF-8</a> format. Sub-leaf 1 returns the first 16 bytes in EAX,EBX,ECX,EDX (in that order); sub-leaf 2 returns the next 16 bytes and sub-leaf 3 returns the last 16 bytes. The string is allowed but not required to be <a href="/facts/Null-terminated_string/Vt75UxVG">null-terminated</a>. </p> <h2 id="eax19h-intel-key-locker-features">EAX=19h: Intel Key Locker Features</h2> <p>This leaf provides feature information for Intel Key Locker in EAX, EBX and ECX. EDX is reserved. </p> CPUID EAX=19h: Key Locker feature bits in EAX, EBX and ECX<table><tbody><tr><th rowspan="2">Bit</th><th colspan="2">EAX</th><th scope="col" rowspan="8"></th><th colspan="2">EBX</th><th scope="col" rowspan="8"></th><th colspan="2">ECX</th><th rowspan="2">Bit</th></tr><tr><th>Short</th><th>Feature</th><th>Short</th><th>Feature</th><th>Short</th><th>Feature</th></tr><tr><th>0</th><td></td><td>Key Locker restriction of CPL0-only supported</td><td>aes_kle</td><td><a href="/facts/Advanced_Encryption_Standard/HdXGBY2Q">AES</a> "Key Locker" Instructions enabled</td><td></td><td>No-backup parameter to LOADIWKEY supported</td><th>0</th></tr><tr><th>1</th><td></td><td>Key Locker restriction of no-encrypt supported</td><td colspan="2"><i>(reserved)</i></td><td></td><td>KeySource encoding of 1 (randomization of internal wrapping key) supported</td><th>1</th></tr><tr><th>2</th><td></td><td>Key Locker restriction of no-decrypt supported</td><td>aes_wide_kl</td><td><a href="/facts/Advanced_Encryption_Standard/HdXGBY2Q">AES</a> "Wide Key Locker" Instructions</td><td colspan="2"><i>(reserved)</i></td><th>2</th></tr><tr><th>3</th><td></td><td>(Process Restriction)<a class="footnote-ref" id="fnref:182" href="#fn:182"><sup>182</sup></a></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>3</th></tr><tr><th>4</th><td colspan="2"><i>(reserved)</i></td><td>kl_msrs</td><td>"Key Locker" MSRs</td><td colspan="2"><i>(reserved)</i></td><th>4</th></tr><tr><th>31:5 </th><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>31:5 </th></tr></tbody></table> <h2 id="eax1dh-tile-information">EAX=1Dh: Tile Information</h2> <p>When ECX=0, the highest supported "palette" subleaf is enumerated in EAX. When ECX≥1, information on palette <i>n</i> is returned. </p> CPUID EAX=1Dh,ECX≥1: Tile Palette <i>n</i> Information<table><tbody><tr><th rowspan="2">Bits</th><th colspan="2">EAX</th><th scope="col" rowspan="4"></th><th colspan="2">EBX</th><th scope="col" rowspan="4"></th><th colspan="2">ECX</th><th scope="col" rowspan="4"></th><th colspan="2">EDX</th><th rowspan="2">Bits</th></tr><tr><th>Short</th><th>Feature</th><th>Short</th><th>Feature</th><th>Short</th><th>Feature</th><th>Short</th><th>Feature</th></tr><tr><th>15:0</th><td>total_tile_bytes</td><td>Size of all tile registers, in bytes (8192)</td><td>bytes_per_row</td><td>(64)</td><td>max_rows</td><td>(16)</td><td colspan="2"><i>(reserved)</i></td><th>15:0</th></tr><tr><th>31:16</th><td>bytes_per_tile</td><td>Size of one tile, in bytes (1024)</td><td>max_names</td><td>Number of tile registers (8)</td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>31:16</th></tr></tbody></table> <h2 id="eax1eh-ecx0-tmul-information">EAX=1Eh, ECX=0: TMUL Information</h2> <p>This leaf returns information on the TMUL (tile multiplier) unit. </p> CPUID EAX=1Eh,ECX=0: TMUL Information<table><tbody><tr><th rowspan="2">Bits</th><th colspan="2">EAX</th><th scope="col" rowspan="6"></th><th colspan="2">EBX</th><th scope="col" rowspan="6"></th><th colspan="2">ECX</th><th scope="col" rowspan="6"></th><th colspan="2">EDX</th><th rowspan="2">Bits</th></tr><tr><th>Short</th><th>Feature</th><th>Short</th><th>Feature</th><th>Short</th><th>Feature</th><th>Short</th><th>Feature</th></tr><tr><th>7:0</th><td colspan="2"><i>(reserved)</i></td><td>tmul_maxk</td><td>Maximum number of rows or columns (16)</td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>7:0</th></tr><tr><th>15:8</th><td colspan="2"><i>(reserved)</i></td><td>tmul_maxn</td><td>Maximum number of bytes per column (64)</td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>15:8</th></tr><tr><th>23:16</th><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>23:16</th></tr><tr><th>31:24</th><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>31:24</th></tr></tbody></table> <h2 id="eax1eh-ecx1-tmul-information">EAX=1Eh, ECX=1: TMUL Information</h2> <p>This leaf returns feature flags on the TMUL (tile multiplier) unit. </p> CPUID EAX=1Eh,ECX=0: TMUL Information<table><tbody><tr><th rowspan="2">Bits</th><th colspan="2">EAX</th><th scope="col" rowspan="12"></th><th colspan="2">EBX</th><th scope="col" rowspan="12"></th><th colspan="2">ECX</th><th scope="col" rowspan="12"></th><th colspan="2">EDX</th><th rowspan="2">Bits</th></tr><tr><th>Short</th><th>Feature</th><th>Short</th><th>Feature</th><th>Short</th><th>Feature</th><th>Short</th><th>Feature</th></tr><tr><th>0</th><td>amx-int8</td><td>8-bit integer support</td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>0</th></tr><tr><th>1</th><td>amx-bf16</td><td><a href="/facts/Bfloat16/wo1Q6IJY">bfloat16</a> support</td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>1</th></tr><tr><th>2</th><td>amx-complex</td><td>Complex number support</td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>2</th></tr><tr><th>3</th><td>amx-fp16</td><td>float16 support</td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>3</th></tr><tr><th>4</th><td>amx-fp8</td><td>float8 support</td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>4</th></tr><tr><th>5</th><td>amx-transpose</td><td>Transposition instruction support</td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>5</th></tr><tr><th>6</th><td>amx-tf32</td><td>tf32/fp19 support</td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>6</th></tr><tr><th>7</th><td>amx-avx512</td><td>AMX-AVX512 support</td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>7</th></tr><tr><th>8</th><td>amx-movrs</td><td>AMX-MOVRS support</td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>8</th></tr><tr><th>31:9</th><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>31:9</th></tr></tbody></table> <h2 id="eax21h-reserved-for-tdx-enumeration">EAX=21h: Reserved for TDX enumeration</h2> <p>When Intel TDX (<a href="/facts/Trust_Domain_Extensions/fQmFGo6j">Trust Domain Extensions</a>) is active, attempts to execute the CPUID instruction by a TD (Trust Domain) guest will be intercepted by the TDX module. This module will, when CPUID is invoked with EAX=21h and ECX=0 (leaf 21h, sub-leaf 0), return the index of the highest supported sub-leaf for leaf 21h in EAX and a TDX module vendor ID string as a 12-byte ASCII string in EBX,EDX,ECX (in that order). Intel's own module implementation returns the vendor ID string "IntelTDX " (with four trailing spaces)<a class="footnote-ref" id="fnref:183" href="#fn:183"><sup>183</sup></a> - for this module, additional feature information is not available through CPUID and must instead be obtained through the TDX-specific TDCALL instruction. </p><p>This leaf is reserved in hardware and will (on processors whose highest basic leaf is 21h or higher) return 0 in EAX/EBX/ECX/EDX when run directly on the CPU. </p> <h2 id="eax24h-ecx0-avx10-converged-vector-isa">EAX=24h, ECX=0: AVX10 Converged Vector ISA</h2> <p>This returns a maximum supported sub-leaf in EAX and AVX10 feature information in EBX.<a class="footnote-ref" id="fnref:184" href="#fn:184"><sup>184</sup></a> (ECX and EDX are reserved.) </p> CPUID EAX=24h, ECX=0: AVX10 feature bits in EBX<table><tbody><tr><th rowspan="2">Bit</th><th colspan="2">EBX</th></tr><tr><th>Short</th><th>Feature</th></tr><tr><th>7:0</th><td></td><td>AVX10 Converged Vector ISA version (≥1)</td></tr><tr><th>15:8</th><td colspan="2"><i>(reserved)</i></td></tr><tr><th>18:16</th><td colspan="2"><i>(reserved as 111b)</i><a class="footnote-ref" id="fnref:185" href="#fn:185"><sup>185</sup></a></td></tr><tr><th>31:19</th><td colspan="2"><i>(reserved)</i></td></tr></tbody></table> <h2 id="eax24h-ecx1-discrete-avx10-features">EAX=24h, ECX=1: Discrete AVX10 Features</h2> <p>Subleaf 1 is reserved for AVX10 features not bound to a version. </p> CPUID EAX=24h, ECX=1: Discrete AVX10 features in ECX<table><tbody><tr><th rowspan="2">Bit</th><th colspan="2">ECX</th></tr><tr><th>Short</th><th>Feature</th></tr><tr><th>0</th><td>(VPMM)</td><td>(Vector-Extension Packed Matrix Multiplication)<a class="footnote-ref" id="fnref:186" href="#fn:186"><sup>186</sup></a></td></tr><tr><th>1</th><td colspan="2"><i>(reserved)</i></td></tr><tr><th>2</th><td>AVX10_VNNI_INT</td><td>AVX10.2 VNNI instructions<a class="footnote-ref" id="fnref:187" href="#fn:187"><sup>187</sup></a><a class="footnote-ref" id="fnref:188" href="#fn:188"><sup>188</sup></a></td></tr><tr><th>31:3</th><td colspan="2"><i>(reserved)</i></td></tr></tbody></table> <h2 id="eax20000000h-highest-xeon-phi-function-implemented">EAX=2000'0000h: Highest Xeon Phi Function Implemented</h2> <p>The highest function is returned in EAX. This leaf is only present on <a href="/facts/Xeon_Phi/Fv5dhyKc">Xeon Phi</a> processors.<a class="footnote-ref" id="fnref:189" href="#fn:189"><sup>189</sup></a> </p> <h2 id="eax20000001h-xeon-phi-feature-bits">EAX=2000'0001h: Xeon Phi Feature Bits</h2> <p>This function returns feature flags. </p> CPUID EAX=2000'0001h: Xeon Phi feature bits<table><tbody><tr><th rowspan="2">Bit</th><th colspan="2">EAX</th><th scope="col" rowspan="5"></th><th colspan="2">EBX</th><th scope="col" rowspan="5"></th><th colspan="2">ECX</th><th scope="col" rowspan="5"></th><th colspan="2">EDX</th><th rowspan="2">Bit</th></tr><tr><th>Short</th><th>Feature</th><th>Short</th><th>Feature</th><th>Short</th><th>Feature</th><th>Short</th><th>Feature</th></tr><tr><th>3:0</th><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>3:0</th></tr><tr><th>4</th><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td>k1om</td><td>K1OM<a class="footnote-ref" id="fnref:190" href="#fn:190"><sup>190</sup></a></td><th>4</th></tr><tr><th>31:5</th><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>31:5</th></tr></tbody></table> <h2 id="eax40000000h-4fffffffh-reserved-for-hypervisors">EAX=4000'0000h-4FFFF'FFFh: Reserved for <a href="/facts/Hypervisor/3gX9fKlH">Hypervisors</a></h2> <p>When the CPUID instruction is executed under <a href="/facts/X86_virtualization/utQwmdY3">Intel VT-x or AMD-v virtualization</a>, it will be intercepted by the hypervisor, enabling the hypervisor to return CPUID feature flags that differ from those of the underlying hardware. CPUID leaves 40000000h to 4FFFFFFFh are not implemented in hardware, and are reserved for use by hypervisors to provide hypervisor-specific identification and feature information through this interception mechanism. </p><p>For leaf 40000000h, the hypervisor is expected to return the index of the highest supported hypervisor CPUID leaf in EAX, and a 12-character hypervisor ID string in EBX,ECX,EDX (in that order). For leaf 40000001h, the hypervisor may return an interface identification signature in EAX - e.g. hypervisors that wish to advertise that they are <a href="/facts/Hyper-V/3Qm0yJsv">Hyper-V</a> compatible may return 0x31237648—"Hv#1" in EAX.<a class="footnote-ref" id="fnref:191" href="#fn:191"><sup>191</sup></a><a class="footnote-ref" id="fnref:192" href="#fn:192"><sup>192</sup></a> The formats of leaves 40000001h and up to the highest supported leaf are otherwise hypervisor-specific. Hypervisors that implement these leaves will normally also set bit 31 of ECX for CPUID leaf 1 to indicate their presence. </p><p>Hypervisors that expose more than one hypervisor interface may provide additional sets of CPUID leaves for the additional interfaces, at a spacing of 100h leaves per interface. For example, when <a href="/facts/QEMU/s6utqULJ">QEMU</a> is configured to provide both <a href="/facts/Hyper-V/3Qm0yJsv">Hyper-V</a> and <a href="/facts/Kernel-based_Virtual_Machine/d6eSuTuK">KVM</a> interfaces, it will provide Hyper-V information starting from CPUID leaf 40000000h and KVM information starting from leaf 40000100h.<a class="footnote-ref" id="fnref:193" href="#fn:193"><sup>193</sup></a><a class="footnote-ref" id="fnref:194" href="#fn:194"><sup>194</sup></a> </p> <p>Some hypervisors that are known to return a hypervisor ID string in leaf 40000000h include: </p> CPUID EAX=4000'0x00h: 12-character Hypervisor ID string in EBX,ECX,EDX<table><tbody><tr><th>Hypervisor</th><th>ID String (ASCII)</th><th>Notes</th></tr><tr><td>Microsoft <a href="/facts/Hyper-V/3Qm0yJsv">Hyper-V</a>,<a href="/facts/Windows_Virtual_PC/wKdazyS3">Windows Virtual PC</a></td><td>"Microsoft Hv"<a class="footnote-ref" id="fnref:195" href="#fn:195"><sup>195</sup></a></td><td></td></tr><tr><td rowspan="2">Linux <a href="/facts/Kernel-based_Virtual_Machine/d6eSuTuK">KVM</a></td><td>"KVMKVMKVM\0\0\0"<a class="footnote-ref" id="fnref:196" href="#fn:196"><sup>196</sup></a></td><td>\0 denotes an ASCII NUL character.</td></tr><tr><td>"Linux KVM Hv"<a class="footnote-ref" id="fnref:197" href="#fn:197"><sup>197</sup></a></td><td>Hyper-V emulation<a class="footnote-ref" id="fnref:198" href="#fn:198"><sup>198</sup></a></td></tr><tr><td><a href="/facts/Bhyve/mCm8pV39">bhyve</a></td><td>"BHyVE BHyVE ","bhyve bhyve "</td><td>ID string changed from mixed-case to lower-case in 2013.<a class="footnote-ref" id="fnref:199" href="#fn:199"><sup>199</sup></a><p>Lower-case string also used in bhyve-derived hypervisors such as xhyve and HyperKit.<a class="footnote-ref" id="fnref:200" href="#fn:200"><sup>200</sup></a></p></td></tr><tr><td><a href="/facts/Xen/U5fq6ESl">Xen</a></td><td>"XenVMMXenVMM"<a class="footnote-ref" id="fnref:201" href="#fn:201"><sup>201</sup></a></td><td>Only when using HVM (hardware virtual machine) mode.</td></tr><tr><td><a href="/facts/QEMU/s6utqULJ">QEMU</a></td><td>"TCGTCGTCGTCG"<a class="footnote-ref" id="fnref:202" href="#fn:202"><sup>202</sup></a></td><td>Only when the TCG (Tiny Code Generator) is enabled.</td></tr><tr><td><a href="/facts/Parallels_(company)/pRhfRest">Parallels</a></td><td>" lrpepyh vr"</td><td>(it possibly should be "prl hyperv", but it is encoded as " lrpepyh vr" due to an <a href="/facts/Endianness/wbrQnyu3">endianness</a> mismatch)</td></tr><tr><td><a href="/facts/VMware/lKHGULx3">VMware</a></td><td>"VMwareVMware"<a class="footnote-ref" id="fnref:203" href="#fn:203"><sup>203</sup></a></td><td></td></tr><tr><td>Project ACRN</td><td>"ACRNACRNACRN"<a class="footnote-ref" id="fnref:204" href="#fn:204"><sup>204</sup></a></td><td></td></tr><tr><td><a href="/facts/VirtualBox/8wordR1n">VirtualBox</a></td><td>"VBoxVBoxVBox"<a class="footnote-ref" id="fnref:205" href="#fn:205"><sup>205</sup></a></td><td>Only when configured to use the "hyperv" paravirtualization provider.</td></tr><tr><td><a href="/facts/QNX/gBsfJvcB">QNX</a> Hypervisor</td><td>"QXNQSBMV"</td><td>The QNX hypervisor detection method provided in the official QNX documentation<a class="footnote-ref" id="fnref:206" href="#fn:206"><sup>206</sup></a> checks only the first 8 characters of the string, as provided in EBX and ECX (including an endianness swap) - EDX is ignored and may take any value.</td></tr><tr><td><a href="/facts/NetBSD/PTm5HWls">NetBSD NVMM</a></td><td>"___ NVMM ___"<a class="footnote-ref" id="fnref:207" href="#fn:207"><sup>207</sup></a></td></tr><tr><td><a href="/facts/OpenBSD/xmPS9tek">OpenBSD</a> VMM</td><td>"OpenBSDVMM58"<a class="footnote-ref" id="fnref:208" href="#fn:208"><sup>208</sup></a></td><td></td></tr><tr><td>Siemens Jailhouse</td><td>"Jailhouse\0\0\0"<a class="footnote-ref" id="fnref:209" href="#fn:209"><sup>209</sup></a></td><td>\0 denotes an ASCII NUL character.</td></tr><tr><td><a href="/facts/Bitdefender/gKfw9PBB">Bitdefender</a> Napoca</td><td>"Napocahv "<a class="footnote-ref" id="fnref:210" href="#fn:210"><sup>210</sup></a></td><td></td></tr><tr><td>Intel HAXM</td><td>"HAXMHAXMHAXM"<a class="footnote-ref" id="fnref:211" href="#fn:211"><sup>211</sup></a></td><td>Project discontinued.</td></tr><tr><td>Intel KGT (Trusty)</td><td>"EVMMEVMMEVMM"<a class="footnote-ref" id="fnref:212" href="#fn:212"><sup>212</sup></a></td><td>On "trusty" branch of KGT only, which is used for the <a href="https://www.intel.com/content/www/us/en/developer/topic-technology/open/trusty/overview.html">Intel x86 Architecture Distribution of Trusty OS</a> (<a href="https://web.archive.org/web/20230821024540/https://www.intel.com/content/www/us/en/developer/topic-technology/open/trusty/overview.html">archive</a>)<p>(KGT also returns a signature in CPUID leaf 3: ECX=0x4D4D5645 "EVMM" and EDX=0x43544E49 "INTC")</p></td></tr><tr><td><a href="/facts/Unisys/y49ddC6b">Unisys</a> s-Par</td><td>"UnisysSpar64"<a class="footnote-ref" id="fnref:213" href="#fn:213"><sup>213</sup></a></td><td></td></tr><tr><td><a href="/facts/Lockheed_Martin/URp9BQpA">Lockheed Martin</a> LMHS</td><td>"SRESRESRESRE"<a class="footnote-ref" id="fnref:214" href="#fn:214"><sup>214</sup></a></td></tr></tbody></table> <h2 id="eax80000000h-highest-extended-function-implemented">EAX=8000'0000h: Highest Extended Function Implemented</h2> <p>The highest calling parameter is returned in EAX. </p><p>EBX/ECX/EDX return the manufacturer ID string (same as EAX=0) on AMD but not Intel CPUs. </p> <h2 id="eax80000001h-extended-processor-info-and-feature-bits">EAX=8000'0001h: Extended Processor Info and Feature Bits</h2> <p>This returns extended feature flags in EDX and ECX. </p><p>Many of the bits in EDX (bits 0 through 9, 12 through 17, 23, and 24) are duplicates of EDX from the EAX=1 leaf - these bits are highlighted in light yellow. (These duplicated bits are present on AMD but not Intel CPUs.) </p><p>AMD feature flags are as follows:<a class="footnote-ref" id="fnref:215" href="#fn:215"><sup>215</sup></a><a class="footnote-ref" id="fnref:216" href="#fn:216"><sup>216</sup></a> </p> CPUID EAX=8000'0001h: Feature bits in EDX and ECX<table><tbody><tr><th rowspan="2">Bit</th><th colspan="2">EDX</th><th scope="col" rowspan="34"></th><th colspan="2">ECX</th><th rowspan="2">Bit</th></tr><tr><th>Short</th><th>Feature</th><th>Short</th><th>Feature</th></tr><tr><th>0</th><td>fpu</td><td>Onboard <a href="/facts/X87/y8X9HnLL">x87</a> FPU</td><td>lahf_lm</td><td>LAHF/SAHF in long mode</td><th>0</th></tr><tr><th>1</th><td>vme</td><td>Virtual mode extensions (VIF)</td><td>cmp_legacy</td><td><a href="/facts/Hyperthreading/hjqGgK8V">Hyperthreading</a> not valid</td><th>1</th></tr><tr><th>2</th><td>de</td><td>Debugging extensions (<a href="/facts/Control_register/9VGRHh3f">CR4</a> bit 3)</td><td>svm</td><td><a href="/facts/Secure_Virtual_Machine/utQwmdY3">Secure Virtual Machine</a></td><th>2</th></tr><tr><th>3</th><td>pse</td><td><a href="/facts/Page_Size_Extension/V35daBet">Page Size Extension</a></td><td>extapic</td><td>Extended <a href="/facts/Advanced_Programmable_Interrupt_Controller/40lXS8r6">APIC</a> space</td><th>3</th></tr><tr><th>4</th><td>tsc</td><td><a href="/facts/Time_Stamp_Counter/THy8g17s">Time Stamp Counter</a></td><td>cr8_legacy</td><td><a href="/facts/Control_register/9VGRHh3f">CR8</a> in 32-bit mode</td><th>4</th></tr><tr><th>5</th><td>msr</td><td><a href="/facts/Model-specific_register/uzoD3Ynm">Model-specific registers</a></td><td>abm/lzcnt</td><td><a href="/facts/Advanced_Bit_Manipulation/LJAm1LWC">Advanced bit manipulation</a> (<a href="/facts/Lzcnt/hBDYDy8z">LZCNT</a> and <a href="/facts/Popcnt/dJIW7qg4">POPCNT</a>)</td><th>5</th></tr><tr><th>6</th><td>pae</td><td><a href="/facts/Physical_Address_Extension/aEr4tj4x">Physical Address Extension</a></td><td>sse4a</td><td><a href="/facts/SSE4a/Tnxrl7Ph">SSE4a</a></td><th>6</th></tr><tr><th>7</th><td>mce</td><td><a href="/facts/Machine_Check_Exception/8aLxkI6W">Machine Check Exception</a></td><td>misalignsse</td><td>Misaligned <a href="/facts/Streaming_SIMD_Extensions/mMa6EFyB">SSE</a> mode</td><th>7</th></tr><tr><th>8</th><td>cx8</td><td>CMPXCHG8B (<a href="/facts/Compare-and-swap/7mJkkycd">compare-and-swap</a>) instruction</td><td>3dnowprefetch</td><td>PREFETCH and PREFETCHW instructions</td><th>8</th></tr><tr><th>9</th><td>apic</td><td>Onboard <a href="/facts/Advanced_Programmable_Interrupt_Controller/40lXS8r6">Advanced Programmable Interrupt Controller</a></td><td>osvw</td><td>OS Visible Workaround</td><th>9</th></tr><tr><th>10</th><td>(syscall)<a class="footnote-ref" id="fnref:217" href="#fn:217"><sup>217</sup></a></td><td>(SYSCALL/SYSRET, K6 only)</td><td>ibs</td><td><a href="/facts/Hardware_performance_counter/gVe7AyKQ">Instruction Based Sampling</a></td><th>10</th></tr><tr><th>11</th><td>syscall<a class="footnote-ref" id="fnref:218" href="#fn:218"><sup>218</sup></a></td><td>SYSCALL and SYSRET instructions</td><td>xop</td><td><a href="/facts/XOP_instruction_set/Xey2cAGM">XOP instruction set</a></td><th>11</th></tr><tr><th>12</th><td>mtrr</td><td><a href="/facts/Memory_Type_Range_Registers/gMC50p6b">Memory Type Range Registers</a></td><td>skinit</td><td>SKINIT/STGI instructions</td><th>12</th></tr><tr><th>13</th><td>pge</td><td>Page Global Enable bit in <a href="/facts/Control_register/9VGRHh3f">CR4</a></td><td>wdt</td><td><a href="/facts/Watchdog_timer/QaXKTqL8">Watchdog timer</a></td><th>13</th></tr><tr><th>14</th><td>mca</td><td><a href="/facts/Machine_check_architecture/zLk8GyQW">Machine check architecture</a></td><td colspan="2"><i>(reserved)</i></td><th>14</th></tr><tr><th>15</th><td>cmov</td><td>Conditional move and <a href="/facts/FCMOV/2WgVBPK4">FCMOV</a> instructions</td><td>lwp</td><td>Light Weight Profiling<a class="footnote-ref" id="fnref:219" href="#fn:219"><sup>219</sup></a></td><th>15</th></tr><tr><th>16</th><td>pat<a class="footnote-ref" id="fnref:220" href="#fn:220"><sup>220</sup></a></td><td><a href="/facts/Page_Attribute_Table/wY8u28fc">Page Attribute Table</a></td><td>fma4</td><td><a href="/facts/FMA_instruction_set/mqglSHqk">4-operand fused multiply-add instructions</a></td><th>16</th></tr><tr><th>17</th><td>pse36</td><td><a href="/facts/PSE-36/UG8myR82">36-bit page size extension</a></td><td>tce</td><td>Translation Cache Extension</td><th>17</th></tr><tr><th>18</th><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>18</th></tr><tr><th>19</th><td>ecc</td><td>"<a href="/facts/Athlon_XP/3BFQu05f">Athlon MP</a>" / "<a href="/facts/Sempron/hk5blISe">Sempron</a>" CPU brand identification<a class="footnote-ref" id="fnref:221" href="#fn:221"><sup>221</sup></a></td><td>nodeid_msr</td><td>NodeID MSR (C001_100C)<a class="footnote-ref" id="fnref:222" href="#fn:222"><sup>222</sup></a></td><th>19</th></tr><tr><th>20</th><td>nx</td><td><a href="/facts/NX_bit/MnBB93BK">NX bit</a></td><td colspan="2"><i>(reserved)</i></td><th>20</th></tr><tr><th>21</th><td colspan="2"><i>(reserved)</i></td><td>tbm</td><td><a href="/facts/Bit_Manipulation_Instruction_Sets/LJAm1LWC">Trailing Bit Manipulation</a></td><th>21</th></tr><tr><th>22</th><td>mmxext</td><td><a href="/facts/3DNow!/QYJL2HBt">Extended MMX</a></td><td>topoext</td><td>Topology Extensions</td><th>22</th></tr><tr><th>23</th><td>mmx</td><td><a href="/facts/MMX_(instruction_set)/8o3JJhns">MMX</a> instructions</td><td>perfctr_core</td><td>Core performance counter extensions</td><th>23</th></tr><tr><th>24</th><td>fxsr<a class="footnote-ref" id="fnref:223" href="#fn:223"><sup>223</sup></a></td><td>FXSAVE, FXRSTOR instructions, <a href="/facts/Control_register/9VGRHh3f">CR4</a> bit 9</td><td>perfctr_nb</td><td><a href="/facts/Northbridge_(computing)/XFbfH4Kl">Northbridge</a> performance counter extensions</td><th>24</th></tr><tr><th>25</th><td>fxsr_opt</td><td>FXSAVE/FXRSTOR optimizations</td><td>(StreamPerfMon)</td><td>(Streaming performance monitor architecture)<a class="footnote-ref" id="fnref:224" href="#fn:224"><sup>224</sup></a></td><th>25</th></tr><tr><th>26</th><td>pdpe1gb</td><td><a href="/facts/Gigabyte/s2hb2SEg">Gigabyte</a> pages</td><td>dbx</td><td>Data breakpoint extensions</td><th>26</th></tr><tr><th>27</th><td>rdtscp</td><td>RDTSCP instruction</td><td>perftsc</td><td>Performance timestamp counter (PTSC)</td><th>27</th></tr><tr><th>28</th><td colspan="2"><i>(reserved)</i></td><td>pcx_l2i</td><td>L2I perf counter extensions</td><th>28</th></tr><tr><th>29</th><td>lm</td><td><a href="/facts/Long_mode/ITshSuE6">Long mode</a></td><td>monitorx</td><td>MONITORX and MWAITX instructions</td><th>29</th></tr><tr><th>30</th><td>3dnowext</td><td><a href="/facts/3DNow!/QYJL2HBt">Extended 3DNow!</a></td><td>addr_mask_ext</td><td>Address mask extension to 32 bits for instruction breakpoints</td><th>30</th></tr><tr><th>31</th><td>3dnow</td><td><a href="/facts/3DNow!/QYJL2HBt">3DNow!</a></td><td colspan="2"><i>(reserved)</i></td><th>31</th></tr></tbody></table> <h2 id="eax80000002h80000003h80000004h-processor-brand-string">EAX=8000'0002h,8000'0003h,8000'0004h: Processor Brand String</h2> <p>These return the processor brand string in EAX, EBX, ECX and EDX. CPUID must be issued with each parameter in sequence to get the entire 48-byte ASCII processor brand string.<a class="footnote-ref" id="fnref:225" href="#fn:225"><sup>225</sup></a> It is necessary to check whether the feature is present in the CPU by issuing CPUID with EAX = 80000000h first and checking if the returned value is not less than 80000004h. </p><p>The string is specified in Intel/AMD documentation to be <a href="/facts/Null-terminated_string/Vt75UxVG">null-terminated</a>, however this is not always the case (e.g. DM&P <a href="/facts/Vortex86/EbQ03bc5">Vortex86DX3</a> and AMD <a href="/facts/List_of_AMD_Ryzen_processors/tUl7QggV">Ryzen 7 6800HS</a> are known to return non-null-terminated brand strings in leaves 80000002h-80000004h<a class="footnote-ref" id="fnref:226" href="#fn:226"><sup>226</sup></a><a class="footnote-ref" id="fnref:227" href="#fn:227"><sup>227</sup></a>), and software should not rely on it. </p> #include <stdio.h> #include <string.h> #include <cpuid.h> int main() { unsigned int regs[12]; char str[sizeof(regs)+1]; __cpuid(0x80000000, regs[0], regs[1], regs[2], regs[3]); if (regs[0] < 0x80000004) return 1; __cpuid(0x80000002, regs[0], regs[1], regs[2], regs[3]); __cpuid(0x80000003, regs[4], regs[5], regs[6], regs[7]); __cpuid(0x80000004, regs[8], regs[9], regs[10], regs[11]); memcpy(str, regs, sizeof(regs)); str[sizeof(regs)] = '\0'; printf("%s\n", str); return 0; } <p>On AMD processors, from <a href="/facts/List_of_AMD_Athlon_processors/sfqNLngw">180nm Athlon</a> onwards (AuthenticAMD Family 6 Model 2 and later), it is possible to modify the processor brand string returned by CPUID leaves 80000002h-80000004h by using the WRMSR instruction to write a 48-byte replacement string to MSRs C0010030h-C0010035h.<a class="footnote-ref" id="fnref:228" href="#fn:228"><sup>228</sup></a><a class="footnote-ref" id="fnref:229" href="#fn:229"><sup>229</sup></a> This can also be done on AMD Geode GX/LX, albeit using MSRs 300Ah-300Fh.<a class="footnote-ref" id="fnref:230" href="#fn:230"><sup>230</sup></a> </p> <p>In some cases, determining the CPU vendor requires examining not just the Vendor ID in CPUID leaf 0 and the CPU signature in leaf 1, but also the Processor Brand String in leaves 80000002h-80000004h. Known cases include: </p> <ul><li>Montage Jintide CPUs can be distinguished from the Intel Xeon CPU models they're based on by the presence of the substring Montage in the brand string of the Montage CPUs (e.g. Montage Jintide C2460<a class="footnote-ref" id="fnref:231" href="#fn:231"><sup>231</sup></a> and Intel Xeon Platinum 8160<a class="footnote-ref" id="fnref:232" href="#fn:232"><sup>232</sup></a> - both of which identify themselves as GenuineIntel Family 6 Model 55h Stepping 4 - can be distinguished in this manner.)</li> <li>CentaurHauls Family 6 CPUs may be either VIA or Zhaoxin CPUs - these can be distinguished by the presence of the substring ZHAOXIN in the brand string of the Zhaoxin CPUs (e.g. Zhaoxin KaiXian ZX-C+ C4580<a class="footnote-ref" id="fnref:233" href="#fn:233"><sup>233</sup></a> and VIA Eden X4 C4250<a class="footnote-ref" id="fnref:234" href="#fn:234"><sup>234</sup></a> - both of which identify themselves as CentaurHauls Family 6 Model 0Fh Stepping 0Eh - can be distinguished in this manner.)</li></ul> <h2 id="eax80000005h-l1-cache-and-tlb-identifiers">EAX=8000'0005h: L1 Cache and TLB Identifiers</h2> <p>This provides information about the processor's level-1 cache and <a href="/facts/Translation_lookaside_buffer/vvwGkfvD">TLB</a> characteristics in EAX, EBX, ECX and EDX as follows:<a class="footnote-ref" id="fnref:235" href="#fn:235"><sup>235</sup></a> </p> <ul><li>EAX: information about L1 hugepage TLBs (TLBs that hold entries corresponding to 2M/4M pages)<a class="footnote-ref" id="fnref:236" href="#fn:236"><sup>236</sup></a></li> <li>EBX: information about L1 small-page TLBs (TLBs that hold entries corresponding to 4K pages)</li> <li>ECX: information about L1 data cache</li> <li>EDX: information about L1 instruction cache</li></ul> CPUID EAX=8000'0005h: L1 Cache/TLB information in EAX,EBX,ECX,EDX<table><tbody><tr><th>Bits</th><th>EAX</th><th>EBX</th><th scope="col" rowspan="5"></th><th>ECX</th><th>EDX</th><th>Bits</th></tr><tr><th>7:0</th><td colspan="2">Number of instruction TLB entries<a class="footnote-ref" id="fnref:237" href="#fn:237"><sup>237</sup></a></td><td colspan="2">Cache line size in bytes</td><th>7:0</th></tr><tr><th>15:8</th><td colspan="2">instruction TLB associativity<a class="footnote-ref" id="fnref:238" href="#fn:238"><sup>238</sup></a></td><td colspan="2">Number of cache lines per tag</td><th>15:8</th></tr><tr><th>23:16</th><td colspan="2">Number of data TLB entries<a class="footnote-ref" id="fnref:239" href="#fn:239"><sup>239</sup></a></td><td colspan="2">Cache associativity<a class="footnote-ref" id="fnref:240" href="#fn:240"><sup>240</sup></a></td><th>23:16</th></tr><tr><th>31:24</th><td colspan="2">Data TLB associativity<a class="footnote-ref" id="fnref:241" href="#fn:241"><sup>241</sup></a></td><td colspan="2">Cache size in kilobytes</td><th>31:24</th></tr></tbody></table> <h2 id="eax80000006h-extended-l2-cache-features">EAX=8000'0006h: Extended L2 Cache Features</h2> <p>Returns details of the L2 cache in ECX, including the line size in bytes (Bits 07 - 00), type of associativity (encoded by a 4 bits field; Bits 15 - 12) and the cache size in KB (Bits 31 - 16). </p> #include <stdio.h> #include <cpuid.h> int main() { unsigned int eax, ebx, ecx, edx; unsigned int lsize, assoc, cache; __cpuid(0x80000006, eax, ebx, ecx, edx); lsize = ecx & 0xff; assoc = (ecx >> 12) & 0x07; cache = (ecx >> 16) & 0xffff; printf("Line size: %d B, Assoc. type: %d, Cache size: %d KB.\n", lsize, assoc, cache); return 0; } <h2 id="eax80000007h-processor-power-management-information-and-ras-capabilities">EAX=8000'0007h: Processor Power Management Information and RAS Capabilities</h2> <p>This function provides information about power management, power reporting and RAS (<a href="/facts/Reliability%2c_availability_and_serviceability/alWe5yD1">Reliability, availability and serviceability</a>) capabilities of the CPU. </p> CPUID EAX=8000'0007h: RAS features in EBX and power management features in EDX<table><tbody><tr><th rowspan="2">Bit</th><th colspan="2">EBX</th><th scope="col" rowspan="19"></th><th colspan="2">EDX</th><th rowspan="2">Bit</th></tr><tr><th>Short</th><th>Feature</th><th>Short</th><th>Feature</th></tr><tr><th>0</th><td>MCAOverflowRecov</td><td>MCA (Machine Check Architecture) overflow recovery support</td><td>TS</td><td>Temperature Sensor</td><th>0</th></tr><tr><th>1</th><td>SUCCOR</td><td>Software uncorrectable error containment and recovery capability</td><td>FID</td><td>Frequency ID Control</td><th>1</th></tr><tr><th>2</th><td>HWA</td><td>Hardware assert support (MSRs C001_10C0 to C001_10DF</td><td>VID</td><td>Voltage ID Control</td><th>2</th></tr><tr><th>3</th><td>ScalableMca</td><td>Scalable MCA supported</td><td>TTP</td><td>THERMTRIP</td><th>3</th></tr><tr><th>4</th><td colspan="2"><i>(reserved)</i></td><td>TM</td><td>Hardware thermal control (HTC) supported</td><th>4</th></tr><tr><th>5</th><td colspan="2"><i>(reserved)</i></td><td>STC</td><td>Software thermal control (STC) supported<a class="footnote-ref" id="fnref:242" href="#fn:242"><sup>242</sup></a></td><th>5</th></tr><tr><th>6</th><td colspan="2"><i>(reserved)</i></td><td>100MHzSteps</td><td>100 MHz multiplier control</td><th>6</th></tr><tr><th>7</th><td colspan="2"><i>(reserved)</i></td><td>HwPstate</td><td>Hardware P-state control (MSRs C001_0061 to C001_0063)</td><th>7</th></tr><tr><th>8</th><td colspan="2"><i>(reserved)</i></td><td>TscInvariant</td><td>Invariant TSC - TSC (<a href="/facts/Time_Stamp_Counter/THy8g17s">Time Stamp Counter</a>) rate is guaranteed to be invariant across all P-states, C-states and sop grant transitions.</td><th>8</th></tr><tr><th>9</th><td colspan="2"><i>(reserved)</i></td><td>CPB</td><td>Core Performance Boost</td><th>9</th></tr><tr><th>10</th><td colspan="2"><i>(reserved)</i></td><td>EffFreqRO</td><td>Read-only effective frequency interface (MSRs C000_00E7 and C000_00E8)</td><th>10</th></tr><tr><th>11</th><td colspan="2"><i>(reserved)</i></td><td>ProcFeedbackInterface</td><td>Processor Feedback Interface supported</td><th>11</th></tr><tr><th>12</th><td colspan="2"><i>(reserved)</i></td><td>ProcPowerReporting</td><td>Processor power reporting interface supported</td><th>12</th></tr><tr><th>13</th><td colspan="2"><i>(reserved)</i></td><td>ConnectedStandby</td><td>Connected Standby<a class="footnote-ref" id="fnref:243" href="#fn:243"><sup>243</sup></a></td><th>13</th></tr><tr><th>14</th><td colspan="2"><i>(reserved)</i></td><td>RAPL</td><td>Running Average Power Limit<a class="footnote-ref" id="fnref:244" href="#fn:244"><sup>244</sup></a></td><th>14</th></tr><tr><th>15</th><td colspan="2"><i>(reserved)</i></td><td>FastCPPC</td><td>Fast CPPC (Collaborative Processor Performance Control) supported<a class="footnote-ref" id="fnref:245" href="#fn:245"><sup>245</sup></a></td><th>15</th></tr><tr><th>31:16 </th><td colspan="2"><i>(reserved)</i></td><td colspan="2"><i>(reserved)</i></td><th>31:16 </th></tr></tbody></table> CPUID EAX=8000'0007h: Processor Feedback info in EAX and power monitoring interface info in ECX<table><tbody><tr><th rowspan="2">Bits</th><th colspan="2">EAX</th><th scope="col" rowspan="5"></th><th colspan="2">ECX</th><th rowspan="2">Bits</th></tr><tr><th>Short</th><th>Feature</th><th>Short</th><th>Feature</th></tr><tr><th>7:0</th><td>NumberOfMonitors</td><td>Number of Processor Feedback MSR pairs available, starting from MSR C001_0080 onwards<a class="footnote-ref" id="fnref:246" href="#fn:246"><sup>246</sup></a></td><td rowspan="3">CpuPwrSampleTimeRatio</td><td rowspan="3">Ratio of compute unit power accumulator sample period to TSC counter period.</td><th>7:0</th></tr><tr><th>15:8</th><td>Version</td><td>Processor Feedback Capabilities version</td><th>15:8</th></tr><tr><th>31:16</th><td>MaxWrapTime</td><td>Maximum time between reads (in milliseconds) that software should use to avoid two wraps.</td><th>31:16</th></tr></tbody></table> <h2 id="eax80000008h-virtual-and-physical-address-sizes">EAX=8000'0008h: Virtual and Physical Address Sizes</h2> CPUID EAX=8000'0008h: Feature bits in EBX<table><tbody><tr><th rowspan="2">Bit</th><th colspan="2">EBX</th></tr><tr><th>Short</th><th>Feature</th></tr><tr><th>0</th><td>clzero</td><td>CLZERO instruction</td></tr><tr><th>1</th><td>retired_instr</td><td>Retired instruction count MSR (C000_00E9h) supported</td></tr><tr><th>2</th><td>xrstor_fp_err</td><td>XRSTOR restores FP errors</td></tr><tr><th>3</th><td>invlpgb</td><td>INVLPGB and TLBSYNC instructions</td></tr><tr><th>4</th><td>rdpru</td><td>RDPRU instruction</td></tr><tr><th>5</th><td></td><td>(<a href="/facts/Playstation_5/vJ2ahUoK">PS5</a> "xotext" / Execute-Only Memory)<a class="footnote-ref" id="fnref:247" href="#fn:247"><sup>247</sup></a><a class="footnote-ref" id="fnref:248" href="#fn:248"><sup>248</sup></a></td></tr><tr><th>6</th><td>mbe</td><td>Memory Bandwidth Enforcement</td></tr><tr><th>7</th><td colspan="2"><i>(reserved)</i><a class="footnote-ref" id="fnref:249" href="#fn:249"><sup>249</sup></a></td></tr><tr><th>8</th><td>mcommit</td><td>MCOMMIT instruction</td></tr><tr><th>9</th><td>wbnoinvd</td><td>WBNOINVD instruction</td></tr><tr><th>10</th><td colspan="2"><i>(reserved)</i></td></tr><tr><th>11</th><td colspan="2"><i>(reserved)</i><a class="footnote-ref" id="fnref:250" href="#fn:250"><sup>250</sup></a></td></tr><tr><th>12</th><td>IBPB</td><td>Indirect Branch Prediction Barrier (performed by writing 1 to bit 0 of PRED_CMD (MSR 049h))</td></tr><tr><th>13</th><td>wbinvd_int</td><td>WBINVD and WBNOINVD are interruptible</td></tr><tr><th>14</th><td>IBRS</td><td>Indirect Branch Restricted Speculation</td></tr><tr><th>15</th><td>STIBP</td><td>Single Thread Indirect Branch Prediction mode</td></tr><tr><th>16</th><td>IbrsAlwaysOn</td><td>IBRS mode has enhanced performance and should be left always on</td></tr><tr><th>17</th><td>StibpAlwaysOn</td><td>STIBP mode has enhanced performance and should be left always on</td></tr><tr><th>18</th><td>ibrs_preferred</td><td>IBRS preferred over software</td></tr><tr><th>19</th><td>ibrs_same_mode_protection</td><td>IBRS provides Same Mode Protection</td></tr><tr><th>20</th><td>no_efer_lmsle</td><td>EFER.LMSLE is unsupported<a class="footnote-ref" id="fnref:251" href="#fn:251"><sup>251</sup></a></td></tr><tr><th>21</th><td>invlpgb_nested</td><td>INVLPGB support for nested pages</td></tr><tr><th>22</th><td colspan="2"><i>(reserved)</i></td></tr><tr><th>23</th><td>ppin</td><td>Protected Processor Inventory Number -<p>PPIN_CTL (C001_02F0) and PPIN (C001_02F1) MSRs are present<a class="footnote-ref" id="fnref:252" href="#fn:252"><sup>252</sup></a></p></td></tr><tr><th>24</th><td>ssbd</td><td>Speculative Store Bypass Disable</td></tr><tr><th>25</th><td>ssbd_legacy</td><td>Speculative Store Bypass Disable Legacy</td></tr><tr><th>26</th><td>ssbd_no</td><td>Speculative Store Bypass Disable Not Required</td></tr><tr><th>27</th><td>cppc</td><td>Collaborative Processor Performance Control</td></tr><tr><th>28</th><td>psfd</td><td>Predictive Store Forward Disable</td></tr><tr><th>29</th><td>btc_no</td><td>Branch Type Confusion: Processor not affected</td></tr><tr><th>30</th><td>IBPB_RET</td><td>IBPB (see bit 12) also clears return address predictor</td></tr><tr><th>31</th><td>branch_sampling</td><td>Branch Sampling Support<a class="footnote-ref" id="fnref:253" href="#fn:253"><sup>253</sup></a></td></tr></tbody></table> CPUID EAX=8000'0008h: Size and range fields in EAX, ECX, EDX<table><tbody><tr><th>Bits</th><th>EAX</th><th scope="col" rowspan="7"></th><th>ECX</th><th scope="col" rowspan="7"></th><th>EDX</th><th>Bits</th></tr><tr><th>7:0</th><td>Number of Physical Address Bits</td><td>Number of Physical Threads in processor (minus 1)</td><td rowspan="3">Maximum page count for INVLPGB instruction</td><th>7:0</th></tr><tr><th>11:8</th><td rowspan="2">Number of Linear Address Bits</td><td><i>(reserved)</i></td><th>11:8</th></tr><tr><th>15:12</th><td>APIC ID Size</td><th>15:12</th></tr><tr><th>17:16</th><td rowspan="2">Guest Physical Address Size<a class="footnote-ref" id="fnref:254" href="#fn:254"><sup>254</sup></a></td><td>Performance Timestamp Counter size</td><td rowspan="3">Maximum ECX value recognized by RDPRU instruction</td><th>17:16</th></tr><tr><th>23:18</th><td rowspan="2"><i>(reserved)</i></td><th>23:18</th></tr><tr><th>31:24</th><td><i>(reserved)</i></td><th>31:24</th></tr></tbody></table> <h2 id="eax8000000ah-svm-features">EAX=8000'000Ah: SVM features</h2> <p>This leaf returns information about AMD SVM (<a href="/facts/Secure_Virtual_Machine/utQwmdY3">Secure Virtual Machine</a>) features in EAX, EBX and EDX. </p> CPUID EAX=8000'000Ah: SVM information in EAX, EBX and ECX<table><tbody><tr><th>Bits</th><th>EAX</th><th scope="col" rowspan="4"></th><th>EBX</th><th scope="col" rowspan="4"></th><th>ECX</th><th>Bits</th></tr><tr><th>7:0</th><td>SVM Revision Number</td><td rowspan="3">Number of available ASIDs (address space identifiers)</td><td rowspan="3"><i>(reserved)</i></td><th>7:0</th></tr><tr><th>8</th><td><i>(hypervisor)</i><a class="footnote-ref" id="fnref:255" href="#fn:255"><sup>255</sup></a></td><th>8</th></tr><tr><th>31:9</th><td><i>(reserved)</i></td><th>31:9</th></tr></tbody></table> CPUID EAX=8000'000Ah: SVM feature flags in EDX<table><tbody><tr><th rowspan="2">Bit</th><th colspan="2">EDX</th></tr><tr><th>Short</th><th>Feature</th></tr><tr><th>0</th><td>NP</td><td>Rapid Virtualization Indexing (<a href="/facts/Second_Level_Address_Translation/WY0j2dRv">Nested Paging</a>)</td></tr><tr><th>1</th><td>LbrVirt</td><td>LBR (Last Branch Records) virtualization</td></tr><tr><th>2</th><td>SVML</td><td>SVM-Lock</td></tr><tr><th>3</th><td>NRIPS</td><td>nRIP (next sequential instruction pointer) save on #VMEXIT supported</td></tr><tr><th>4</th><td>TscRateMsr</td><td>MSR-based <a href="/facts/Time_Stamp_Counter/THy8g17s">TSC</a> rate control (MSR C000_0104h)</td></tr><tr><th>5</th><td>VmcbClean</td><td>VMCB (Virtual Machine Control Block) clean bits supported</td></tr><tr><th>6</th><td>FlushByAsid</td><td><a href="/facts/Translation_lookaside_buffer/vvwGkfvD">TLB</a> flush events (e.g. <a href="/facts/Control_register/9VGRHh3f">CR3</a> writes, <a href="/facts/Control_Register/9VGRHh3f">CR4.PGE</a> toggles) only flush the TLB entries of the current ASID (address space ID)</td></tr><tr><th>7</th><td>DecodeAssist</td><td>Decode assists supported</td></tr><tr><th>8</th><td>PmcVirt</td><td>PMC (Performance Monitoring Counters) virtualization</td></tr><tr><th>9</th><td><i>(SseIsa10Compat)</i><a class="footnote-ref" id="fnref:256" href="#fn:256"><sup>256</sup></a></td><td><i>(reserved)</i></td></tr><tr><th>10</th><td>PauseFilter</td><td>PAUSE intercept filter supported</td></tr><tr><th>11</th><td colspan="2"><i>(reserved)</i></td></tr><tr><th>12</th><td>PauseFilterThreshold</td><td>PAUSE filter cycle count threshold supported</td></tr><tr><th>13</th><td>AVIC</td><td>AMD Advanced Virtualized Interrupt Controller supported</td></tr><tr><th>14</th><td colspan="2"><i>(reserved)</i></td></tr><tr><th>15</th><td>VMSAVEvirt</td><td>VMSAVE and VMLOAD virtualization</td></tr><tr><th>16</th><td>VGIF</td><td>Global Interrupt Flag (GIF) virtualization</td></tr><tr><th>17</th><td>GMET</td><td>Guest Mode Execution Trap</td></tr><tr><th>18</th><td>x2AVIC</td><td>x2APIC mode supported for AVIC</td></tr><tr><th>19</th><td>SSSCheck</td><td>SVM Supervisor <a href="/facts/Shadow_stack/mnQMEvou">shadow stack</a> restrictions</td></tr><tr><th>20</th><td>SpecCtrl</td><td>SPEC_CTRL (MSR 2E0h) virtualization</td></tr><tr><th>21</th><td>ROGPT</td><td>Read-Only Guest Page Table supported</td></tr><tr><th>22</th><td colspan="2"><i>(reserved)</i></td></tr><tr><th>23</th><td>HOST_MCE_OVERRIDE</td><td>Guest mode <a href="/facts/Machine-check_exception/8aLxkI6W">Machine-check exceptions</a> when host <a href="/facts/Control_register/9VGRHh3f">CR4.MCE</a>=1 and guest CR4.MCE=0 cause intercepts instead of shutdowns</td></tr><tr><th>24</th><td>TlbiCtl</td><td>INVLPGB/TLBSYNC hypervisor enable in VMCB and TLBSYNC intercept support</td></tr><tr><th>25</th><td>VNMI</td><td>NMI (<a href="/facts/Non-Maskable_interrupt/f7CWJU1B">Non-Maskable interrupt</a>) virtualization</td></tr><tr><th>26</th><td>IbsVirt</td><td>IBS (Instruction-Based Sampling) virtualization</td></tr><tr><th>27</th><td>ExtLvtOffsetFaultChg</td><td>Read/Write fault behavior for extended LVT offsets (APIC addresses 0x500-0x530) changed to Read Allowed, Write #VMEXIT<a class="footnote-ref" id="fnref:257" href="#fn:257"><sup>257</sup></a></td></tr><tr><th>28</th><td>VmcbAddrChkChg</td><td>VMCB address check change<a class="footnote-ref" id="fnref:258" href="#fn:258"><sup>258</sup></a></td></tr><tr><th>29</th><td>BusLockThreshold</td><td>Bus Lock Threshold</td></tr><tr><th>30</th><td>IdleHltIntercept</td><td>Idle HLT (HLT instruction executed while no virtual interrupt is pending) intercept</td></tr><tr><th>31</th><td>EnhancedShutdownIntercept</td><td>Support for EXITINFO1 on shutdown intercept, and nested shutdown intercepts will result in a non-interceptible shutdown.<a class="footnote-ref" id="fnref:259" href="#fn:259"><sup>259</sup></a></td></tr></tbody></table> <h2 id="eax8000001fh-encrypted-memory-capabilities">EAX=8000'001Fh: Encrypted Memory Capabilities</h2> CPUID EAX=8000'001Fh: Encrypted Memory feature bits in EAX<table><tbody><tr><th rowspan="2">Bit</th><th colspan="2">EAX</th></tr><tr><th>Short</th><th>Feature</th></tr><tr><th>0</th><td>SME</td><td>Secure Memory Encryption</td></tr><tr><th>1</th><td>SEV</td><td>Secure Encrypted Virtualization</td></tr><tr><th>2</th><td>PageFlushMSR</td><td>Page flush MSR (C001_011Eh) supported</td></tr><tr><th>3</th><td>SEV-ES</td><td>SEV Encrypted State</td></tr><tr><th>4</th><td>SEV-SNP</td><td>SEV Secure Nested Paging</td></tr><tr><th>5</th><td>VMPL</td><td>VM Privilege Levels</td></tr><tr><th>6</th><td>RMPQUERY</td><td>RMPQUERY instruction supported</td></tr><tr><th>7</th><td>VmplSSS</td><td>VMPL Supervisor <a href="/facts/Shadow_stack/mnQMEvou">shadow stack</a> supported</td></tr><tr><th>8</th><td>SecureTSC</td><td>Secure <a href="/facts/Time_Stamp_Counter/THy8g17s">TSC</a> supported</td></tr><tr><th>9</th><td>TscAuxVirtualization</td><td>Virtualization of TSC_AUX MSR (C000_0103) supported</td></tr><tr><th>10</th><td>HwEnfCacheCoh</td><td>Hardware cache coherency across encryption domains enforced</td></tr><tr><th>11</th><td>64BitHost</td><td>SEV Guest execution only allowed from 64-bit host</td></tr><tr><th>12</th><td>RestrictedInjection</td><td>SEV-ES guests can refuse all event-injections except #HV (Hypervisor Injection Exception)</td></tr><tr><th>13</th><td>AlternateInjection</td><td>SEV-ES guests can use an encrypted VMCB field for event-injection</td></tr><tr><th>14</th><td>DebugVirt</td><td>Full debug state virtualization supported for SEV-ES and SEV-SNP guests</td></tr><tr><th>15</th><td>PreventHostIBS</td><td>Prevent host IBS for a SEV-ES guest</td></tr><tr><th>16</th><td>VTE</td><td>Virtual Transparent Encryption for SEV</td></tr><tr><th>17</th><td>VmgexitParameter</td><td>VMGEXIT parameter is supported (using the RAX register)</td></tr><tr><th>18</th><td>VirtualTomMsr</td><td>Virtual TOM (top-of-memory) MSR (C001_0135) supported</td></tr><tr><th>19</th><td>IbsVirtGuestCtl</td><td>IBS virtualization is supported for SEV-ES and SEV-SNP guests</td></tr><tr><th>20</th><td>PmcVirtGuestCtl</td><td>PMC virtualization is supported for SEV-ES and SEV-SNP guests</td></tr><tr><th>21</th><td>RMPREAD</td><td>RMPREAD instruction supported</td></tr><tr><th>22</th><td>GuestInterceptControl</td><td>Guest Intercept control supported for SEV-ES guests</td></tr><tr><th>23</th><td>SegmentedRmp</td><td>Segmented RMP (Reverse-Map Table) supported</td></tr><tr><th>24</th><td>VmsaRegProt</td><td>VMSA (VM Save Area) register protection supported</td></tr><tr><th>25</th><td>SmtProtection</td><td><a href="/facts/Simultaneous_multithreading/bk8ec9yn">SMT</a> Protection supported</td></tr><tr><th>26</th><td>SecureAvic</td><td>Secure AVIC supported</td></tr><tr><th>27</th><td>AllowedSEVfeatures</td><td>ALLOWED_SEV_FEATURES_MASK field in VMCB (offset 138h) supported</td></tr><tr><th>28</th><td>SVSMCommPageMSR</td><td>SVSM (Secure VM Service Module<a class="footnote-ref" id="fnref:260" href="#fn:260"><sup>260</sup></a>) communication page MSR (C001_F000h) supported</td></tr><tr><th>29</th><td>NestedVirtSnpMsr</td><td>VIRT_RMPUPDATE (C001_F001h) and VIRT_PSMASH (C001_F002h) MSRs supported</td></tr><tr><th>30</th><td>HvInUseWrAllowed</td><td>Writes to Hypervisor-owned paged allowed when marked in-use</td></tr><tr><th>31</th><td>IbpbOnEntry</td><td>IBPB on entry to virtual machine supported</td></tr></tbody></table> CPUID EAX=8000'001Fh: Encrypted Memory feature information in EBX, ECX and EDX<table><tbody><tr><th>Bits</th><th>EBX</th><th>ECX</th><th>EDX</th><th>Bits</th></tr><tr><th>5:0</th><td>C-bit (encryption enable bit) location in page table entry</td><td rowspan="4">Maximum ASID value that can be used for a SEV-enabled guest (maximum number of encrypted guests that can be supported simultaneously)</td><td rowspan="4">Minimum ASID value for a guest that is SEV-enabled but not SEV-ES-enabled</td><th>5:0</th></tr><tr><th>11:6</th><td>Physical address width reduction when memory encryption is enabled</td><th>11:6</th></tr><tr><th>15:12</th><td>Number of VMPLs (VM Privilege Levels) supported</td><th>15:12</th></tr><tr><th>31:16</th><td><i>(reserved)</i></td><th>31:16</th></tr></tbody></table> <h2 id="eax80000021h-extended-feature-identification">EAX=8000'0021h: Extended Feature Identification</h2> CPUID EAX=8000'0021h: Extended feature bits in EAX<table><tbody><tr><th rowspan="2">Bit</th><th colspan="2">EAX</th></tr><tr><th>Short</th><th>Feature</th></tr><tr><th>0</th><td>NoNestedDataBp</td><td>Processor ignores nested data breakpoints</td></tr><tr><th>1</th><td>FsGsKernelGsBaseNonSerializing</td><td>WRMSR to the FS_BASE, GS_BASE and KernelGSBase MSRs is non-serializing<a class="footnote-ref" id="fnref:261" href="#fn:261"><sup>261</sup></a></td></tr><tr><th>2</th><td>LFenceAlwaysSerializing</td><td>LFENCE is always dispatch serializing</td></tr><tr><th>3</th><td>SmmPgCfgLock</td><td>SMM paging configuration lock supported</td></tr><tr><th>4</th><td colspan="2"><i>(reserved)</i></td></tr><tr><th>5</th><td colspan="2"><i>(reserved)</i></td></tr><tr><th>6</th><td>NullSelectClearsBase</td><td>Null segment selector loads also clear the destination segment register base and limit</td></tr><tr><th>7</th><td>UpperAddressIgnore</td><td>Upper Address Ignore is supported</td></tr><tr><th>8</th><td>AutomaticIBRS</td><td>Automatic IBRS</td></tr><tr><th>9</th><td>NoSmmCtlMSR</td><td>SMM_CTL MSR (C0010116h) is not supported</td></tr><tr><th>10</th><td>FSRS</td><td>Fast short REP STOSB supported</td></tr><tr><th>11</th><td>FSRC</td><td>Fast short REPE CMPSB supported</td></tr><tr><th>12</th><td>PMC2PreciseRetire</td><td>PreciseRetire performance counter control bit (MSR C0010002h bit 43) supported<a class="footnote-ref" id="fnref:262" href="#fn:262"><sup>262</sup></a></td></tr><tr><th>13</th><td>PrefetchCtlMsr</td><td>PrefetchControl MSR (C0000108h) is supported</td></tr><tr><th>14</th><td>L2TlbSIzeX32</td><td>If set, L2 TLB sizes (leaf 80000006h) are encoded as multiples of 32</td></tr><tr><th>15</th><td>AMD_ERMSB</td><td>Processor supports AMD implementation of Enhanced REP MOVSB and REP STOSB</td></tr><tr><th>16</th><td>OPCODE_0F017_RECLAIM</td><td>Reserves opcode 0F 01 /7 for AMD use, returning #UD.<a class="footnote-ref" id="fnref:263" href="#fn:263"><sup>263</sup></a></td></tr><tr><th>17</th><td>CpuidUserDis</td><td>CPUID disable for non-privileged software (#GP)</td></tr><tr><th>18</th><td>EPSF</td><td>Enhanced Predictive Store Forwarding supported<a class="footnote-ref" id="fnref:264" href="#fn:264"><sup>264</sup></a></td></tr><tr><th>19</th><td>FAST_REP_SCASB</td><td>Fast Short REP SCASB supported</td></tr><tr><th>20</th><td>PREFETCHI</td><td>Instruction Cache prefetch instructions supported</td></tr><tr><th>21</th><td>FP512_DOWNGRADE</td><td>Downgrade of 512-bit datapath to 256-bit supported.<a class="footnote-ref" id="fnref:265" href="#fn:265"><sup>265</sup></a></td></tr><tr><th>22</th><td>WL_CLASS_SUPPORT</td><td>Support for workload-based heuristic feedback to OS for scheduling decisions</td></tr><tr><th>23</th><td colspan="2"><i>(reserved)</i></td></tr><tr><th>24</th><td>ERAPS</td><td>Enhanced Return Address Predictor Security (see also EBX[23:16] "RapSize")</td></tr><tr><th>25</th><td colspan="2"><i>(reserved)</i></td></tr><tr><th>26</th><td colspan="2"><i>(reserved)</i></td></tr><tr><th>27</th><td>SBPB</td><td>Selective Branch Predictor Barrier supported<a class="footnote-ref" id="fnref:266" href="#fn:266"><sup>266</sup></a></td></tr><tr><th>28</th><td>IBPB_BRTYPE</td><td>IBPB flushes all branch type predictions<a class="footnote-ref" id="fnref:267" href="#fn:267"><sup>267</sup></a></td></tr><tr><th>29</th><td>SRSO_NO</td><td>CPU is not subject to SRSO (Speculative Return Stack Overflow) vulnerability<a class="footnote-ref" id="fnref:268" href="#fn:268"><sup>268</sup></a></td></tr><tr><th>30</th><td>SRSO_USER_KERNEL_NO</td><td>CPU is not subject to SRSO vulnerability across user/kernel boundary<a class="footnote-ref" id="fnref:269" href="#fn:269"><sup>269</sup></a></td></tr><tr><th>31</th><td>SRSO_MSR_FIX</td><td>SRSO can be mitigated by setting bit 4 of BP_CFG (MSR C001_102E)<a class="footnote-ref" id="fnref:270" href="#fn:270"><sup>270</sup></a></td></tr></tbody></table> CPUID EAX=8000'0021h: Extended feature information in EBX<table><tbody><tr><th rowspan="2">Bit</th><th colspan="2">EBX</th></tr><tr><th>Short</th><th>Feature</th></tr><tr><th>15:0</th><td>MicrocodePatchSize</td><td>The size of the Microcode patch in 16-byte multiples. If 0, the size of the patch is at most 5568 (15C0h) bytes</td></tr><tr><th>23:16</th><td>RapSize</td><td>Return Address Predictor Size.RapSize * 8 is the minimum number of CALL instructions without matching RET instructions that are needed to flush the Return Address Predictor.</td></tr><tr><th>31:24</th><td colspan="2"><i>(reserved)</i></td></tr></tbody></table> <h2 id="eax8fffffffh-amd-easter-egg">EAX=8FFF'FFFFh: AMD Easter Egg</h2> <p>Several AMD CPU models will, for CPUID with EAX=8FFFFFFFh, return an Easter Egg string in EAX, EBX, ECX and EDX.<a class="footnote-ref" id="fnref:271" href="#fn:271"><sup>271</sup></a><a class="footnote-ref" id="fnref:272" href="#fn:272"><sup>272</sup></a> Known Easter Egg strings include: </p> <table><tbody><tr><th>Processor</th><th>String</th></tr><tr><td><a href="/facts/AMD_K6/VSDY3GcM">AMD K6</a></td><td><a href="/facts/NexGen/7WWCsBnP">NexGen</a>erationAMD</td></tr><tr><td><a href="/facts/AMD_K8/31Fh4soT">AMD K8</a></td><td>IT'S <a href="/facts/U_Can%2527t_Touch_This/hQWzNuXK">HAMMER TIME</a></td></tr><tr><td><a href="/facts/Jaguar_(microarchitecture)/PkCbNj9a">AMD Jaguar</a><a class="footnote-ref" id="fnref:273" href="#fn:273"><sup>273</sup></a></td><td><a href="/facts/Hello_Kitty/GwKzPCzs">HELLO KITTY</a>! ^-^</td></tr></tbody></table> <h2 id="eaxc0000000h-highest-centaurextended-function">EAX=C000'0000h: Highest <a href="/facts/Centaur_Technology/blY0qw55">Centaur</a> Extended Function</h2> <p>Returns index of highest Centaur leaf in EAX. If the returned value in EAX is less than C0000001h, then Centaur extended leaves are not supported. </p><p>Present in CPUs from <a href="/facts/VIA_Technologies/g6REHNFE">VIA</a> and <a href="/facts/Zhaoxin/2wpVktlp">Zhaoxin</a>. </p><p>On IDT <a href="/facts/WinChip/mslaY86X">WinChip</a> CPUs (CentaurHauls Family 5), the extended leaves C0000001h-C0000005h do not encode any Centaur-specific functionality but are instead aliases of leaves 80000001h-80000005h.<a class="footnote-ref" id="fnref:274" href="#fn:274"><sup>274</sup></a> </p> <h2 id="eaxc0000001h-centaur-feature-information">EAX=C000'0001h: Centaur Feature Information</h2> <p>This leaf returns Centaur feature information (mainly <a href="/facts/VIA_PadLock/g6REHNFE">VIA/Zhaoxin PadLock</a>) in EDX.<a class="footnote-ref" id="fnref:275" href="#fn:275"><sup>275</sup></a><a class="footnote-ref" id="fnref:276" href="#fn:276"><sup>276</sup></a><a class="footnote-ref" id="fnref:277" href="#fn:277"><sup>277</sup></a><a class="footnote-ref" id="fnref:278" href="#fn:278"><sup>278</sup></a> (EAX, EBX and ECX are reserved.) </p> CPUID EAX=C000'0001h: Centaur feature bits in EDX<table><tbody><tr><th rowspan="2">Bit</th><th colspan="2">EDX</th></tr><tr><th>Short</th><th>Feature</th></tr><tr><th>0</th><td>sm2<a class="footnote-ref" id="fnref:279" href="#fn:279"><sup>279</sup></a></td><td>GMI <a href="/facts/SM9_(cryptography_standard)/5QkNunda">SM2</a> instruction present</td></tr><tr><th>1</th><td>sm2_en<a class="footnote-ref" id="fnref:280" href="#fn:280"><sup>280</sup></a></td><td>SM2 enabled</td></tr><tr><th>2</th><td>rng</td><td>PadLock <a href="/facts/Random_number_generation/RtXEfbzd">RNG</a> present: XSTORE and REP XSTORE instructions</td></tr><tr><th>3</th><td>rng_en</td><td>RNG enabled</td></tr><tr><th>4</th><td>ccs<a class="footnote-ref" id="fnref:281" href="#fn:281"><sup>281</sup></a></td><td>GMI <a href="/facts/SM3_(hash_function)/pdIyJ5jN">SM3</a>/<a href="/facts/SM4_(cipher)/05jCyaFf">SM4</a> instructions present: CCS_HASH and CCS_ENCRYPT</td></tr><tr><th>5</th><td>ccs_en<a class="footnote-ref" id="fnref:282" href="#fn:282"><sup>282</sup></a></td><td>SM3/SM4 instructions enabled</td></tr><tr><th>6</th><td>xcrypt</td><td>PadLock Advanced Cryptographic Engine (ACE, using <a href="/facts/Advanced_Encryption_Standard/HdXGBY2Q">AES</a> cipher) present: REP XCRYPT(ECB,CBC,CFB,OFB) instructions</td></tr><tr><th>7</th><td>xcrypt_en</td><td>ACE enabled</td></tr><tr><th>8</th><td>ace2</td><td>ACE v2 present: REP XCRYPTCTR instruction, as well as support for digest mode and misaligned data for ACE's REP XCRYPT* instructions.</td></tr><tr><th>9</th><td>ace2_en</td><td>ACE v2 enabled</td></tr><tr><th>10</th><td>phe</td><td>PadLock Hash Engine (PHE): REP XSHA1 and REP XSHA256 instructions</td></tr><tr><th>11</th><td>phe_en</td><td>PHE enabled</td></tr><tr><th>12</th><td>pmm</td><td>PadLock <a href="/facts/Montgomery_modular_multiplication/C1UyVrKJ">Montgomery Multiplier</a> (PMM): REP MONTMUL instruction</td></tr><tr><th>13</th><td>pmm_en</td><td>PMM enabled</td></tr><tr><th>14</th><td colspan="2"><i>(reserved)</i></td></tr><tr><th>15</th><td>zx_fma</td><td>FMA supported</td></tr><tr><th>16</th><td>parallax</td><td>Adaptive <a href="/facts/ACPI/GnLLzfyr">P-state</a> control present</td></tr><tr><th>17</th><td>parallax_en</td><td>Adaptive P-state control enabled</td></tr><tr><th>18</th><td>overstress</td><td>Overstress feature for auto overclock present</td></tr><tr><th>19</th><td>overstress_en</td><td>Overstress feature for auto overclock enabled</td></tr><tr><th>20</th><td>tm3</td><td>Thermal Monitor 3 present</td></tr><tr><th>21</th><td>tm3_en</td><td>Thermal Monitor 3 enabled</td></tr><tr><th>22</th><td>rng2</td><td>RNG v2 - second generation RNG present: REP XRNG2 instruction</td></tr><tr><th>23</th><td>rng2_en</td><td>RNG v2 enabled</td></tr><tr><th>24</th><td>sem</td><td>SME feature present</td></tr><tr><th>25</th><td>phe2</td><td>PHE v2: SHA384 and SHA512 present</td></tr><tr><th>26</th><td>phe2_en</td><td>PHE v2 enabled</td></tr><tr><th>27</th><td>xmodx</td><td>RSA instructions present: XMODEXP and MONTMUL2 instructions</td></tr><tr><th>28</th><td>xmodx_en</td><td>RSA instructions enabled</td></tr><tr><th>29</th><td>vex</td><td>VEX instructions present</td></tr><tr><th>30</th><td>vex_en</td><td>VEX instructions enabled</td></tr><tr><th>31</th><td>stk</td><td>STK is present</td></tr></tbody></table> <h2 id="cpuid-usage-from-high-level-languages">CPUID usage from high-level languages</h2> <h3>Inline assembly</h3> <p>This information is easy to access from other languages as well. For instance, the C code for gcc below prints the first five values, returned by the cpuid: </p> #include <stdio.h> #include <cpuid.h> int main() { unsigned int i, eax, ebx, ecx, edx; for (i = 0; i < 5; i++) { __cpuid(i, eax, ebx, ecx, edx); printf ("InfoType %x\nEAX: %x\nEBX: %x\nECX: %x\nEDX: %x\n", i, eax, ebx, ecx, edx); } return 0; } <p>In MSVC and Borland/Embarcadero C compilers (bcc32) flavored inline assembly, the clobbering information is implicit in the instructions: </p> #include <stdio.h> int main() { unsigned int a, b, c, d, i = 0; __asm { /* Do the call. */ mov EAX, i; cpuid; /* Save results. */ mov a, EAX; mov b, EBX; mov c, ECX; mov d, EDX; } printf ("InfoType %x\nEAX: %x\nEBX: %x\nECX: %x\nEDX: %x\n", i, a, b, c, d); return 0; } <p>If either version was written in plain assembly language, the programmer must manually save the results of EAX, EBX, ECX, and EDX elsewhere if they want to keep using the values. </p> <h3>Wrapper functions</h3> <p>GCC also provides a header called <cpuid.h> on systems that have CPUID. The __cpuid is a macro expanding to inline assembly. Typical usage would be: </p> #include <stdio.h> #include <cpuid.h> int main() { unsigned int eax, ebx, ecx, edx; __cpuid(0 /* vendor string */, eax, ebx, ecx, edx); printf("EAX: %x\nEBX: %x\nECX: %x\nEDX: %x\n", eax, ebx, ecx, edx); return 0; } <p>But if one requested an extended feature not present on this CPU, they would not notice and might get random, unexpected results. Safer version is also provided in <cpuid.h>. It checks for extended features and does some more safety checks. The output values are not passed using reference-like macro parameters, but more conventional pointers. </p> #include <stdio.h> #include <cpuid.h> int main() { unsigned int eax, ebx, ecx, edx; /* 0x81234567 is nonexistent, but assume it exists */ if (!__get_cpuid (0x81234567, &eax, &ebx, &ecx, &edx)) { printf("Warning: CPUID request 0x81234567 not valid!\n"); return 1; } printf("EAX: %x\nEBX: %x\nECX: %x\nEDX: %x\n", eax, ebx, ecx, edx); return 0; } <p>Notice the ampersands in &a, &b, &c, &d and the conditional statement. If the __get_cpuid call receives a correct request, it will return a non-zero value, if it fails, zero.<a class="footnote-ref" id="fnref:283" href="#fn:283"><sup>283</sup></a> </p><p>Microsoft Visual C compiler has builtin function __cpuid() so the cpuid instruction may be embedded without using inline assembly, which is handy since the x86-64 version of MSVC does not allow inline assembly at all. The same program for <a href="/facts/MSVC/RM3sbYw5">MSVC</a> would be: </p> #include <stdio.h> #ifdef _MSC_VER #include <intrin.h> #endif int main() { unsigned int regs[4]; int i; for (i = 0; i < 4; i++) { __cpuid(regs, i); printf("The code %d gives %d, %d, %d, %d", regs[0], regs[1], regs[2], regs[3]); } return 0; } <p>Many interpreted or compiled scripting languages are capable of using CPUID via an <a href="/facts/Foreign_function_interface/ntAxkhK0">FFI</a> library. <a href="https://web.archive.org/web/20150429190703/http://www.cstrahan.com/posts/pure-ruby-cpuid-via-ffi.html">One such implementation</a> shows usage of the Ruby FFI module to execute assembly language that includes the CPUID opcode. </p> <p><a href="/facts/.NET/PDMQdfFu">.NET</a> 5 and later versions provide the System.Runtime.Intrinsics.X86.X86base.CpuId method. For instance, the C# code below prints the processor brand if it supports CPUID instruction:</p>using System.Runtime.InteropServices; using System.Runtime.Intrinsics.X86; using System.Text; namespace X86CPUID { class CPUBrandString { public static void Main(string[] args) { if (!X86Base.IsSupported) { Console.WriteLine("Your CPU does not support CPUID instruction."); } else { Span<int> raw = stackalloc int[12]; (raw[0], raw[1], raw[2], raw[3]) = X86Base.CpuId(unchecked((int)0x80000002), 0); (raw[4], raw[5], raw[6], raw[7]) = X86Base.CpuId(unchecked((int)0x80000003), 0); (raw[8], raw[9], raw[10], raw[11]) = X86Base.CpuId(unchecked((int)0x80000004), 0); Span<byte> bytes = MemoryMarshal.AsBytes(raw); string brand = Encoding.UTF8.GetString(bytes).Trim(); Console.WriteLine(brand); } } } } <h2 id="cpu-specific-information-outside-x86">CPU-specific information outside x86</h2> <p>Some of the non-x86 CPU architectures also provide certain forms of structured information about the processor's abilities, commonly as a set of special registers: </p> <ul><li><a href="/facts/ARM_architecture/SALsYA79">ARM architectures</a> have a CPUID coprocessor register which requires <a href="/facts/Protection_ring/27y4kjHs">exception level</a> EL1 or above to access.<a class="footnote-ref" id="fnref:284" href="#fn:284"><sup>284</sup></a></li> <li><a href="/facts/IBM_System%2f370/TRo1jaFw">System/370</a> through <a href="/facts/Z%2fArchitecture/FcKYkGn9">z/Architecture</a> IBM mainframe processors have a supervisor-mode-only <i>Store CPU ID</i> (STIDP) instruction, which provides information that includes the CPU type.<a class="footnote-ref" id="fnref:285" href="#fn:285"><sup>285</sup></a><a class="footnote-ref" id="fnref:286" href="#fn:286"><sup>286</sup></a>: 10-147–10-149 </li> <li>The z/Architecture mainframe processors also have a supervisor-mode-only <i>Store Facilities List</i> (STFL)<a class="footnote-ref" id="fnref:287" href="#fn:287"><sup>287</sup></a>: 10-149 instruction, and a non-privileged <i>Store Facilities List Extended</i> (STFLE) instruction: 7-394–7-395 , which list the installed hardware features.</li> <li>The <a href="/facts/MIPS_architecture/efV4KgK4">MIPS32/64</a> architecture defines a mandatory <i>Processor Identification</i> (PrId) and a series of daisy-chained <i>Configuration Registers</i>.<a class="footnote-ref" id="fnref:288" href="#fn:288"><sup>288</sup></a></li> <li>The <a href="/facts/PowerPC/DqmM9y50">PowerPC</a> processor has the 32-bit read-only <i>Processor Version Register</i> (PVR) identifying the processor model in use. The instruction requires supervisor access level.<a class="footnote-ref" id="fnref:289" href="#fn:289"><sup>289</sup></a></li> <li>The <a href="/facts/RISC-V/pUSKDat1">RISC-V</a> architecture has an mcpuid "read-only register containing information regarding the capabilities of the CPU implementation"<a class="footnote-ref" id="fnref:290" href="#fn:290"><sup>290</sup></a></li></ul> <p><a href="/facts/Digital_signal_processor/YuBXweos">DSP</a> and <a href="/facts/Transputer/V0ShkUhE">transputer</a>-like chip families have not taken up the instruction in any noticeable way, in spite of having (in relative terms) as many variations in design. Alternate ways of silicon identification might be present; for example, DSPs from <a href="/facts/Texas_Instruments/88NUhuHF">Texas Instruments</a> contain a memory-based register set for each functional unit that starts with identifiers determining the unit type and model, its <a href="/facts/ASIC/tEd61Jen">ASIC</a> design revision and features selected at the design phase, and continues with unit-specific control and data registers. Access to these areas is performed by simply using the existing load and store instructions; thus, for such devices, there is no need for extending the register set for device identification purposes. </p> <h2 id="see-also">See also</h2> <ul><li><a href="https://x86-cpuid.org/">x86-cpuid.org</a>, a complete x86 architecture CPUID database plus related code generation tools, to be used by both the <a href="/facts/Linux_kernel/dlkduHuA">Linux Kernel</a> and the <a href="/facts/Xen_hypervisor/U5fq6ESl">Xen hypervisor</a>. <a class="footnote-ref" id="fnref:291" href="#fn:291"><sup>291</sup></a></li> <li><a href="/facts/CPU-Z/vmpfFkJl">CPU-Z</a>, a Windows utility that uses CPUID to identify various system settings</li> <li><a href="https://thetumultuousunicornofdarkness.github.io/CPU-X/">CPU-X</a>, an alternative of CPU-Z for Linux and FreeBSD</li> <li><a href="/facts/Spectre_(security_vulnerability)/1PBIla24">Spectre (security vulnerability)</a></li> <li><a href="/facts/Speculative_Store_Bypass/foA66VXX">Speculative Store Bypass</a> (SSB)</li> <li><a href="/facts/Cpuinfo/qGd3Ncgz">/proc/cpuinfo</a>, a text file generated by certain systems containing some of the CPUID information</li></ul> <h2 id="further-reading">Further reading</h2> <ul><li><a href="https://developer.amd.com/wp-content/resources/Architecture_Guidelines_Update_Indirect_Branch_Control.pdf">"AMD64 Technology Indirect Branch Control Extension"</a> (PDF) (White paper). Revision 4.10.18. <a href="/facts/Advanced_Micro_Devices%2c_Inc./CB1G7QTb">Advanced Micro Devices, Inc.</a> (AMD). 2018. <a href="https://web.archive.org/web/20180509093400/https://developer.amd.com/wp-content/resources/Architecture_Guidelines_Update_Indirect_Branch_Control.pdf">Archived</a> (PDF) from the original on 2018-05-09. Retrieved 2018-05-09.</li></ul> <h2 id="external-links">External links</h2> <ul><li>Intel <a href="https://web.archive.org/web/20120625025623/http://www.intel.com/Assets/PDF/appnote/241618.pdf">Processor Identification and the CPUID Instruction</a> (Application Note 485), last published version. Said to be incorporated into the <a href="http://www.intel.com/Assets/PDF/appnote/241618.pdf">Intel 64 and IA-32 Architectures Software Developer's Manual</a> <a href="https://web.archive.org/web/20130626034554/http://www.intel.com/content/dam/www/public/us/en/documents/application-notes/processor-identification-cpuid-instruction-note.pdf">in 2013</a>, but as of July 2014 the manual still directs the reader to note 485. <ul><li>Contains some information that can be <i>and was</i> easily misinterpreted though, particularly with respect to processor topology identification.</li> <li>The big Intel manuals tend to lag behind the Intel ISA document, available at the top of <a href="https://software.intel.com/en-us/intel-isa-extensions">this page</a>, which is updated even for processors not yet publicly available, and thus usually contains more CPUID bits. For example, as of this writing, the ISA book (at revision 19, dated May 2014) documents the CLFLUSHOPT bit in leaf 7, but the big manuals although apparently more up-to-date (at revision 51, dated June 2014) don't mention it.</li></ul></li> <li><a href="https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24594.pdf">AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions</a></li> <li><a href="https://www.etallen.com/cpuid.html">cpuid</a> command-line program for Linux</li> <li><a href="https://skanthak.homepage.t-online.de/cpuid.html">cpuprint.com, cpuprint.exe, cpuprint.raw</a> command-line programs for Windows</li> <li><a href="http://users.atw.hu/instlatx64/">instlatx64</a> - collection of x86/x64 Instruction Latency, Memory Latency and CPUID dumps</li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>"Intel 64 and IA-32 Architectures Software Developer's Manual" (PDF). Intel.com. Retrieved 2013-04-11. <a href="http://www.intel.com/design/processor/manuals/253668.pdf" target="_blank">http://www.intel.com/design/processor/manuals/253668.pdf</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>"Detecting Intel Processors - Knowing the generation of a system CPU". Rcollins.org. Retrieved 2013-04-11. <a href="http://www.rcollins.org/ddj/Sep96/Sep96.html" target="_blank">http://www.rcollins.org/ddj/Sep96/Sep96.html</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>"LXR linux-old/arch/i386/kernel/head.S". Lxr.linux.no. Archived from the original on 2012-07-13. Retrieved 2013-04-11. <a href="https://archive.today/20120713012856/http://lxr.linux.no/source/arch/i386/kernel/head.S?v=1.2.13%23L92" target="_blank">https://archive.today/20120713012856/http://lxr.linux.no/source/arch/i386/kernel/head.S?v=1.2.13%23L92</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>Debbie Wiles, CPU Identification, archived on 2006-06-04 <a href="https://web.archive.org/web/20040604002243/http://debs.future.easyspace.com/Programming/OS/cpuid.txt" target="_blank">https://web.archive.org/web/20040604002243/http://debs.future.easyspace.com/Programming/OS/cpuid.txt</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>B-CoolWare, TMi0SDGL x86 CPU/FPU detection library with source code, v2.15, June 2000 - see /SOURCE/REALCODE.ASM for a large collection of pre-CPUID x86 CPU detection routines. Archived on 14 Mar 2023. <a href="https://www.sac.sk/download/utildiag/cpu215.zip" target="_blank">https://www.sac.sk/download/utildiag/cpu215.zip</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>"CPUID, EAX=4 - Strange results (Solved)". Software.intel.com. Retrieved 2014-07-10. <a href="https://software.intel.com/en-us/forums/topic/306523?language=en#comment-1590394" target="_blank">https://software.intel.com/en-us/forums/topic/306523?language=en#comment-1590394</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>@InstLatX64 (February 28, 2019). "First encounter with "GenuineIotel" (o after I, instead of n)" (Tweet) – via Twitter. <a href="https://x.com/InstLatX64/status/1101230794364862464" target="_blank">https://x.com/InstLatX64/status/1101230794364862464</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> <li id="fn:8"><p>"GenuineIotel CPUID dump for Intel Xeon E3-1231". instlatx64. <a href="http://users.atw.hu/instlatx64/GenuineIotel/GenuineIotel00306C3_Haswell_CPUID5.txt" target="_blank">http://users.atw.hu/instlatx64/GenuineIotel/GenuineIotel00306C3_Haswell_CPUID5.txt</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></p></li> <li id="fn:9"><p>instlatx64, CPUID dump for RDC IAD 100. Retrieved 22 December 2022. <a href="http://users.atw.hu/instlatx64/Genuine__RDC/Genuine%20%20RDC0000586_RDC_CPUID.txt" target="_blank">http://users.atw.hu/instlatx64/Genuine__RDC/Genuine%20%20RDC0000586_RDC_CPUID.txt</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></p></li> <li id="fn:10"><p>smxi, Inxi issue 197: Elbrus CPU support data and implementation. Retrieved 23 October 2023. Archived on 23 October 2023. <a href="https://codeberg.org/smxi/inxi/issues/197" target="_blank">https://codeberg.org/smxi/inxi/issues/197</a> <a href="#fnref:10" class="footnote-back-ref">↩</a></p></li> <li id="fn:11"><p>Grzegorz Mazur, Identification of x86 CPUs with CPUID support, 5 May 1997. Archived from the original on 24 May 1997. <a href="https://web.archive.org/web/19970524043213/http://grafi.ii.pw.edu.pl:80/gbm/x86/cpuid.html" target="_blank">https://web.archive.org/web/19970524043213/http://grafi.ii.pw.edu.pl:80/gbm/x86/cpuid.html</a> <a href="#fnref:11" class="footnote-back-ref">↩</a></p></li> <li id="fn:12"><p>Ingo Böttcher, CPUDET.PAS v1.61, 23 Oct 1996 - CPU identification program that tests for "AMD ISBETTER" string. Archived on 26 Apr 2024. <a href="https://groups.google.com/g/fido.ger.pascal/c/Hy8JY6JqO_o/m/0Xv22DWi6TAJ" target="_blank">https://groups.google.com/g/fido.ger.pascal/c/Hy8JY6JqO_o/m/0Xv22DWi6TAJ</a> <a href="#fnref:12" class="footnote-back-ref">↩</a></p></li> <li id="fn:13"><p>sorgelig (Aug 3, 2017). "ao486 CPUID instruction (in commit 43a2004)". GitHub. Archived from the original on 2023-12-04. Retrieved 2023-12-04. <a href="https://github.com/MiSTer-devel/ao486_MiSTer/blob/43a20047d5e2e99f1264dadbdab777733ccbb61a/rtl/ao486/commands/CMD_CPUID.txt" target="_blank">https://github.com/MiSTer-devel/ao486_MiSTer/blob/43a20047d5e2e99f1264dadbdab777733ccbb61a/rtl/ao486/commands/CMD_CPUID.txt</a> <a href="#fnref:13" class="footnote-back-ref">↩</a></p></li> <li id="fn:14"><p>sorgelig (Aug 30, 2020). "Update cpuid. · MiSTer-devel/ao486_MiSTer@82f5014". GitHub. Archived from the original on 2023-12-04. Retrieved 2023-12-04. <a href="https://github.com/MiSTer-devel/ao486_MiSTer/commit/82f5014bb44356e256a9c5454e8810d43a9990f1" target="_blank">https://github.com/MiSTer-devel/ao486_MiSTer/commit/82f5014bb44356e256a9c5454e8810d43a9990f1</a> <a href="#fnref:14" class="footnote-back-ref">↩</a></p></li> <li id="fn:15"><p>sorgelig (Aug 30, 2020). "ao486 CPUID instruction". GitHub. Archived from the original on October 23, 2023. Retrieved 4 Dec 2023. <a href="https://github.com/MiSTer-devel/ao486_MiSTer/blob/master/rtl/ao486/commands/CMD_CPUID.txt" target="_blank">https://github.com/MiSTer-devel/ao486_MiSTer/blob/master/rtl/ao486/commands/CMD_CPUID.txt</a> <a href="#fnref:15" class="footnote-back-ref">↩</a></p></li> <li id="fn:16"><p>sorgelig (Aug 30, 2020). "Update cpuid. · MiSTer-devel/ao486_MiSTer@82f5014". GitHub. Archived from the original on 2023-12-04. Retrieved 2023-12-04. <a href="https://github.com/MiSTer-devel/ao486_MiSTer/commit/82f5014bb44356e256a9c5454e8810d43a9990f1" target="_blank">https://github.com/MiSTer-devel/ao486_MiSTer/commit/82f5014bb44356e256a9c5454e8810d43a9990f1</a> <a href="#fnref:16" class="footnote-back-ref">↩</a></p></li> <li id="fn:17"><p>"v586: 586 compatible soft core for FPGA". GitHub. 6 December 2021. <a href="https://github.com/valptek/v586" target="_blank">https://github.com/valptek/v586</a> <a href="#fnref:17" class="footnote-back-ref">↩</a></p></li> <li id="fn:18"><p>"Steam Hardware & Software Survey". store.steampowered.com. Retrieved 2022-07-26. <a href="https://store.steampowered.com/hwsurvey/processormfg?sort=chg" target="_blank">https://store.steampowered.com/hwsurvey/processormfg?sort=chg</a> <a href="#fnref:18" class="footnote-back-ref">↩</a></p></li> <li id="fn:19"><p>"Fun with Timers and cpuid - by Jim Cownie - CPU fun". 3 March 2021. <a href="https://cpufun.substack.com/p/fun-with-timers-and-cpuid" target="_blank">https://cpufun.substack.com/p/fun-with-timers-and-cpuid</a> <a href="#fnref:19" class="footnote-back-ref">↩</a></p></li> <li id="fn:20"><p>virt-what source tree, tests/lx86/proc/cpuinfo - PowerVM Lx86 cpuinfo dump. Archived on 10 Nov 2024. <a href="http://git.annexia.org/?p=virt-what.git;a=blob;f=tests/lx86/proc/cpuinfo;h=9da5dca2c754ff95c6f3d3ef96da0e6fa24aeb34;hb=82c0e9c469953a36f18db1e329629cecd950134a" target="_blank">http://git.annexia.org/?p=virt-what.git;a=blob;f=tests/lx86/proc/cpuinfo;h=9da5dca2c754ff95c6f3d3ef96da0e6fa24aeb34;hb=82c0e9c469953a36f18db1e329629cecd950134a</a> <a href="#fnref:20" class="footnote-back-ref">↩</a></p></li> <li id="fn:21"><p>Neko Project 21/W, help/configure (in Japanese). Archived on 22 Sep 2024. <a href="https://simk98.github.io/np21w/help/cfgdlg.html" target="_blank">https://simk98.github.io/np21w/help/cfgdlg.html</a> <a href="#fnref:21" class="footnote-back-ref">↩</a></p></li> <li id="fn:22"><p>CPU-World, CPUID for emulated Neko Project CPU with "Neko Project" string. Archived on 21 Dec 2024. <a href="https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=82924" target="_blank">https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=82924</a> <a href="#fnref:22" class="footnote-back-ref">↩</a></p></li> <li id="fn:23"><p>iXBT Labs, VIA Nano CPUID Tricks, Aug 26, 2010. Archived on Aug 29, 2010. <a href="http://ixbtlabs.com/articles3/cpu/via-nano-cpuid-fake-p1.html" target="_blank">http://ixbtlabs.com/articles3/cpu/via-nano-cpuid-fake-p1.html</a> <a href="#fnref:23" class="footnote-back-ref">↩</a></p></li> <li id="fn:24"><p>IDT, WinChip 2A data sheet, v1.0, Jan 1999, page A-3. <a href="https://www.ardent-tool.com/CPU/docs/IDT_Centaur/WinChip2/wc_2_datasheet_a2.pdf" target="_blank">https://www.ardent-tool.com/CPU/docs/IDT_Centaur/WinChip2/wc_2_datasheet_a2.pdf</a> <a href="#fnref:24" class="footnote-back-ref">↩</a></p></li> <li id="fn:25"><p>VIA, C3 Nehemiah Datasheet, rev 1.13, Sep 29, 2004, page A-3. <a href="http://datasheets.chipdb.org/VIA/Nehemiah/VIA%20C3%20Nehemiah%20Datasheet%20R113.pdf" target="_blank">http://datasheets.chipdb.org/VIA/Nehemiah/VIA%20C3%20Nehemiah%20Datasheet%20R113.pdf</a> <a href="#fnref:25" class="footnote-back-ref">↩</a></p></li> <li id="fn:26"><p>Agner Fog, CpuIDFake, v1.00, Jan 22, 2010, see "Instructions.txt". Archived on Jul 9, 2010. <a href="http://www.agner.org/optimize/cpuidfake.zip" target="_blank">http://www.agner.org/optimize/cpuidfake.zip</a> <a href="#fnref:26" class="footnote-back-ref">↩</a></p></li> <li id="fn:27"><p>Transmeta, Crusoe BIOS Programmer's Guide, Jan 23, 2004, pages 63-65. <a href="http://datasheets.chipdb.org/Transmeta/Crusoe/TM5900/tm5900_bisoguide_040123.pdf" target="_blank">http://datasheets.chipdb.org/Transmeta/Crusoe/TM5900/tm5900_bisoguide_040123.pdf</a> <a href="#fnref:27" class="footnote-back-ref">↩</a></p></li> <li id="fn:28"><p>Transmeta, Efficeon BIOS Programmers Guide, Aug 19, 2003, section 8.3, page 148. <a href="#fnref:28" class="footnote-back-ref">↩</a></p></li> <li id="fn:29"><p>AMD, Geode LX Data Book, pub.id. 33234H, Feb. 2009, page 107. Archived on Dec 3, 2023. <a href="https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/datasheets/33234H_LX_databook.pdf" target="_blank">https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/datasheets/33234H_LX_databook.pdf</a> <a href="#fnref:29" class="footnote-back-ref">↩</a></p></li> <li id="fn:30"><p>DM&P, Vortex86EX2_A9133_Master_Data_Sheet_V11_BF, May 8, 2019, page 72. <a href="https://www.vortex86.com/downloads/Vortex86EX2" target="_blank">https://www.vortex86.com/downloads/Vortex86EX2</a> <a href="#fnref:30" class="footnote-back-ref">↩</a></p></li> <li id="fn:31"><p>"Chapter 3 Instruction Set Reference, A-L" (PDF). Intel 64 and IA-32 Architectures Software Developer's Manual. Intel Corporation. 2018-12-20. Retrieved 2018-12-20. <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4" target="_blank">https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4</a> <a href="#fnref:31" class="footnote-back-ref">↩</a></p></li> <li id="fn:32"><p>Intel, Pentium Processor Family Developer's Manual, 1997, order no. 241428-005, sections 3.4.1.2 (page 91), 17.5.1 (page 489) and appendix A (page 522) provide more detail on how the "processor type" field and the "dual processor" designation work. <a href="https://www.ardent-tool.com/CPU/docs/Intel/Pentium/241428-005.pdf" target="_blank">https://www.ardent-tool.com/CPU/docs/Intel/Pentium/241428-005.pdf</a> <a href="#fnref:32" class="footnote-back-ref">↩</a></p></li> <li id="fn:33"><p>InstLatx64, x86, x64 Instruction Latency, Memory Latency and CPUID dumps, 30 Sep 2023. <a href="http://users.atw.hu/instlatx64/" target="_blank">http://users.atw.hu/instlatx64/</a> <a href="#fnref:33" class="footnote-back-ref">↩</a></p></li> <li id="fn:34"><p>The i386 processor does not support the CPUID instruction - it does however return Family ID 3h in the reset-value of EDX. <a href="/wiki/I386" target="_blank">/wiki/I386</a> <a href="#fnref:34" class="footnote-back-ref">↩</a></p></li> <li id="fn:35"><p>AMD, Enhanced Am486DX Microprocessor Family, pub.no. 20736 rev B, March 1997, section 9.2.2, page 55. Archived on 18 Oct 2023. <a href="https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/datasheets/20736.pdf" target="_blank">https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/datasheets/20736.pdf</a> <a href="#fnref:35" class="footnote-back-ref">↩</a></p></li> <li id="fn:36"><p>AMD, ÉlanSC400 and ÉlanSC410 Microcontrollers User's Manual, pub.no. 21030, 1997, section 3.6.2, page 73. Archived on 18 Oct 2023. <a href="https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/user-guides/21030.pdf" target="_blank">https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/user-guides/21030.pdf</a> <a href="#fnref:36" class="footnote-back-ref">↩</a></p></li> <li id="fn:37"><p>Cyrix, 5x86 BIOS Writers Guide, rev 1.12, order no. 92426-00, 1995, page 7 <a href="http://www.bitsavers.org/components/cyrix/94246-00_5x86_CPU_BIOS_Writers_Guide_199510.pdf" target="_blank">http://www.bitsavers.org/components/cyrix/94246-00_5x86_CPU_BIOS_Writers_Guide_199510.pdf</a> <a href="#fnref:37" class="footnote-back-ref">↩</a></p></li> <li id="fn:38"><p>Cyrix, CPU Detection Guide, rev 1.01, 2 Oct 1997, page 6. <a href="http://www.bitsavers.org/components/cyrix/appnotes/Cyrix_CPU_Detection_Guide_1997.pdf" target="_blank">http://www.bitsavers.org/components/cyrix/appnotes/Cyrix_CPU_Detection_Guide_1997.pdf</a> <a href="#fnref:38" class="footnote-back-ref">↩</a></p></li> <li id="fn:39"><p>Debbie Wiles, CPU Identification, archived on 2006-06-04 <a href="https://web.archive.org/web/20040604002243/http://debs.future.easyspace.com/Programming/OS/cpuid.txt" target="_blank">https://web.archive.org/web/20040604002243/http://debs.future.easyspace.com/Programming/OS/cpuid.txt</a> <a href="#fnref:39" class="footnote-back-ref">↩</a></p></li> <li id="fn:40"><p>smxi, Inxi issue 197: Elbrus CPU support data and implementation. Retrieved 23 October 2023. Archived on 23 October 2023. <a href="https://codeberg.org/smxi/inxi/issues/197" target="_blank">https://codeberg.org/smxi/inxi/issues/197</a> <a href="#fnref:40" class="footnote-back-ref">↩</a></p></li> <li id="fn:41"><p>MiSTer ao486 source code, rtl/ao486/defines.v, line 70. Archived on 23 Oct 2023. <a href="https://github.com/MiSTer-devel/ao486_MiSTer/blob/43a20047d5e2e99f1264dadbdab777733ccbb61a/rtl/ao486/defines.v" target="_blank">https://github.com/MiSTer-devel/ao486_MiSTer/blob/43a20047d5e2e99f1264dadbdab777733ccbb61a/rtl/ao486/defines.v</a> <a href="#fnref:41" class="footnote-back-ref">↩</a></p></li> <li id="fn:42"><p>Cyrix, CPU Detection Guide, rev 1.01, 2 Oct 1997, page 6. <a href="http://www.bitsavers.org/components/cyrix/appnotes/Cyrix_CPU_Detection_Guide_1997.pdf" target="_blank">http://www.bitsavers.org/components/cyrix/appnotes/Cyrix_CPU_Detection_Guide_1997.pdf</a> <a href="#fnref:42" class="footnote-back-ref">↩</a></p></li> <li id="fn:43"><p>Debbie Wiles, CPU Identification, archived on 2006-06-04 <a href="https://web.archive.org/web/20040604002243/http://debs.future.easyspace.com/Programming/OS/cpuid.txt" target="_blank">https://web.archive.org/web/20040604002243/http://debs.future.easyspace.com/Programming/OS/cpuid.txt</a> <a href="#fnref:43" class="footnote-back-ref">↩</a></p></li> <li id="fn:44"><p>CPU-World, CPUID for Vortex86DX2 933 MHz. Archived on 17 Oct 2023. <a href="https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=66102" target="_blank">https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=66102</a> <a href="#fnref:44" class="footnote-back-ref">↩</a></p></li> <li id="fn:45"><p>smxi, Inxi issue 197: Elbrus CPU support data and implementation. Retrieved 23 October 2023. Archived on 23 October 2023. <a href="https://codeberg.org/smxi/inxi/issues/197" target="_blank">https://codeberg.org/smxi/inxi/issues/197</a> <a href="#fnref:45" class="footnote-back-ref">↩</a></p></li> <li id="fn:46"><p>CPU-World, CPUID for Vortex86EX2. Archived on 18 Oct 2023. <a href="https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=72324" target="_blank">https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=72324</a> <a href="#fnref:46" class="footnote-back-ref">↩</a></p></li> <li id="fn:47"><p>InstLatx64, Centaur CNS CPUID dump. Archived on 30 May 2023. <a href="http://users.atw.hu/instlatx64/CentaurHauls/CentaurHauls0040672_CNS_04_CPUID.txt" target="_blank">http://users.atw.hu/instlatx64/CentaurHauls/CentaurHauls0040672_CNS_04_CPUID.txt</a> <a href="#fnref:47" class="footnote-back-ref">↩</a></p></li> <li id="fn:48"><p>smxi, Inxi issue 197: Elbrus CPU support data and implementation. Retrieved 23 October 2023. Archived on 23 October 2023. <a href="https://codeberg.org/smxi/inxi/issues/197" target="_blank">https://codeberg.org/smxi/inxi/issues/197</a> <a href="#fnref:48" class="footnote-back-ref">↩</a></p></li> <li id="fn:49"><p>Family ID 8h has been reported to have been deliberately avoided for the Pentium 4 processor family due to incompatibility with Windows NT 4.0.[41] <a href="#fnref:49" class="footnote-back-ref">↩</a></p></li> <li id="fn:50"><p>Intel, Intel Xeon Phi Coprocessor Instruction Set Architecture Reference Manual, sep 2012, order no. 327364-001, appendix B.8, pages 673-674. Archived on 4 Aug 2021. <a href="https://www.intel.com/content/dam/develop/external/us/en/documents/327364001en.pdf" target="_blank">https://www.intel.com/content/dam/develop/external/us/en/documents/327364001en.pdf</a> <a href="#fnref:50" class="footnote-back-ref">↩</a></p></li> <li id="fn:51"><p>CPU-World, CPUID for Intel Itanium 2 1.50 GHz. Archived on 17 Oct 2023. <a href="https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=40724" target="_blank">https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=40724</a> <a href="#fnref:51" class="footnote-back-ref">↩</a></p></li> <li id="fn:52"><p>"[PATCH] x86/cpu: Add two Intel CPU model numbers - Tony Luck". lore.kernel.org. Retrieved 2024-09-24. <a href="https://lore.kernel.org/lkml/20240923173750.16874-1-tony.luck@intel.com/" target="_blank">https://lore.kernel.org/lkml/20240923173750.16874-1-tony.luck@intel.com/</a> <a href="#fnref:52" class="footnote-back-ref">↩</a></p></li> <li id="fn:53"><p>On CPUs with more than 128 logical processors in a single package (e.g. Intel Xeon Phi 7290[45] and AMD Threadripper Pro 7995WX[46]) the value in bit 23:16 is set to a non-power-of-2 value. <a href="/wiki/Xeon_Phi" target="_blank">/wiki/Xeon_Phi</a> <a href="#fnref:53" class="footnote-back-ref">↩</a></p></li> <li id="fn:54"><p>Descriptors 77h, 7Eh, 8Dh are documented for the IA-32 operation mode of Itanium 2 only.[81]Intel Processor Identification and the CPUID Instruction (PDF), Intel, May 2002, archived from the original (PDF) on 2021-04-17 <a href="/wiki/Itanium_2" target="_blank">/wiki/Itanium_2</a> <a href="#fnref:54" class="footnote-back-ref">↩</a></p></li> <li id="fn:55"><p>The Local APIC ID can also be identified via the cpuid 0Bh leaf ( CPUID.0Bh.EDX[x2APIC-ID] ). On CPUs with more than 256 logical processors in one package (e.g. Xeon Phi 7290), leaf 0Bh must be used because the APIC ID does not fit into 8 bits. <a href="#fnref:55" class="footnote-back-ref">↩</a></p></li> <li id="fn:56"><p>On some older processors, executing CPUID with a leaf index (EAX) greater than 0 may leave EBX and ECX unmodified, keeping their old values. For this reason, it is recommended to zero out EBX and ECX before executing CPUID with a leaf index of 1.Processors noted to exhibit this behavior include Cyrix MII[48] and IDT WinChip 2.[49] <a href="#fnref:56" class="footnote-back-ref">↩</a></p></li> <li id="fn:57"><p>On processors from IDT, Transmeta and Rise (vendor IDs CentaurHauls, GenuineTMx86 and RiseRiseRise), the CMPXCHG8B instruction is always supported, however the feature bit for the instruction might not be set. This is a workaround for a bug in Windows NT.[50] <a href="#fnref:57" class="footnote-back-ref">↩</a></p></li> <li id="fn:58"><p>On early AMD K5 (AuthenticAMD Family 5 Model 0) processors only, EDX bit 9 used to indicate support for PGE instead. This was moved to bit 13 from K5 Model 1 onwards.[51] <a href="/wiki/AMD_K5" target="_blank">/wiki/AMD_K5</a> <a href="#fnref:58" class="footnote-back-ref">↩</a></p></li> <li id="fn:59"><p>Intel AP-485, revisions 006[52] to 008, lists CPUID.(EAX=1):EDX[bit 10] as having the name "MTRR" (albeit described as "Reserved"/"Do not count on their value") - this name was removed in later revisions of AP-485, and the bit has been listed as reserved with no name since then. <a href="#fnref:59" class="footnote-back-ref">↩</a></p></li> <li id="fn:60"><p>On Pentium Pro (GenuineIntel Family 6 Model 1) processors only, EDX bit 11 is invalid - the bit is set, but the SYSENTER and SYSEXIT instructions are not supported on the Pentium Pro.[53] <a href="/wiki/Pentium_Pro" target="_blank">/wiki/Pentium_Pro</a> <a href="#fnref:60" class="footnote-back-ref">↩</a></p></li> <li id="fn:61"><p>For the MTRRs, additional feature information is not available through CPUID, but instead through the read-only MTRRCAP MSR (MSR 0FEh). This MSR has the following layout: BitsUsage7:0Number of variable-range MTRRs8Fixed-range MTRRs supported9(Reserved)10Write-Combining memory type supported11SMRR (System-Management Range Register) supported12PRMRR (Processor Reserved Memory Range Register, part of SGX) supported13SMRR2 supported[54]14SMRR-lock supported15SEAMRR (SEcure Arbitration Mode Range Register, part of TDX) supported[55]63:16(Reserved) <a href="/wiki/Software_Guard_Extensions" target="_blank">/wiki/Software_Guard_Extensions</a> <a href="#fnref:61" class="footnote-back-ref">↩</a></p></li> <li id="fn:62"><p>Some very early Intel 64 processors have the CMPXCHG16B feature bit set even though they do not support the instruction - this applies to GenuineIntel Family 0Fh Model 3 Stepping 4 chips (90nm Pentium 4) only.[56] <a href="#fnref:62" class="footnote-back-ref">↩</a></p></li> <li id="fn:63"><p>FCMOV and FCOMI instructions only available if onboard x87 FPU also present (indicated by EDX bit 0). <a href="#fnref:63" class="footnote-back-ref">↩</a></p></li> <li id="fn:64"><p>ECX bit 16 is listed as "Reserved" in public Intel and AMD documentation and is not set in any known processor. However, some versions of the Windows Vista kernel are reported to be checking this bit[57] - if it is set, Vista will recognize it as a "processor channels" feature. <a href="/wiki/Windows_Vista" target="_blank">/wiki/Windows_Vista</a> <a href="#fnref:64" class="footnote-back-ref">↩</a></p></li> <li id="fn:65"><p>On Intel and Transmeta[26] CPUs that support PSN (Processor Serial Number), the PSN can be disabled by setting bit 21 of MSR 119h (BBL_CR_CTL) to 1. Doing so will remove leaf 3 and cause CPUID.(EAX=1):EDX[bit 18] to return 0. <a href="#fnref:65" class="footnote-back-ref">↩</a></p></li> <li id="fn:66"><p>Huggahalli, Ram; Iyer, Ravi; Tetrick, Scott (2005). "Direct Cache Access for High Bandwidth Network I/O". ACM SIGARCH Computer Architecture News. 33 (2): 50–59. CiteSeerX 10.1.1.85.3862. doi:10.1145/1080695.1069976. CiteSeerX:10.1.1.91.957. <a href="/w/index.php?title=ACM_SIGARCH_Computer_Architecture_News&action=edit&redlink=1" target="_blank">/w/index.php?title=ACM_SIGARCH_Computer_Architecture_News&action=edit&redlink=1</a> <a href="#fnref:66" class="footnote-back-ref">↩</a></p></li> <li id="fn:67"><p>Drepper, Ulrich (2007), What Every Programmer Should Know About Memory, CiteSeerX:10.1.1.91.957 <a href="/wiki/CiteSeerX" target="_blank">/wiki/CiteSeerX</a> <a href="#fnref:67" class="footnote-back-ref">↩</a></p></li> <li id="fn:68"><p>Intel, Itanium Architecture Software Developer's Manual, rev 2.3, volume 4: IA-32 Instruction Set, may 2010, document number: 323208, table 2-5, page 4:81, see bits 20 and 30. Archived on Feb 15, 2012. <a href="https://www.intel.com/content/dam/www/public/us/en/documents/manuals/itanium-architecture-vol-4-manual.pdf" target="_blank">https://www.intel.com/content/dam/www/public/us/en/documents/manuals/itanium-architecture-vol-4-manual.pdf</a> <a href="#fnref:68" class="footnote-back-ref">↩</a></p></li> <li id="fn:69"><p>On non-Itanium x86 processors, support for the No-execute bit is indicated in CPUID.(EAX=8000_0001):EDX[bit 20] instead. <a href="/wiki/NX_bit" target="_blank">/wiki/NX_bit</a> <a href="#fnref:69" class="footnote-back-ref">↩</a></p></li> <li id="fn:70"><p>EDX bit 28, if set, indicates that bits 23:16 of CPUID.(EAX=1):EBX are valid. If this bit is not set, then the CPU package contains only 1 logical processor.In older documentation, this bit is often listed as a "Hyper-threading technology"[61] flag - however, while this flag is a prerequisite for Hyper-Threading support, it does not by itself indicate support for Hyper-Threading and it has been set on many CPUs that do not feature any form of multi-threading technology.[62] <a href="/wiki/Hyper-threading" target="_blank">/wiki/Hyper-threading</a> <a href="#fnref:70" class="footnote-back-ref">↩</a></p></li> <li id="fn:71"><p>Intel, Itanium Architecture Software Developer's Manual, rev 2.3, volume 4: IA-32 Instruction Set, may 2010, document number: 323208, table 2-5, page 4:81, see bits 20 and 30. Archived on Feb 15, 2012. <a href="https://www.intel.com/content/dam/www/public/us/en/documents/manuals/itanium-architecture-vol-4-manual.pdf" target="_blank">https://www.intel.com/content/dam/www/public/us/en/documents/manuals/itanium-architecture-vol-4-manual.pdf</a> <a href="#fnref:71" class="footnote-back-ref">↩</a></p></li> <li id="fn:72"><p>"Mechanisms to determine if software is running in a VMware virtual machine". VMware Knowledge Base. VMWare. 2015-05-01. Intel and AMD CPUs have reserved bit 31 of ECX of CPUID leaf 0x1 as the hypervisor present bit. This bit allows hypervisors to indicate their presence to the guest operating system. Hypervisors set this bit and physical CPUs (all existing and future CPUs) set this bit to zero. Guest operating systems can test bit 31 to detect if they are running inside a virtual machine. <a href="https://kb.vmware.com/s/article/1009458" target="_blank">https://kb.vmware.com/s/article/1009458</a> <a href="#fnref:72" class="footnote-back-ref">↩</a></p></li> <li id="fn:73"><p>Kataria, Alok; Hecht, Dan (2008-10-01). "Hypervisor CPUID Interface Proposal". LKML Archive on lore.kernel.org. Archived from the original on 2019-03-15. Bit 31 of ECX of CPUID leaf 0x1. This bit has been reserved by Intel & AMD for use by hypervisors and indicates the presence of a hypervisor. Virtual CPU's (hypervisors) set this bit to 1 and physical CPU's (all existing and future CPU's) set this bit to zero. This bit can be probed by the guest software to detect whether they are running inside a virtual machine. <a href="https://lore.kernel.org/lkml/1222881242.9381.17.camel@alok-dev1/" target="_blank">https://lore.kernel.org/lkml/1222881242.9381.17.camel@alok-dev1/</a> <a href="#fnref:73" class="footnote-back-ref">↩</a></p></li> <li id="fn:74"><p>"AMD64 Technology AMD64 Architecture Programmer's Manual Volume 2: System Programming" (PDF) (3.41 ed.). Advanced Micro Devices, Inc. p. 498. 24593. Archived from the original (PDF) on 30 Sep 2023. Retrieved 9 September 2023. 15.2.2 Guest Mode This new processor mode is entered through the VMRUN instruction. When in guest mode, the behavior of some x86 instructions changes to facilitate virtualization. The CPUID function numbers 4000_0000h-4000_00FFh have been reserved for software use. Hypervisors can use these function numbers to provide an interface to pass information from the hypervisor to the guest. This is similar to extracting information about a physical CPU by using CPUID. Hypervisors use the CPUID Fn 400000[FF:00] bit to denote a virtual platform. Feature bit CPUID Fn0000_0001_ECX[31] has been reserved for use by hypervisors to indicate the presence of a hypervisor. Hypervisors set this bit to 1 and physical CPU's set this bit to zero. This bit can be probed by the guest software to detect whether they are running inside a virtual machine. <a href="https://web.archive.org/web/20230930084941/https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.pdf" target="_blank">https://web.archive.org/web/20230930084941/https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.pdf</a> <a href="#fnref:74" class="footnote-back-ref">↩</a></p></li> <li id="fn:75"><p>In older Intel documentation, the bottom byte of the value returned in EAX is described as specifying the number of times the CPUID must be called with EAX=2 to get hold of all the cache/TLB descriptors. However, all known processors that implement this leaf return 01h in this byte, and newer Intel documentation (SDM rev 053[66] and later) specifies this byte as having the value 01h. <a href="#fnref:75" class="footnote-back-ref">↩</a></p></li> <li id="fn:76"><p>For descriptors 0Dh and 0Eh, Intel AP-485 rev 37[67] lists the caches they describe as having ECC - this was removed in rev 38 and later Intel documentation. <a href="#fnref:76" class="footnote-back-ref">↩</a></p></li> <li id="fn:77"><p>For descriptors 0Dh and 0Eh, Intel AP-485 rev 37[67] lists the caches they describe as having ECC - this was removed in rev 38 and later Intel documentation. <a href="#fnref:77" class="footnote-back-ref">↩</a></p></li> <li id="fn:78"><p>Descriptors 10h, 15h, 1Ah, 88h, 89h, 8Ah, 90h, 96h, 9Bh are documented for the IA-32 operation mode of Itanium only.[68] <a href="/wiki/Itanium" target="_blank">/wiki/Itanium</a> <a href="#fnref:78" class="footnote-back-ref">↩</a></p></li> <li id="fn:79"><p>Descriptors 10h, 15h, 1Ah, 88h, 89h, 8Ah, 90h, 96h, 9Bh are documented for the IA-32 operation mode of Itanium only.[68] <a href="/wiki/Itanium" target="_blank">/wiki/Itanium</a> <a href="#fnref:79" class="footnote-back-ref">↩</a></p></li> <li id="fn:80"><p>Descriptors 10h, 15h, 1Ah, 88h, 89h, 8Ah, 90h, 96h, 9Bh are documented for the IA-32 operation mode of Itanium only.[68] <a href="/wiki/Itanium" target="_blank">/wiki/Itanium</a> <a href="#fnref:80" class="footnote-back-ref">↩</a></p></li> <li id="fn:81"><p>The cache described by descriptor 21h is in some places (e.g. AP-485 rev 36[69] but not rev 37) referred to as an "MLC" (Mid-Level Cache). <a href="#fnref:81" class="footnote-back-ref">↩</a></p></li> <li id="fn:82"><p>Descriptor values 26h,27h,28h and 81h are not listed in Intel documentation and are not used in any known released CPU. (81h has been seen in engineering samples of the cancelled Intel Timna.[79]) They have nevertheless been reported to be recognized by the Windows NT kernel v5.1 (Windows XP) and higher. 81h is also recognized by v5.0 (Windows 2000).[80] <a href="/wiki/Intel_Timna" target="_blank">/wiki/Intel_Timna</a> <a href="#fnref:82" class="footnote-back-ref">↩</a></p></li> <li id="fn:83"><p>Descriptor values 26h,27h,28h and 81h are not listed in Intel documentation and are not used in any known released CPU. (81h has been seen in engineering samples of the cancelled Intel Timna.[79]) They have nevertheless been reported to be recognized by the Windows NT kernel v5.1 (Windows XP) and higher. 81h is also recognized by v5.0 (Windows 2000).[80] <a href="/wiki/Intel_Timna" target="_blank">/wiki/Intel_Timna</a> <a href="#fnref:83" class="footnote-back-ref">↩</a></p></li> <li id="fn:84"><p>Descriptor values 26h,27h,28h and 81h are not listed in Intel documentation and are not used in any known released CPU. (81h has been seen in engineering samples of the cancelled Intel Timna.[79]) They have nevertheless been reported to be recognized by the Windows NT kernel v5.1 (Windows XP) and higher. 81h is also recognized by v5.0 (Windows 2000).[80] <a href="/wiki/Intel_Timna" target="_blank">/wiki/Intel_Timna</a> <a href="#fnref:84" class="footnote-back-ref">↩</a></p></li> <li id="fn:85"><p>Descriptors 39h-3Eh and 73h are listed in rev 36 of Intel AP-485,[69] but have been removed from later Intel documentation even though several of them have been used in Intel CPUs (mostly in Netburst-based Celeron CPUs, e.g. 39h in "Willamette-128",[70] 3Bh in "Northwood-128",[71] and 3Ch in "Prescott-256"[72]). <a href="#fnref:85" class="footnote-back-ref">↩</a></p></li> <li id="fn:86"><p>Descriptors 39h-3Eh and 73h are listed in rev 36 of Intel AP-485,[69] but have been removed from later Intel documentation even though several of them have been used in Intel CPUs (mostly in Netburst-based Celeron CPUs, e.g. 39h in "Willamette-128",[70] 3Bh in "Northwood-128",[71] and 3Ch in "Prescott-256"[72]). <a href="#fnref:86" class="footnote-back-ref">↩</a></p></li> <li id="fn:87"><p>Descriptors 39h-3Eh and 73h are listed in rev 36 of Intel AP-485,[69] but have been removed from later Intel documentation even though several of them have been used in Intel CPUs (mostly in Netburst-based Celeron CPUs, e.g. 39h in "Willamette-128",[70] 3Bh in "Northwood-128",[71] and 3Ch in "Prescott-256"[72]). <a href="#fnref:87" class="footnote-back-ref">↩</a></p></li> <li id="fn:88"><p>Descriptors 39h-3Eh and 73h are listed in rev 36 of Intel AP-485,[69] but have been removed from later Intel documentation even though several of them have been used in Intel CPUs (mostly in Netburst-based Celeron CPUs, e.g. 39h in "Willamette-128",[70] 3Bh in "Northwood-128",[71] and 3Ch in "Prescott-256"[72]). <a href="#fnref:88" class="footnote-back-ref">↩</a></p></li> <li id="fn:89"><p>Descriptors 39h-3Eh and 73h are listed in rev 36 of Intel AP-485,[69] but have been removed from later Intel documentation even though several of them have been used in Intel CPUs (mostly in Netburst-based Celeron CPUs, e.g. 39h in "Willamette-128",[70] 3Bh in "Northwood-128",[71] and 3Ch in "Prescott-256"[72]). <a href="#fnref:89" class="footnote-back-ref">↩</a></p></li> <li id="fn:90"><p>Descriptors 39h-3Eh and 73h are listed in rev 36 of Intel AP-485,[69] but have been removed from later Intel documentation even though several of them have been used in Intel CPUs (mostly in Netburst-based Celeron CPUs, e.g. 39h in "Willamette-128",[70] 3Bh in "Northwood-128",[71] and 3Ch in "Prescott-256"[72]). <a href="#fnref:90" class="footnote-back-ref">↩</a></p></li> <li id="fn:91"><p>Descriptor 3Fh is, as of November 2024, not listed in any known Intel documentation - it is nevertheless used in Intel Tolapai processors,[73] and is listed in an Intel-provided Linux kernel patch.[74] <a href="/wiki/Tolapai" target="_blank">/wiki/Tolapai</a> <a href="#fnref:91" class="footnote-back-ref">↩</a></p></li> <li id="fn:92"><p>Documentation for the VIA Cyrix III "Joshua" processor (CyrixInstead Family 6 Model 5) indicates that this processor uses descriptor values 74h and 77h for its TLBs, and values 42h and 82h for its caches - but does not specify which caches/TLBs in the processor each of these descriptor values correspond to.[75] <a href="/wiki/Cyrix_III" target="_blank">/wiki/Cyrix_III</a> <a href="#fnref:92" class="footnote-back-ref">↩</a></p></li> <li id="fn:93"><p>Descriptor 49h indicates a level-3 cache on GenuineIntel Family 0Fh Model 6 (Pentium 4 based Xeon) CPUs, and a level-2 cache on other CPUs. <a href="#fnref:93" class="footnote-back-ref">↩</a></p></li> <li id="fn:94"><p>Intel's CPUID documentation does not specify the associativity of the ITLB indicated by descriptor 4Fh. The processors that use this descriptor (Intel Atom "Bonnell"[76]) are described elsewhere as having a fully-associative 32-entry ITLB.[77] <a href="/wiki/Bonnell_(microarchitecture)" target="_blank">/wiki/Bonnell_(microarchitecture)</a> <a href="#fnref:94" class="footnote-back-ref">↩</a></p></li> <li id="fn:95"><p>On Cyrix and Geode CPUs (Vendor IDs CyrixInstead and Geode by NSC), descriptors 70h and 80h have a different meaning:[78] Descriptor 70h indicates a 32-entry shared instruction+data 4-way-set-associative TLB with a 4K page size. Descriptor 80h indicates a 16 KB shared instruction+data L1 cache with 4-way set-associativity and a cache-line size of 16 bytes. <a href="#fnref:95" class="footnote-back-ref">↩</a></p></li> <li id="fn:96"><p>Descriptors 39h-3Eh and 73h are listed in rev 36 of Intel AP-485,[69] but have been removed from later Intel documentation even though several of them have been used in Intel CPUs (mostly in Netburst-based Celeron CPUs, e.g. 39h in "Willamette-128",[70] 3Bh in "Northwood-128",[71] and 3Ch in "Prescott-256"[72]). <a href="#fnref:96" class="footnote-back-ref">↩</a></p></li> <li id="fn:97"><p>Documentation for the VIA Cyrix III "Joshua" processor (CyrixInstead Family 6 Model 5) indicates that this processor uses descriptor values 74h and 77h for its TLBs, and values 42h and 82h for its caches - but does not specify which caches/TLBs in the processor each of these descriptor values correspond to.[75] <a href="/wiki/Cyrix_III" target="_blank">/wiki/Cyrix_III</a> <a href="#fnref:97" class="footnote-back-ref">↩</a></p></li> <li id="fn:98"><p>Descriptor 76h is listed as an 1 MB L2 cache in rev 37 of Intel AP-485,[67] but as an instruction TLB in rev 38 and all later Intel documentation. <a href="#fnref:98" class="footnote-back-ref">↩</a></p></li> <li id="fn:99"><p>Descriptors 77h, 7Eh, 8Dh are documented for the IA-32 operation mode of Itanium 2 only.[81]Intel Processor Identification and the CPUID Instruction (PDF), Intel, May 2002, archived from the original (PDF) on 2021-04-17 <a href="/wiki/Itanium_2" target="_blank">/wiki/Itanium_2</a> <a href="#fnref:99" class="footnote-back-ref">↩</a></p></li> <li id="fn:100"><p>Documentation for the VIA Cyrix III "Joshua" processor (CyrixInstead Family 6 Model 5) indicates that this processor uses descriptor values 74h and 77h for its TLBs, and values 42h and 82h for its caches - but does not specify which caches/TLBs in the processor each of these descriptor values correspond to.[75] <a href="/wiki/Cyrix_III" target="_blank">/wiki/Cyrix_III</a> <a href="#fnref:100" class="footnote-back-ref">↩</a></p></li> <li id="fn:101"><p>Descriptors 77h, 7Eh, 8Dh are documented for the IA-32 operation mode of Itanium 2 only.[81]Intel Processor Identification and the CPUID Instruction (PDF), Intel, May 2002, archived from the original (PDF) on 2021-04-17 <a href="/wiki/Itanium_2" target="_blank">/wiki/Itanium_2</a> <a href="#fnref:101" class="footnote-back-ref">↩</a></p></li> <li id="fn:102"><p>On Cyrix and Geode CPUs (Vendor IDs CyrixInstead and Geode by NSC), descriptors 70h and 80h have a different meaning:[78] Descriptor 70h indicates a 32-entry shared instruction+data 4-way-set-associative TLB with a 4K page size. Descriptor 80h indicates a 16 KB shared instruction+data L1 cache with 4-way set-associativity and a cache-line size of 16 bytes. <a href="#fnref:102" class="footnote-back-ref">↩</a></p></li> <li id="fn:103"><p>Descriptor values 26h,27h,28h and 81h are not listed in Intel documentation and are not used in any known released CPU. (81h has been seen in engineering samples of the cancelled Intel Timna.[79]) They have nevertheless been reported to be recognized by the Windows NT kernel v5.1 (Windows XP) and higher. 81h is also recognized by v5.0 (Windows 2000).[80] <a href="/wiki/Intel_Timna" target="_blank">/wiki/Intel_Timna</a> <a href="#fnref:103" class="footnote-back-ref">↩</a></p></li> <li id="fn:104"><p>Documentation for the VIA Cyrix III "Joshua" processor (CyrixInstead Family 6 Model 5) indicates that this processor uses descriptor values 74h and 77h for its TLBs, and values 42h and 82h for its caches - but does not specify which caches/TLBs in the processor each of these descriptor values correspond to.[75] <a href="/wiki/Cyrix_III" target="_blank">/wiki/Cyrix_III</a> <a href="#fnref:104" class="footnote-back-ref">↩</a></p></li> <li id="fn:105"><p>Descriptors 10h, 15h, 1Ah, 88h, 89h, 8Ah, 90h, 96h, 9Bh are documented for the IA-32 operation mode of Itanium only.[68] <a href="/wiki/Itanium" target="_blank">/wiki/Itanium</a> <a href="#fnref:105" class="footnote-back-ref">↩</a></p></li> <li id="fn:106"><p>Descriptors 10h, 15h, 1Ah, 88h, 89h, 8Ah, 90h, 96h, 9Bh are documented for the IA-32 operation mode of Itanium only.[68] <a href="/wiki/Itanium" target="_blank">/wiki/Itanium</a> <a href="#fnref:106" class="footnote-back-ref">↩</a></p></li> <li id="fn:107"><p>Descriptors 10h, 15h, 1Ah, 88h, 89h, 8Ah, 90h, 96h, 9Bh are documented for the IA-32 operation mode of Itanium only.[68] <a href="/wiki/Itanium" target="_blank">/wiki/Itanium</a> <a href="#fnref:107" class="footnote-back-ref">↩</a></p></li> <li id="fn:108"><p>Descriptors 77h, 7Eh, 8Dh are documented for the IA-32 operation mode of Itanium 2 only.[81]Intel Processor Identification and the CPUID Instruction (PDF), Intel, May 2002, archived from the original (PDF) on 2021-04-17 <a href="/wiki/Itanium_2" target="_blank">/wiki/Itanium_2</a> <a href="#fnref:108" class="footnote-back-ref">↩</a></p></li> <li id="fn:109"><p>Under the IA-32 operation mode of Itanium 2, the L3 cache size is always reported as 3 MB regardless of the actual size of the cache.[82] <a href="#fnref:109" class="footnote-back-ref">↩</a></p></li> <li id="fn:110"><p>Descriptors 10h, 15h, 1Ah, 88h, 89h, 8Ah, 90h, 96h, 9Bh are documented for the IA-32 operation mode of Itanium only.[68] <a href="/wiki/Itanium" target="_blank">/wiki/Itanium</a> <a href="#fnref:110" class="footnote-back-ref">↩</a></p></li> <li id="fn:111"><p>Descriptors 10h, 15h, 1Ah, 88h, 89h, 8Ah, 90h, 96h, 9Bh are documented for the IA-32 operation mode of Itanium only.[68] <a href="/wiki/Itanium" target="_blank">/wiki/Itanium</a> <a href="#fnref:111" class="footnote-back-ref">↩</a></p></li> <li id="fn:112"><p>Descriptors 10h, 15h, 1Ah, 88h, 89h, 8Ah, 90h, 96h, 9Bh are documented for the IA-32 operation mode of Itanium only.[68] <a href="/wiki/Itanium" target="_blank">/wiki/Itanium</a> <a href="#fnref:112" class="footnote-back-ref">↩</a></p></li> <li id="fn:113"><p>For descriptor B1h, the TLB capacity is 8 elements when using 2 MB pages, but reduced to 4 elements when using 4 MB pages. <a href="#fnref:113" class="footnote-back-ref">↩</a></p></li> <li id="fn:114"><p>Intel, Atom C3000 Processor Product Family Specification Update, order no. 336345-020, page 16, Mar 2023. Archived on 7 Oct 2023. <a href="https://cdrdv2-public.intel.com/336345/336345_C3000_SU_Rev020.pdf" target="_blank">https://cdrdv2-public.intel.com/336345/336345_C3000_SU_Rev020.pdf</a> <a href="#fnref:114" class="footnote-back-ref">↩</a></p></li> <li id="fn:115"><p>For descriptor C3h, many Intel processors that use this descriptor have an L2 TLB that is 12-way set-associative, not 6-way set-associative. This applies to at least Skylake[84] and Whiskey/Kaby/Coffee/Comet Lake[85] CPUs. <a href="#fnref:115" class="footnote-back-ref">↩</a></p></li> <li id="fn:116"><p>Intel, Xeon Processor 7500 Series Datasheet, order no. 323341-001, March 2010, page 150. Archived on Oct 8, 2023. <a href="https://www.intel.com.tw/content/dam/www/public/us/en/documents/datasheets/xeon-processor-7500-series-vol-2-datasheet.pdf" target="_blank">https://www.intel.com.tw/content/dam/www/public/us/en/documents/datasheets/xeon-processor-7500-series-vol-2-datasheet.pdf</a> <a href="#fnref:116" class="footnote-back-ref">↩</a></p></li> <li id="fn:117"><p>The prefetch specified by descriptors F0h and F1h is the recommended stride for memory prefetching with the PREFETCHNTA instruction.[87] <a href="#fnref:117" class="footnote-back-ref">↩</a></p></li> <li id="fn:118"><p>The prefetch specified by descriptors F0h and F1h is the recommended stride for memory prefetching with the PREFETCHNTA instruction.[87] <a href="#fnref:118" class="footnote-back-ref">↩</a></p></li> <li id="fn:119"><p>Intel AP-485, revisions 31[88] and 32, list bits 9:0 of EDX as a "Prefetch Stride" field - this was removed in revision 33 and all later Intel documentation, and no processor is known to use EDX in this manner. <a href="#fnref:119" class="footnote-back-ref">↩</a></p></li> <li id="fn:120"><p>For CPUID leaf 4, bits 11:10 of EAX are documented for the Xeon Phi "Knights Corner" (GenuineIntel Family 0Bh) processor only.[42] For other processors, bits 1:0 of EDX should be used instead. <a href="#fnref:120" class="footnote-back-ref">↩</a></p></li> <li id="fn:121"><p>For CPUID leaf 4, bits 11:10 of EAX are documented for the Xeon Phi "Knights Corner" (GenuineIntel Family 0Bh) processor only.[42] For other processors, bits 1:0 of EDX should be used instead. <a href="#fnref:121" class="footnote-back-ref">↩</a></p></li> <li id="fn:122"><p>Shih Kuo (Jan 27, 2012). "Intel 64 Architecture Processor Topology Enumeration". <a href="https://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration/" target="_blank">https://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration/</a> <a href="#fnref:122" class="footnote-back-ref">↩</a></p></li> <li id="fn:123"><p>"Processor and Core Enumeration Using CPUID | AMD". Developer.amd.com. Archived from the original on 2014-07-14. Retrieved 2014-07-10. <a href="https://web.archive.org/web/20140714221717/http://developer.amd.com/resources/documentation-articles/articles-whitepapers/processor-and-core-enumeration-using-cpuid/" target="_blank">https://web.archive.org/web/20140714221717/http://developer.amd.com/resources/documentation-articles/articles-whitepapers/processor-and-core-enumeration-using-cpuid/</a> <a href="#fnref:123" class="footnote-back-ref">↩</a></p></li> <li id="fn:124"><p>"Sandybridge processors report incorrect core number?". Software.intel.com. 2012-12-29. Retrieved 2014-07-10. <a href="https://software.intel.com/en-us/forums/topic/352709#comment-1719904" target="_blank">https://software.intel.com/en-us/forums/topic/352709#comment-1719904</a> <a href="#fnref:124" class="footnote-back-ref">↩</a></p></li> <li id="fn:125"><p>"cpuid, __cpuidex". Msdn.microsoft.com. 2014-06-20. Retrieved 2014-07-10. <a href="http://msdn.microsoft.com/en-us/library/hskdteyh.aspx" target="_blank">http://msdn.microsoft.com/en-us/library/hskdteyh.aspx</a> <a href="#fnref:125" class="footnote-back-ref">↩</a></p></li> <li id="fn:126"><p>"x86 architecture - CPUID". sandpile.org. Retrieved 2014-07-10. <a href="http://www.sandpile.org/x86/cpuid.htm" target="_blank">http://www.sandpile.org/x86/cpuid.htm</a> <a href="#fnref:126" class="footnote-back-ref">↩</a></p></li> <li id="fn:127"><p>Shih Kuo (Jan 27, 2012). "Intel 64 Architecture Processor Topology Enumeration". <a href="https://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration/" target="_blank">https://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration/</a> <a href="#fnref:127" class="footnote-back-ref">↩</a></p></li> <li id="fn:128"><p>"topology.cpp in ps/trunk/source/lib/sysdep/arch/x86_x64 – Wildfire Games". Trac.wildfiregames.com. 2011-12-27. Archived from the original on 2021-03-09. Retrieved 2014-07-10. <a href="https://web.archive.org/web/20210309001211/http://trac.wildfiregames.com/browser/ps/trunk/source/lib/sysdep/arch/x86_x64/topology.cpp" target="_blank">https://web.archive.org/web/20210309001211/http://trac.wildfiregames.com/browser/ps/trunk/source/lib/sysdep/arch/x86_x64/topology.cpp</a> <a href="#fnref:128" class="footnote-back-ref">↩</a></p></li> <li id="fn:129"><p>Hyper-Threading Technology and Multi-Core Processor Detection <a href="https://software.intel.com/en-us/articles/hyper-threading-technology-and-multi-core-processor-detection" target="_blank">https://software.intel.com/en-us/articles/hyper-threading-technology-and-multi-core-processor-detection</a> <a href="#fnref:129" class="footnote-back-ref">↩</a></p></li> <li id="fn:130"><p>The C0 to C7 states are processor-specific C-states, which do not necessarily correspond 1:1 to ACPI C-states. <a href="/wiki/ACPI#Processor_states" target="_blank">/wiki/ACPI#Processor_states</a> <a href="#fnref:130" class="footnote-back-ref">↩</a></p></li> <li id="fn:131"><p>Intel, Architecture Instruction Set Extensions Programming Reference, order no. 319433-052, March 2024, chapter 17. Archived on Apr 7, 2024. <a href="https://cdrdv2-public.intel.com/819680/architecture-instruction-set-extensions-programming-reference.pdf" target="_blank">https://cdrdv2-public.intel.com/819680/architecture-instruction-set-extensions-programming-reference.pdf</a> <a href="#fnref:131" class="footnote-back-ref">↩</a></p></li> <li id="fn:132"><p>On Intel Pentium 4 family processors only, bit 2 of EAX is used to indicate OPP (Operating Point Protection)[97] instead of ARAT. <a href="#fnref:132" class="footnote-back-ref">↩</a></p></li> <li id="fn:133"><p>To enable fast (non-serializing) access mode for the IA32_HWP_REQUEST MSR on CPUs that support it, it is necessary to set bit 0 of the FAST_UNCORE_MSRS_CTL(657h) MSR. <a href="#fnref:133" class="footnote-back-ref">↩</a></p></li> <li id="fn:134"><p>Intel, Intel 64 and IA-32 Architecture Software Developer's Manual, order no. 352462-079, volume 3B, section 15.4.4.4, page 3503 <a href="https://kib.kiev.ua/x86docs/Intel/SDMs/325462-079.pdf" target="_blank">https://kib.kiev.ua/x86docs/Intel/SDMs/325462-079.pdf</a> <a href="#fnref:134" class="footnote-back-ref">↩</a></p></li> <li id="fn:135"><p>The "ACNT2 Capability" bit is listed in Intel AP-485 rev 038[99] and 039, but not listed in any revision of the Intel SDM. The feature is known to exist in only a few Intel CPUs, e.g. Xeon "Harpertown" stepping E0.[100] <a href="#fnref:135" class="footnote-back-ref">↩</a></p></li> <li id="fn:136"><p>As of April 2024, the FZM, MPRR and SGX_TEM bits are listed only in Intel TDX documentation[102] and are not set in any known processor. <a href="/wiki/Trust_Domain_Extensions" target="_blank">/wiki/Trust_Domain_Extensions</a> <a href="#fnref:136" class="footnote-back-ref">↩</a></p></li> <li id="fn:137"><p>"Performance Monitoring Impact of Intel Transactional Synchronization Extension Memory Ordering Issue" (PDF). Intel. June 2023. p. 8. Retrieved 8 May 2024. <a href="https://cdrdv2.intel.com/v1/dl/getContent/604224" target="_blank">https://cdrdv2.intel.com/v1/dl/getContent/604224</a> <a href="#fnref:137" class="footnote-back-ref">↩</a></p></li> <li id="fn:138"><p>"Performance Monitoring Impact of Intel Transactional Synchronization Extension Memory Ordering Issue" (PDF). Intel. June 2023. p. 8. Retrieved 8 May 2024. <a href="https://cdrdv2.intel.com/v1/dl/getContent/604224" target="_blank">https://cdrdv2.intel.com/v1/dl/getContent/604224</a> <a href="#fnref:138" class="footnote-back-ref">↩</a></p></li> <li id="fn:139"><p>As of April 2024, the FZM, MPRR and SGX_TEM bits are listed only in Intel TDX documentation[102] and are not set in any known processor. <a href="/wiki/Trust_Domain_Extensions" target="_blank">/wiki/Trust_Domain_Extensions</a> <a href="#fnref:139" class="footnote-back-ref">↩</a></p></li> <li id="fn:140"><p>Intel, Deprecating the PCOMMIT instruction, sep 12, 2016. Archived on Apr 23, 2023. <a href="https://www.intel.com/content/www/us/en/developer/articles/technical/deprecate-pcommit-instruction.html" target="_blank">https://www.intel.com/content/www/us/en/developer/articles/technical/deprecate-pcommit-instruction.html</a> <a href="#fnref:140" class="footnote-back-ref">↩</a></p></li> <li id="fn:141"><p>Intel, AVX512-FP16 Architecture Specification (PDF), document number 347407-001, June 2021. Archived on Oct 26, 2022 <a href="https://cdrdv2-public.intel.com/678970/intel-avx512-fp16.pdf" target="_blank">https://cdrdv2-public.intel.com/678970/intel-avx512-fp16.pdf</a> <a href="#fnref:141" class="footnote-back-ref">↩</a></p></li> <li id="fn:142"><p>As of April 2024, the FZM, MPRR and SGX_TEM bits are listed only in Intel TDX documentation[102] and are not set in any known processor. <a href="/wiki/Trust_Domain_Extensions" target="_blank">/wiki/Trust_Domain_Extensions</a> <a href="#fnref:142" class="footnote-back-ref">↩</a></p></li> <li id="fn:143"><p>"Speculative Execution Side Channel Mitigations" (PDF). Revision 2.0. Intel. May 2018 [January 2018]. Document Number: 336996-002. Retrieved 2018-05-26. <a href="https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf" target="_blank">https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf</a> <a href="#fnref:143" class="footnote-back-ref">↩</a></p></li> <li id="fn:144"><p>"IBRS patch series [LWN.net]". <a href="https://lwn.net/Articles/743019/" target="_blank">https://lwn.net/Articles/743019/</a> <a href="#fnref:144" class="footnote-back-ref">↩</a></p></li> <li id="fn:145"><p>"Speculative Execution Side Channel Mitigations" (PDF). Revision 2.0. Intel. May 2018 [January 2018]. Document Number: 336996-002. Retrieved 2018-05-26. <a href="https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf" target="_blank">https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf</a> <a href="#fnref:145" class="footnote-back-ref">↩</a></p></li> <li id="fn:146"><p>"Speculative Execution Side Channel Mitigations" (PDF). Revision 2.0. Intel. May 2018 [January 2018]. Document Number: 336996-002. Retrieved 2018-05-26. <a href="https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf" target="_blank">https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf</a> <a href="#fnref:146" class="footnote-back-ref">↩</a></p></li> <li id="fn:147"><p>"Speculative Execution Side Channel Mitigations" (PDF). Revision 2.0. Intel. May 2018 [January 2018]. Document Number: 336996-002. Retrieved 2018-05-26. <a href="https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf" target="_blank">https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf</a> <a href="#fnref:147" class="footnote-back-ref">↩</a></p></li> <li id="fn:148"><p>Intel, X86S External Architecture Specification v1.2, June 2024, order no. 351407-002, section 3.5, page 13. Archived from the original on 2 Oct 2024. <a href="https://web.archive.org/web/20241002150150/https://cdrdv2-public.intel.com/776648/x86s-eas-external-1.2.pdf" target="_blank">https://web.archive.org/web/20241002150150/https://cdrdv2-public.intel.com/776648/x86s-eas-external-1.2.pdf</a> <a href="#fnref:148" class="footnote-back-ref">↩</a></p></li> <li id="fn:149"><p>Intel, Envisioning a Simplified Intel Architecture - as of 20 Dec 2024, contains a mention that Intel has chosen not to pursue X86S. Archived on 20 Dec 2024. <a href="https://www.intel.com/content/www/us/en/developer/articles/technical/envisioning-future-simplified-architecture.html" target="_blank">https://www.intel.com/content/www/us/en/developer/articles/technical/envisioning-future-simplified-architecture.html</a> <a href="#fnref:149" class="footnote-back-ref">↩</a></p></li> <li id="fn:150"><p>As of April 2024, the DEDUP bit is listed only in Intel TDX documentation[102] and is not set in any known processor. <a href="/wiki/Trust_Domain_Extensions" target="_blank">/wiki/Trust_Domain_Extensions</a> <a href="#fnref:150" class="footnote-back-ref">↩</a></p></li> <li id="fn:151"><p>Intel, Flexible Return and Event Delivery (FRED) Specification, rev 6.1, December 2023, order no. 346446-007, page 14. Archived on Dec 22, 2023. <a href="https://cdrdv2-public.intel.com/795033/346446-flexible-return-and-event-delivery.pdf" target="_blank">https://cdrdv2-public.intel.com/795033/346446-flexible-return-and-event-delivery.pdf</a> <a href="#fnref:151" class="footnote-back-ref">↩</a></p></li> <li id="fn:152"><p>Intel, Flexible Return and Event Delivery (FRED) Specification, rev 6.1, December 2023, order no. 346446-007, page 14. Archived on Dec 22, 2023. <a href="https://cdrdv2-public.intel.com/795033/346446-flexible-return-and-event-delivery.pdf" target="_blank">https://cdrdv2-public.intel.com/795033/346446-flexible-return-and-event-delivery.pdf</a> <a href="#fnref:152" class="footnote-back-ref">↩</a></p></li> <li id="fn:153"><p>Intel, Software Developer's Manual, order no. 325462-080, June 2023 - information about prematurely busy shadow stacks provided in Volume 1, section 17.2.3 on page 410; Volume 2A, table 3.8 (CPUID EAX=7,ECX=2) on page 820; Volume 3C, table 25-14 on page 3958 and section 26.4.3 on page 3984. <a href="https://kib.kiev.ua/x86docs/Intel/SDMs/325462-080.pdf" target="_blank">https://kib.kiev.ua/x86docs/Intel/SDMs/325462-080.pdf</a> <a href="#fnref:153" class="footnote-back-ref">↩</a></p></li> <li id="fn:154"><p>Intel, Complex Shadow-Stack Updates (Intel Control-Flow Enforcement Technology), order no. 356628-001, August 2023. Archived on 2 Apr 2024. <a href="https://cdrdv2-public.intel.com/785687/356628-complex-shadow-stack-updates-2.pdf" target="_blank">https://cdrdv2-public.intel.com/785687/356628-complex-shadow-stack-updates-2.pdf</a> <a href="#fnref:154" class="footnote-back-ref">↩</a></p></li> <li id="fn:155"><p>LKML, Re: (PATCH v3 00/21) Enable CET Virtualization, Jun 16, 2023 - provides additional discussion of how the CET-SSS prematurely-busy stack issue interacts with virtualization. Archived on 7 Aug 2023. <a href="https://lkml.org/lkml/2023/6/16/1194" target="_blank">https://lkml.org/lkml/2023/6/16/1194</a> <a href="#fnref:155" class="footnote-back-ref">↩</a></p></li> <li id="fn:156"><p>Intel, Advanced Vector Extensions 10, rev 1.0, July 2023, order no. 355989-001. Archived on Jul 24, 2023. <a href="https://cdrdv2-public.intel.com/784267/355989-intel-avx10-spec.pdf" target="_blank">https://cdrdv2-public.intel.com/784267/355989-intel-avx10-spec.pdf</a> <a href="#fnref:156" class="footnote-back-ref">↩</a></p></li> <li id="fn:157"><p>Intel, Flexible Return and Event Delivery (FRED) Specification, rev 6.1, December 2023, order no. 346446-007, page 14. Archived on Dec 22, 2023. <a href="https://cdrdv2-public.intel.com/795033/346446-flexible-return-and-event-delivery.pdf" target="_blank">https://cdrdv2-public.intel.com/795033/346446-flexible-return-and-event-delivery.pdf</a> <a href="#fnref:157" class="footnote-back-ref">↩</a></p></li> <li id="fn:158"><p>Intel, Advanced Performance Extensions - Architecture Specification, rev 2.0, Aug 2023, order no. 355828-002, page 37. Archived on Sep 10, 2023. <a href="https://cdrdv2-public.intel.com/786223/355828-intel-apx-spec.pdf" target="_blank">https://cdrdv2-public.intel.com/786223/355828-intel-apx-spec.pdf</a> <a href="#fnref:158" class="footnote-back-ref">↩</a></p></li> <li id="fn:159"><p>Support for the MWAIT instruction may be indicated by either CPUID.(EAX=1).ECX[3] or CPUID.(EAX=7,ECX=1).EDX[23]. (One or both may be set.) The former indicates support for the MONITOR instruction as well, while the latter does not indicate one way or another whether the MONITOR instruction is present. MWAIT without MONITOR may be present in systems that support the "Monitorless MWAIT" feature (which is itself indicated by CPUID.(EAX=5).ECX[3].) <a href="#fnref:159" class="footnote-back-ref">↩</a></p></li> <li id="fn:160"><p>Intel, Fast Store Forwarding Predictor, 8 Feb 2022. Archived on 6 Apr 2024. <a href="https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/fast-store-forwarding-predictor.html" target="_blank">https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/fast-store-forwarding-predictor.html</a> <a href="#fnref:160" class="footnote-back-ref">↩</a></p></li> <li id="fn:161"><p>Intel, Branch History Injection and Intra-mode Branch Target Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598, 4 Aug 2022. Archived on 5 May 2023. <a href="https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/branch-history-injection.html" target="_blank">https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/branch-history-injection.html</a> <a href="#fnref:161" class="footnote-back-ref">↩</a></p></li> <li id="fn:162"><p>Intel, Return Stack Buffer Underflow / CVE-2022-29901, CVE-2022-28693 / INTEL-SA-00702, 12 Jul 2022. Archived on 13 Jul 2022. <a href="https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/advisory-guidance/return-stack-buffer-underflow.html" target="_blank">https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/advisory-guidance/return-stack-buffer-underflow.html</a> <a href="#fnref:162" class="footnote-back-ref">↩</a></p></li> <li id="fn:163"><p>Intel, Branch History Injection and Intra-mode Branch Target Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598, 4 Aug 2022. Archived on 5 May 2023. <a href="https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/branch-history-injection.html" target="_blank">https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/branch-history-injection.html</a> <a href="#fnref:163" class="footnote-back-ref">↩</a></p></li> <li id="fn:164"><p>Intel, Data Dependent Prefetcher, 10 Nov 2022. Archived on 4 Aug 2024. <a href="https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/data-dependent-prefetcher.html" target="_blank">https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/data-dependent-prefetcher.html</a> <a href="#fnref:164" class="footnote-back-ref">↩</a></p></li> <li id="fn:165"><p>Intel, Branch History Injection and Intra-mode Branch Target Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598, 4 Aug 2022. Archived on 5 May 2023. <a href="https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/branch-history-injection.html" target="_blank">https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/branch-history-injection.html</a> <a href="#fnref:165" class="footnote-back-ref">↩</a></p></li> <li id="fn:166"><p>Intel, MONITOR and UMONITOR Performance Guidance, 10 Jul 2024. Archived on 27 Nov 2024. <a href="https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/monitor-umonitor-performance-guidance.html" target="_blank">https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/monitor-umonitor-performance-guidance.html</a> <a href="#fnref:166" class="footnote-back-ref">↩</a></p></li> <li id="fn:167"><p>Bit 0 of XCR0 is hardwired to 1, so that the XSAVE instructions will always support save/restore of x87 state. <a href="#fnref:167" class="footnote-back-ref">↩</a></p></li> <li id="fn:168"><p>Intel, Advanced Performance Extensions - Architecture Specification, rev 2.0, Aug 2023, order no. 355828-002, page 37. Archived on Sep 10, 2023. <a href="https://cdrdv2-public.intel.com/786223/355828-intel-apx-spec.pdf" target="_blank">https://cdrdv2-public.intel.com/786223/355828-intel-apx-spec.pdf</a> <a href="#fnref:168" class="footnote-back-ref">↩</a></p></li> <li id="fn:169"><p>For the XCR0 and IA32_XSS registers, bit 63 is reserved specifically for bit vector expansion - this precludes the existence of a state-component 63. <a href="#fnref:169" class="footnote-back-ref">↩</a></p></li> <li id="fn:170"><p>For the copy of the SECS that exists inside an exclave, bit 0 (INIT) of SECS.ATTRIBUTES is used to indicate that the enclave has been initialized with ENCLS[EINIT]. This bit must be 0 in the SECS copy that is given as input to ENCLS[CREATE]. <a href="#fnref:170" class="footnote-back-ref">↩</a></p></li> <li id="fn:171"><p>Intel, Asynchronous Enclave Exit Notify and the EDECCSSA User Leaf Function, 30 Jun 2022. Archived on 21 Nov 2022. <a href="https://cdrdv2-public.intel.com/736463/aex-notify-white-paper-public.pdf" target="_blank">https://cdrdv2-public.intel.com/736463/aex-notify-white-paper-public.pdf</a> <a href="#fnref:171" class="footnote-back-ref">↩</a></p></li> <li id="fn:172"><p>Field not enumerated if zero. <a href="#fnref:172" class="footnote-back-ref">↩</a></p></li> <li id="fn:173"><p>Field not enumerated if zero. <a href="#fnref:173" class="footnote-back-ref">↩</a></p></li> <li id="fn:174"><p>The frequency values reported by leaf 16h are the processor's specification frequencies - they are constant for the given processor and do not necessarily reflect the actual CPU clock speed at the time CPUID is called. <a href="#fnref:174" class="footnote-back-ref">↩</a></p></li> <li id="fn:175"><p>Field not enumerated if zero. <a href="#fnref:175" class="footnote-back-ref">↩</a></p></li> <li id="fn:176"><p>Field not enumerated if zero. <a href="#fnref:176" class="footnote-back-ref">↩</a></p></li> <li id="fn:177"><p>Field not enumerated if zero. <a href="#fnref:177" class="footnote-back-ref">↩</a></p></li> <li id="fn:178"><p>Linux kernel git commit 604dc91, x86/tsc: Use CPUID.0x16 to calculate missing crystal frequency, 9 May 2019 - contains notes on computing the Core Crystal Clock frequency on CPUs that don't specify it, and corresponding C code. <a href="https://github.com/torvalds/linux/commit/604dc9170f2435d27da5039a3efd757dceadc684" target="_blank">https://github.com/torvalds/linux/commit/604dc9170f2435d27da5039a3efd757dceadc684</a> <a href="#fnref:178" class="footnote-back-ref">↩</a></p></li> <li id="fn:179"><p>Intel, SDM Volume 3A, order no 253668-083, March 2024, chapter 11.5.4, page 408 <a href="https://kib.kiev.ua/x86docs/Intel/SDMs/253668-083.pdf" target="_blank">https://kib.kiev.ua/x86docs/Intel/SDMs/253668-083.pdf</a> <a href="#fnref:179" class="footnote-back-ref">↩</a></p></li> <li id="fn:180"><p>As of May 2024, the following Vendor IDs are known to have been assigned by Intel: IDVendor1Spreadtrum[123] <a href="/wiki/Spreadtrum" target="_blank">/wiki/Spreadtrum</a> <a href="#fnref:180" class="footnote-back-ref">↩</a></p></li> <li id="fn:181"><p>As of May 2024, Intel documentation does not specify which "Industry Standard" enumeration scheme to use for the Vendor ID in EBX[15:0] if EBX[16] is set. <a href="#fnref:181" class="footnote-back-ref">↩</a></p></li> <li id="fn:182"><p>As of April 2024, the "Process Restriction" bit is listed only in Intel TDX documentation[102] and is not set in any known processor. <a href="/wiki/Trust_Domain_Extensions" target="_blank">/wiki/Trust_Domain_Extensions</a> <a href="#fnref:182" class="footnote-back-ref">↩</a></p></li> <li id="fn:183"><p>Intel, Architecture Specification: Intel Trust Domain Extensions (Intel TDX) Module, order no. 344425-005, page 93, Feb 2023. Archived on 20 Jul 2023. <a href="https://cdrdv2-public.intel.com/733568/tdx-module-1.0-public-spec-344425005.pdf" target="_blank">https://cdrdv2-public.intel.com/733568/tdx-module-1.0-public-spec-344425005.pdf</a> <a href="#fnref:183" class="footnote-back-ref">↩</a></p></li> <li id="fn:184"><p>Intel, Advanced Vector Extensions 10, rev 1.0, July 2023, order no. 355989-001. Archived on Jul 24, 2023. <a href="https://cdrdv2-public.intel.com/784267/355989-intel-avx10-spec.pdf" target="_blank">https://cdrdv2-public.intel.com/784267/355989-intel-avx10-spec.pdf</a> <a href="#fnref:184" class="footnote-back-ref">↩</a></p></li> <li id="fn:185"><p>These three bits were originally designed to indicate the "supported vector width", with bit 16 indicating 128-bit vector support, bit 17 for 256-bit, and bit 18 for 512-bit. 128-bit maximum CPUs were said to have "AVX10/128" support, 256-bit maximum to have "AVX10/256" support, and 512-bit maximum to have "AVX10/512" support; The number after the slash indicated the maximum supported vector width. Shortly after the announcement of AVX10.1, Intel dropped plans for AVX10/128,[125], likely after pushback from developers, leaving only 256-bit and 512-bit maximum vector widths as supported. With AVX10.2, Intel dropped the vector width distinction entirely, instead mandating 512-bit vector support. As the only shipping AVX10.1 CPUs were based on Granite Rapids, a P-core-only design (and subsequently has had AVX10/512), no AVX10/256 CPUs were ever shipped. In other words, the only shipped CPUs with AVX10 had 128-, 256-, and 512-bit support, putting all three bits as 111b. <a href="#fnref:185" class="footnote-back-ref">↩</a></p></li> <li id="fn:186"><p>Intel, Trust Domain Extensions (Intel TDX) Module Base Architecture Specification, order no. 348549-006US, April 2025, p. 116. Archived on 24 Apr 2025. <a href="https://cdrdv2-public.intel.com/853286/intel-tdx-module-base-spec-348549006.pdf" target="_blank">https://cdrdv2-public.intel.com/853286/intel-tdx-module-base-spec-348549006.pdf</a> <a href="#fnref:186" class="footnote-back-ref">↩</a></p></li> <li id="fn:187"><p>The AVX10.2 VNNI instructions are present if either the AVX10 version is 2 or higher (see CPUID.(EAX=24h).EBX[7:0]) or the AVX10_VNNI_INT bit is set. <a href="#fnref:187" class="footnote-back-ref">↩</a></p></li> <li id="fn:188"><p>Intel, Advanced Vector Extensions 10.2 Architecture Specification, revision 4.0, order no. 361050-004US, May 2025, p. 16. Archived on 25 May 2025. <a href="https://cdrdv2-public.intel.com/855340/361050-004-intel-avx10.2-spec.pdf" target="_blank">https://cdrdv2-public.intel.com/855340/361050-004-intel-avx10.2-spec.pdf</a> <a href="#fnref:188" class="footnote-back-ref">↩</a></p></li> <li id="fn:189"><p>Intel, Intel Xeon Phi Coprocessor Instruction Set Architecture Reference Manual, Sep 2012, order no. 327364-001, appendix B.8, pages 677. Archived on 4 Aug 2021. <a href="https://www.intel.com/content/dam/develop/external/us/en/documents/327364001en.pdf" target="_blank">https://www.intel.com/content/dam/develop/external/us/en/documents/327364001en.pdf</a> <a href="#fnref:189" class="footnote-back-ref">↩</a></p></li> <li id="fn:190"><p>Intel, Intel Xeon Phi Coprocessor Instruction Set Architecture Reference Manual, Sep 2012, order no. 327364-001, appendix B.8, pages 677. Archived on 4 Aug 2021. <a href="https://www.intel.com/content/dam/develop/external/us/en/documents/327364001en.pdf" target="_blank">https://www.intel.com/content/dam/develop/external/us/en/documents/327364001en.pdf</a> <a href="#fnref:190" class="footnote-back-ref">↩</a></p></li> <li id="fn:191"><p>Microsoft, Hyper-V Feature and Interface Discovery, 8 Jul 2022. Archived on 18 Nov 2023. <a href="https://learn.microsoft.com/en-us/virtualization/hyper-v-on-windows/tlfs/feature-discovery" target="_blank">https://learn.microsoft.com/en-us/virtualization/hyper-v-on-windows/tlfs/feature-discovery</a> <a href="#fnref:191" class="footnote-back-ref">↩</a></p></li> <li id="fn:192"><p>Geoff Chappell, HV_HYPERVISOR_INTERFACE, 10 Dec 2022. Archived on 1 Feb 2023. <a href="https://www.geoffchappell.com/studies/windows/km/ntoskrnl/inc/shared/hvgdk_mini/hv_hypervisor_interface.htm" target="_blank">https://www.geoffchappell.com/studies/windows/km/ntoskrnl/inc/shared/hvgdk_mini/hv_hypervisor_interface.htm</a> <a href="#fnref:192" class="footnote-back-ref">↩</a></p></li> <li id="fn:193"><p>QEMU documentation, Hyper-V Enlightenments. Archived on 17 Apr 2024. <a href="https://www.qemu.org/docs/master/system/i386/hyperv.html" target="_blank">https://www.qemu.org/docs/master/system/i386/hyperv.html</a> <a href="#fnref:193" class="footnote-back-ref">↩</a></p></li> <li id="fn:194"><p>Linux 6.8.7 kernel source, /source/arch/x86/kvm/cpuid.c, lines 1482-1488 <a href="https://elixir.bootlin.com/linux/v6.8.7/source/arch/x86/kvm/cpuid.c" target="_blank">https://elixir.bootlin.com/linux/v6.8.7/source/arch/x86/kvm/cpuid.c</a> <a href="#fnref:194" class="footnote-back-ref">↩</a></p></li> <li id="fn:195"><p>Microsoft, Hyper-V Feature and Interface Discovery, 8 Jul 2022. Archived on 18 Nov 2023. <a href="https://learn.microsoft.com/en-us/virtualization/hyper-v-on-windows/tlfs/feature-discovery" target="_blank">https://learn.microsoft.com/en-us/virtualization/hyper-v-on-windows/tlfs/feature-discovery</a> <a href="#fnref:195" class="footnote-back-ref">↩</a></p></li> <li id="fn:196"><p>Linux kernel documentation, KVM CPUID bits. Archived on 22 Aug 2022. <a href="https://docs.kernel.org/virt/kvm/x86/cpuid.html" target="_blank">https://docs.kernel.org/virt/kvm/x86/cpuid.html</a> <a href="#fnref:196" class="footnote-back-ref">↩</a></p></li> <li id="fn:197"><p>Linux 6.8.7 kernel source, /arch/x86/kvm/hyperv.c, line 2793 <a href="https://elixir.bootlin.com/linux/v6.8.7/source/arch/x86/kvm/hyperv.c#L2793" target="_blank">https://elixir.bootlin.com/linux/v6.8.7/source/arch/x86/kvm/hyperv.c#L2793</a> <a href="#fnref:197" class="footnote-back-ref">↩</a></p></li> <li id="fn:198"><p>Linux kernel documentation, Virtualization support: 4.118 KVM_GET_SUPPORTED_HV_CPUID. Archived on 26 Mar 2024. <a href="https://docs.kernel.org/virt/kvm/api.html#kvm-get-supported-hv-cpuid" target="_blank">https://docs.kernel.org/virt/kvm/api.html#kvm-get-supported-hv-cpuid</a> <a href="#fnref:198" class="footnote-back-ref">↩</a></p></li> <li id="fn:199"><p>FreeBSD commit 560d5ed, 28 Jun 2013, see file /sys/amd64/vmm/x86.c, line 48. Archived on 22 Apr 2024. <a href="https://github.com/freebsd/freebsd-src/commit/560d5eda2cb0861d11dd055fc63199e21116f6e5" target="_blank">https://github.com/freebsd/freebsd-src/commit/560d5eda2cb0861d11dd055fc63199e21116f6e5</a> <a href="#fnref:199" class="footnote-back-ref">↩</a></p></li> <li id="fn:200"><p>HyperKit source code, /src/lib/vmm/x86.c line 42, 8 May 2021. <a href="https://github.com/moby/hyperkit/blob/45c0ba15f100871ba29d0bd227ca58e5426a4a50/src/lib/vmm/x86.c#L42" target="_blank">https://github.com/moby/hyperkit/blob/45c0ba15f100871ba29d0bd227ca58e5426a4a50/src/lib/vmm/x86.c#L42</a> <a href="#fnref:200" class="footnote-back-ref">↩</a></p></li> <li id="fn:201"><p>Xen, CPUID Interface to Xen. Archived on 22 Apr 2024. <a href="https://xenbits.xen.org/docs/unstable/hypercall/x86_32/include,public,arch-x86,cpuid.h.html" target="_blank">https://xenbits.xen.org/docs/unstable/hypercall/x86_32/include,public,arch-x86,cpuid.h.html</a> <a href="#fnref:201" class="footnote-back-ref">↩</a></p></li> <li id="fn:202"><p>QEMU source code, fb/target/i386/cpu.c, line 6475, 18 Mar 2024. <a href="https://github.com/qemu/qemu/blob/2cc68629a6fc198f4a972698bdd6477f883aedfb/target/i386/cpu.c#L6475" target="_blank">https://github.com/qemu/qemu/blob/2cc68629a6fc198f4a972698bdd6477f883aedfb/target/i386/cpu.c#L6475</a> <a href="#fnref:202" class="footnote-back-ref">↩</a></p></li> <li id="fn:203"><p>VMWare, Mechanisms to determine if software is running in a VMware virtual machine, 1 May 2015. Archived on 18 Jun 2023. <a href="https://kb.vmware.com/s/article/1009458" target="_blank">https://kb.vmware.com/s/article/1009458</a> <a href="#fnref:203" class="footnote-back-ref">↩</a></p></li> <li id="fn:204"><p>Project ACRN, CPUID Virtualization, 20 Oct 2022. Archived on 25 Mar 2023. <a href="https://projectacrn.github.io/latest/developer-guides/hld/hv-cpu-virt.html#cpuid-virtualization" target="_blank">https://projectacrn.github.io/latest/developer-guides/hld/hv-cpu-virt.html#cpuid-virtualization</a> <a href="#fnref:204" class="footnote-back-ref">↩</a></p></li> <li id="fn:205"><p>VirtualBox documentation, 9.30 Paravirtualized Debugging. Archived on 22 Apr 2024. <a href="https://www.virtualbox.org/manual/ch09.html#gimdebug" target="_blank">https://www.virtualbox.org/manual/ch09.html#gimdebug</a> <a href="#fnref:205" class="footnote-back-ref">↩</a></p></li> <li id="fn:206"><p>QNX, Hypervisor - Checking the guest's environment, 25 Mar 2022. Archived on 22 Apr 2024. <a href="https://www.qnx.com/developers/docs/7.1/#com.qnx.doc.hypervisor.safety.user/topic/qhs/guest_check.html" target="_blank">https://www.qnx.com/developers/docs/7.1/#com.qnx.doc.hypervisor.safety.user/topic/qhs/guest_check.html</a> <a href="#fnref:206" class="footnote-back-ref">↩</a></p></li> <li id="fn:207"><p>NetBSD source code, /sys/dev/nvmm/x86/nvmm_x86_vmx.c, line 1430, 6 Nov 2023. <a href="https://github.com/NetBSD/src/blob/90116d8fc2f0c32a7863c868afa8d77e9a865cc7/sys/dev/nvmm/x86/nvmm_x86_vmx.c#L1430" target="_blank">https://github.com/NetBSD/src/blob/90116d8fc2f0c32a7863c868afa8d77e9a865cc7/sys/dev/nvmm/x86/nvmm_x86_vmx.c#L1430</a> <a href="#fnref:207" class="footnote-back-ref">↩</a></p></li> <li id="fn:208"><p>OpenBSD source code, /sys/arch/amd64/include/vmmvar.h, line 24, 9 Apr 2024. <a href="https://github.com/openbsd/src/blob/1ebbcee88fd42e4612c9e2e6d12b4aad159f7741/sys/arch/amd64/include/vmmvar.h#L24" target="_blank">https://github.com/openbsd/src/blob/1ebbcee88fd42e4612c9e2e6d12b4aad159f7741/sys/arch/amd64/include/vmmvar.h#L24</a> <a href="#fnref:208" class="footnote-back-ref">↩</a></p></li> <li id="fn:209"><p>Siemens Jailhouse hypervisor documentation, hypervisor-interfaces.txt, line 39, 27 Jan 2020. Archived on Jul 5, 2024. <a href="https://github.com/siemens/jailhouse/blob/e57d1eff6d55aeed5f977fe4e2acfb6ccbdd7560/Documentation/hypervisor-interfaces.txt" target="_blank">https://github.com/siemens/jailhouse/blob/e57d1eff6d55aeed5f977fe4e2acfb6ccbdd7560/Documentation/hypervisor-interfaces.txt</a> <a href="#fnref:209" class="footnote-back-ref">↩</a></p></li> <li id="fn:210"><p>Bitdefender Napoca source code, /napoca/kernel/guestenlight.c, line 293, 30 Jul 2020. <a href="https://github.com/bitdefender/napoca/blob/c97d26c672ac9dba5373385fc69be32a856a4d02/napoca/kernel/guestenlight.c#L293" target="_blank">https://github.com/bitdefender/napoca/blob/c97d26c672ac9dba5373385fc69be32a856a4d02/napoca/kernel/guestenlight.c#L293</a> <a href="#fnref:210" class="footnote-back-ref">↩</a></p></li> <li id="fn:211"><p>Intel HAXM source code, /core/cpuid.c, line 979, 20 Jan 2023. Archived on 22 Apr 2024. <a href="https://github.com/intel/haxm/blob/cc86e90b5ed959e6904c13b54e21ad45b9ad12ce/core/cpuid.c#L979" target="_blank">https://github.com/intel/haxm/blob/cc86e90b5ed959e6904c13b54e21ad45b9ad12ce/core/cpuid.c#L979</a> <a href="#fnref:211" class="footnote-back-ref">↩</a></p></li> <li id="fn:212"><p>Intel KGT source code (trusty branch), /vmm/vmexit/vmexit_cpuid.c, lines 17-75, 15 May 2019 <a href="https://github.com/intel/ikgt-core/blob/7dfd4d1614d788ec43b02602cce7a272ef8d5931/vmm/vmexit/vmexit_cpuid.c" target="_blank">https://github.com/intel/ikgt-core/blob/7dfd4d1614d788ec43b02602cce7a272ef8d5931/vmm/vmexit/vmexit_cpuid.c</a> <a href="#fnref:212" class="footnote-back-ref">↩</a></p></li> <li id="fn:213"><p>Linux kernel v5.18.19 source code, /source/drivers/visorbus/visorchipset.c, line 28 <a href="https://elixir.bootlin.com/linux/v5.18.19/source/drivers/visorbus/visorchipset.c" target="_blank">https://elixir.bootlin.com/linux/v5.18.19/source/drivers/visorbus/visorchipset.c</a> <a href="#fnref:213" class="footnote-back-ref">↩</a></p></li> <li id="fn:214"><p>N. Moore, virt: Support detection of LMHS SRE guests #25594, 1 Dec 2022 - Lockheed Martin-provided pull-request for systemd, adding CPUID hypervisor ID string for the LMHS SRE hypervisor. Archived on 23 Apr 2024. <a href="https://github.com/systemd/systemd/pull/25594/commits/edc028437def5c1e005ce1b965ecf400a7c1498a" target="_blank">https://github.com/systemd/systemd/pull/25594/commits/edc028437def5c1e005ce1b965ecf400a7c1498a</a> <a href="#fnref:214" class="footnote-back-ref">↩</a></p></li> <li id="fn:215"><p>CPUID Specification, publication no.25481, rev 2.34 (PDF), AMD, September 2010, archived from the original (PDF) on 18 Aug 2022 <a href="https://web.archive.org/web/20220818192714/http://developer.amd.com/wordpress/media/2012/10/25481.pdf" target="_blank">https://web.archive.org/web/20220818192714/http://developer.amd.com/wordpress/media/2012/10/25481.pdf</a> <a href="#fnref:215" class="footnote-back-ref">↩</a></p></li> <li id="fn:216"><p>Linux kernel source code <a href="https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/x86/include/asm/cpufeatures.h?id=HEAD" target="_blank">https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/x86/include/asm/cpufeatures.h?id=HEAD</a> <a href="#fnref:216" class="footnote-back-ref">↩</a></p></li> <li id="fn:217"><p>The use of EDX bit 10 to indicate support for SYSCALL/SYSRET is only valid on AuthenticAMD Family 5 Model 7 CPUs (AMD K6, 250nm "Little Foot") - for all other processors, EDX bit 11 should be used instead.These instructions were first introduced on Model 7[154] - the CPUID bit to indicate their support was moved[155] to EDX bit 11 from Model 8 (AMD K6-2) onwards. <a href="/wiki/List_of_AMD_CPU_microarchitectures" target="_blank">/wiki/List_of_AMD_CPU_microarchitectures</a> <a href="#fnref:217" class="footnote-back-ref">↩</a></p></li> <li id="fn:218"><p>On Intel CPUs, the CPUID bit for SYSCALL/SYSRET is only set if the CPUID instruction is executed in 64-bit mode.[156] <a href="#fnref:218" class="footnote-back-ref">↩</a></p></li> <li id="fn:219"><p>Lightweight Profiling Specification (PDF), AMD, August 2010, archived from the original (PDF) on 2012-11-27, retrieved 2013-04-03 <a href="https://web.archive.org/web/20121127061327/http://support.amd.com/us/Processor_TechDocs/43724.pdf" target="_blank">https://web.archive.org/web/20121127061327/http://support.amd.com/us/Processor_TechDocs/43724.pdf</a> <a href="#fnref:219" class="footnote-back-ref">↩</a></p></li> <li id="fn:220"><p>On some processors - Cyrix MediaGXm,[158] several Geodes (NatSemi Geode GXm, GXLV, GX1; AMD Geode GX1[159]) and Transmeta Crusoe[160] - EDX bits 16 and 24 have a different meaning: Bit 16: Floating-point Conditional Move (FCMOV) supported Bit 24: 6x86MX Extended MMX instructions supported <a href="/wiki/MediaGX" target="_blank">/wiki/MediaGX</a> <a href="#fnref:220" class="footnote-back-ref">↩</a></p></li> <li id="fn:221"><p>EDX bit 19 is used for CPU brand identification on AuthenticAMD Family 6 processors only - the bit is, combined with processor signature and FSB speed, used to identify processors as either multiprocessor-capable or carrying the Sempron brand name.[161] <a href="/wiki/AMD_K7" target="_blank">/wiki/AMD_K7</a> <a href="#fnref:221" class="footnote-back-ref">↩</a></p></li> <li id="fn:222"><p>AMD, Family 10h BKDG, document no. 31116, rev 3.62, jan 11, 2013, p. 388 - lists the NodeId bit. Archived on 16 Jan 2019. <a href="https://www.amd.com/system/files/TechDocs/31116.pdf" target="_blank">https://www.amd.com/system/files/TechDocs/31116.pdf</a> <a href="#fnref:222" class="footnote-back-ref">↩</a></p></li> <li id="fn:223"><p>On some processors - Cyrix MediaGXm,[158] several Geodes (NatSemi Geode GXm, GXLV, GX1; AMD Geode GX1[159]) and Transmeta Crusoe[160] - EDX bits 16 and 24 have a different meaning: Bit 16: Floating-point Conditional Move (FCMOV) supported Bit 24: 6x86MX Extended MMX instructions supported <a href="/wiki/MediaGX" target="_blank">/wiki/MediaGX</a> <a href="#fnref:223" class="footnote-back-ref">↩</a></p></li> <li id="fn:224"><p>ECX bit 25 is listed as StreamPerfMon in revision 3.20 of AMD APM[163] only - it is listed as reserved in later revisions. The bit is set on Excavator and Steamroller CPUs only. <a href="#fnref:224" class="footnote-back-ref">↩</a></p></li> <li id="fn:225"><p>"Intel Processor Identification and the CPUID Instruction" (PDF). Download.intel.com. 2012-03-06. Retrieved 2013-04-11. <a href="http://download.intel.com/design/processor/applnots/24161832.pdf" target="_blank">http://download.intel.com/design/processor/applnots/24161832.pdf</a> <a href="#fnref:225" class="footnote-back-ref">↩</a></p></li> <li id="fn:226"><p>InstLatx64, Vortex86DX3 CPUID dump, 27 Sep 2021. Archived on 21 Oct 2021. <a href="http://users.atw.hu/instlatx64/Vortex86_SoC/Vortex86%20SoC0000611_Vortex86DX3_CPUID.txt" target="_blank">http://users.atw.hu/instlatx64/Vortex86_SoC/Vortex86%20SoC0000611_Vortex86DX3_CPUID.txt</a> <a href="#fnref:226" class="footnote-back-ref">↩</a></p></li> <li id="fn:227"><p>InstLatx64, AMD Ryzen 7 6800HS CPUID dump, 21 Feb 2022. Archived on 24 Mar 2023. <a href="http://users.atw.hu/instlatx64/AuthenticAMD/AuthenticAMD0A40F41_K19_Rembrandt_01_CPUID.txt" target="_blank">http://users.atw.hu/instlatx64/AuthenticAMD/AuthenticAMD0A40F41_K19_Rembrandt_01_CPUID.txt</a> <a href="#fnref:227" class="footnote-back-ref">↩</a></p></li> <li id="fn:228"><p>AMD, Processor Recognition Application Note, pub.no. 20734, rev. 3.13, december 2005. Section 2.2.2 (p.20) and Section 3 (pages 33 to 40) provide details on how CPUID.(EAX=8000_0001):EDX[bit 19] should be used to identify processors. Section 3 also provides information on AMD's brand name string MSRs. Archived from the original on Jun 26, 2006. <a href="https://web.archive.org/web/20060626212818/http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/20734.pdf" target="_blank">https://web.archive.org/web/20060626212818/http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/20734.pdf</a> <a href="#fnref:228" class="footnote-back-ref">↩</a></p></li> <li id="fn:229"><p>Chips and Cheese, Why you can't trust CPUID, 27 Oct 2022. Archived on 3 Nov 2022. <a href="https://chipsandcheese.com/2022/10/27/why-you-cant-trust-cpuid/" target="_blank">https://chipsandcheese.com/2022/10/27/why-you-cant-trust-cpuid/</a> <a href="#fnref:229" class="footnote-back-ref">↩</a></p></li> <li id="fn:230"><p>AMD, Geode LX Databook, pub.id. 33234H, Feb 2009, page 207. <a href="https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/datasheets/33234H_LX_databook.pdf" target="_blank">https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/datasheets/33234H_LX_databook.pdf</a> <a href="#fnref:230" class="footnote-back-ref">↩</a></p></li> <li id="fn:231"><p>InstLatx64, 2x 24-core Montage Jintide C2460 CPUID dump <a href="http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel0050654_SkylakeXeon_Jintide_CPUID1.txt" target="_blank">http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel0050654_SkylakeXeon_Jintide_CPUID1.txt</a> <a href="#fnref:231" class="footnote-back-ref">↩</a></p></li> <li id="fn:232"><p>InstLatx64, 2x 24-core Intel Xeon Platinum 8160 CPUID dump <a href="http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel0050654_SkylakeXeon_20_CPUID.txt" target="_blank">http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel0050654_SkylakeXeon_20_CPUID.txt</a> <a href="#fnref:232" class="footnote-back-ref">↩</a></p></li> <li id="fn:233"><p>InstLatx64, Zhaoxin KaiXian ZX-C+ C4580 CPUID dump <a href="http://users.atw.hu/instlatx64/CentaurHauls/CentaurHauls00006FE_CNR_Isaiah_CPUID3.txt" target="_blank">http://users.atw.hu/instlatx64/CentaurHauls/CentaurHauls00006FE_CNR_Isaiah_CPUID3.txt</a> <a href="#fnref:233" class="footnote-back-ref">↩</a></p></li> <li id="fn:234"><p>InstLatx64, VIA Eden X4 C4250 CPUID dump <a href="http://users.atw.hu/instlatx64/CentaurHauls/CentaurHauls00006FE_CNR_Isaiah_CPUID.txt" target="_blank">http://users.atw.hu/instlatx64/CentaurHauls/CentaurHauls00006FE_CNR_Isaiah_CPUID.txt</a> <a href="#fnref:234" class="footnote-back-ref">↩</a></p></li> <li id="fn:235"><p>On some older Cyrix and Geode CPUs (specifically, CyrixInstead/Geode by NSC Family 5 Model 4 CPUs only), leaf 80000005h exists but has a completely different format, similar to that of leaf 2.[173] <a href="#fnref:235" class="footnote-back-ref">↩</a></p></li> <li id="fn:236"><p>On processors that can only handle small-pages in their TLBs, this leaf will return 0 in EAX. (On such processors, which include e.g. AMD K6 and Transmeta Crusoe, hugepage entries in the page-tables are broken up into 4K pages as needed upon entry into the TLB.)On some processors, e.g. VIA Cyrix III "Samuel",[174] this leaf returns 0x80000005 in EAX. This has the same meaning as EAX=0, i.e. no hugepage TLBs. <a href="/wiki/Cyrix_III" target="_blank">/wiki/Cyrix_III</a> <a href="#fnref:236" class="footnote-back-ref">↩</a></p></li> <li id="fn:237"><p>On Transmeta CPUs, the value FFh is used to indicate a 256-entry TLB. <a href="#fnref:237" class="footnote-back-ref">↩</a></p></li> <li id="fn:238"><p>For the associativity fields of leaf 80000005h, the following values are used: ValueMeaning0(reserved)1Direct-mapped2 to FEhN-way set-associative (field encodes N)FFhFully-associative <a href="#fnref:238" class="footnote-back-ref">↩</a></p></li> <li id="fn:239"><p>On Transmeta CPUs, the value FFh is used to indicate a 256-entry TLB. <a href="#fnref:239" class="footnote-back-ref">↩</a></p></li> <li id="fn:240"><p>For the associativity fields of leaf 80000005h, the following values are used: ValueMeaning0(reserved)1Direct-mapped2 to FEhN-way set-associative (field encodes N)FFhFully-associative <a href="#fnref:240" class="footnote-back-ref">↩</a></p></li> <li id="fn:241"><p>For the associativity fields of leaf 80000005h, the following values are used: ValueMeaning0(reserved)1Direct-mapped2 to FEhN-way set-associative (field encodes N)FFhFully-associative <a href="#fnref:241" class="footnote-back-ref">↩</a></p></li> <li id="fn:242"><p>AMD, BKDG for AMD Family 10h Processors, pub.no. 31116, rev 3.62, jan 11, 2013, page 392. Archived on 16 Jan 2019. <a href="https://www.amd.com/system/files/TechDocs/31116.pdf" target="_blank">https://www.amd.com/system/files/TechDocs/31116.pdf</a> <a href="#fnref:242" class="footnote-back-ref">↩</a></p></li> <li id="fn:243"><p>AMD, PPR For AMD Family 19h Model 61h rev B1 procesors, pub.no. 56713, rev 3.05, Mar 8, 2023, pages 99-100. Archived on 25 Apr 2023. <a href="https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip" target="_blank">https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip</a> <a href="#fnref:243" class="footnote-back-ref">↩</a></p></li> <li id="fn:244"><p>AMD, PPR For AMD Family 19h Model 61h rev B1 procesors, pub.no. 56713, rev 3.05, Mar 8, 2023, pages 99-100. Archived on 25 Apr 2023. <a href="https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip" target="_blank">https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip</a> <a href="#fnref:244" class="footnote-back-ref">↩</a></p></li> <li id="fn:245"><p>AMD, PPR For AMD Family 19h Model 61h rev B1 procesors, pub.no. 56713, rev 3.05, Mar 8, 2023, pages 99-100. Archived on 25 Apr 2023. <a href="https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip" target="_blank">https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip</a> <a href="#fnref:245" class="footnote-back-ref">↩</a></p></li> <li id="fn:246"><p>AMD, BKDG for AMD Family 16h Models 00-0Fh processors, pub.no. 48571, rev 3.03, Feb 19, 2015, page 482. Archived on 16 Jan 2019. <a href="https://www.amd.com/system/files/TechDocs/48751_16h_bkdg.pdf" target="_blank">https://www.amd.com/system/files/TechDocs/48751_16h_bkdg.pdf</a> <a href="#fnref:246" class="footnote-back-ref">↩</a></p></li> <li id="fn:247"><p>SpecterDev, Next-Gen Exploitation: Exploring the PS5 Security Landscape, June 2023 hardwear.io conference presentation slide deck, pages 34, 41 and 53. Archived on 10 Jun 2023. <a href="https://hardwear.io/usa-2023/presentation/next-gen-exploitation-exploring-the-PS5-security-landscape.pdf" target="_blank">https://hardwear.io/usa-2023/presentation/next-gen-exploitation-exploring-the-PS5-security-landscape.pdf</a> <a href="#fnref:247" class="footnote-back-ref">↩</a></p></li> <li id="fn:248"><p>As of June 2025, bits 5, 7, and 11 of CPUID.(EAX=8000_0008):EBX are not listed in any known public AMD documentation, but have been observed to be set on AMD 4700S Desktop Kit processors.[179] <a href="#fnref:248" class="footnote-back-ref">↩</a></p></li> <li id="fn:249"><p>As of June 2025, bits 5, 7, and 11 of CPUID.(EAX=8000_0008):EBX are not listed in any known public AMD documentation, but have been observed to be set on AMD 4700S Desktop Kit processors.[179] <a href="#fnref:249" class="footnote-back-ref">↩</a></p></li> <li id="fn:250"><p>As of June 2025, bits 5, 7, and 11 of CPUID.(EAX=8000_0008):EBX are not listed in any known public AMD documentation, but have been observed to be set on AMD 4700S Desktop Kit processors.[179] <a href="#fnref:250" class="footnote-back-ref">↩</a></p></li> <li id="fn:251"><p>The LMSLE (Long Mode Segment Limit Enable) feature does not have its own CPUID flag and is detected by checking CPU family and model. It was introduced in AuthenticAMD Family 0Fh Model 14h[180] (90nm Athlon64/Opteron) CPUs and is present in all later AMD CPUs - except the ones with the 'no_efer_lmsle' flag set. <a href="#fnref:251" class="footnote-back-ref">↩</a></p></li> <li id="fn:252"><p>AMD, PPR For AMD Family 19h Model 61h rev B1 procesors, pub.no. 56713, rev 3.05, Mar 8, 2023, pages 99-100. Archived on 25 Apr 2023. <a href="https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip" target="_blank">https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip</a> <a href="#fnref:252" class="footnote-back-ref">↩</a></p></li> <li id="fn:253"><p>AMD, PPR for AMD Family 19h Model 01h, Revision B1 Processors, Volume 1 of 2, document no. 55898, rev 0.50, may 27, 2021, page 98 - lists branch-sampling bit. Archived on Jul 24, 2022 <a href="https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip" target="_blank">https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip</a> <a href="#fnref:253" class="footnote-back-ref">↩</a></p></li> <li id="fn:254"><p>A value of 0 indicates that the "Guest Physical Address Size" is the same as the "Number Of Physical Address Bits", specified in EAX[7:0]. <a href="#fnref:254" class="footnote-back-ref">↩</a></p></li> <li id="fn:255"><p>Early revisions of AMD's "Pacifica" documentation listed EAX bit 8 as an always-zero bit reserved for hypervisor use.[182]Later AMD documentation, such as #25481 "CPUID specification" rev 2.18[183] and later, only lists the bit as reserved.In rev 2.30[184] and later, a different bit is listed as reserved for hypervisor use: CPUID.(EAX=1):ECX[bit 31]. <a href="#fnref:255" class="footnote-back-ref">↩</a></p></li> <li id="fn:256"><p>EDX bit 9 is briefly listed in some older revisions of AMD's document #25481 "CPUID Specification", and is set only in some AMD Bobcat CPUs.[185]Rev 2.28 of #25481 lists the bit as "Ssse3Sse5Dis"[186] - in rev 2.34, it is listed as having been removed from the spec at rev 2.32 under the name "SseIsa10Compat".[187] <a href="/wiki/Bobcat_(microarchitecture)" target="_blank">/wiki/Bobcat_(microarchitecture)</a> <a href="#fnref:256" class="footnote-back-ref">↩</a></p></li> <li id="fn:257"><p>AMD, PPR for AMD Family 19h Model 61h, Revision B1 processors, document no. 56713, rev 3.05, mar 8 2023, page 102. Archived on Apr 25, 2023. <a href="https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip" target="_blank">https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip</a> <a href="#fnref:257" class="footnote-back-ref">↩</a></p></li> <li id="fn:258"><p>AMD, PPR for AMD Family 19h Model 61h, Revision B1 processors, document no. 56713, rev 3.05, mar 8 2023, page 102. Archived on Apr 25, 2023. <a href="https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip" target="_blank">https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip</a> <a href="#fnref:258" class="footnote-back-ref">↩</a></p></li> <li id="fn:259"><p>AMD, Processor Programming Reference (PPR) for AMD Family 1Ah Model 24h, Revision B0 Processors, order no. 57254, rev 3.00, Sep 26, 2024, pages 102, 118, 119 and 199. <a href="https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/software-optimization-guides/57254-PUB_3.00.zip" target="_blank">https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/software-optimization-guides/57254-PUB_3.00.zip</a> <a href="#fnref:259" class="footnote-back-ref">↩</a></p></li> <li id="fn:260"><p>AMD, Secure VM Service Module for SEV-SNP Guests, pub.no #58019, rev 1.00, Jul 2023, page 13. Archived on 5 Aug 2023. <a href="https://www.amd.com/system/files/TechDocs/58019_1.00.pdf" target="_blank">https://www.amd.com/system/files/TechDocs/58019_1.00.pdf</a> <a href="#fnref:260" class="footnote-back-ref">↩</a></p></li> <li id="fn:261"><p>AMD, PPR for AMD Family 19h Model 61h, Revision B1 processors, document no. 56713, rev 3.05, mar 8 2023, page 116. Archived on Apr 25, 2023. <a href="https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip" target="_blank">https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip</a> <a href="#fnref:261" class="footnote-back-ref">↩</a></p></li> <li id="fn:262"><p>AMD, Processor Programming Reference (PPR) for AMD Family 1Ah Model 24h, Revision B0 Processors, order no. 57254, rev 3.00, Sep 26, 2024, pages 102, 118, 119 and 199. <a href="https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/software-optimization-guides/57254-PUB_3.00.zip" target="_blank">https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/software-optimization-guides/57254-PUB_3.00.zip</a> <a href="#fnref:262" class="footnote-back-ref">↩</a></p></li> <li id="fn:263"><p>AMD, Processor Programming Reference (PPR) for AMD Family 1Ah Model 24h, Revision B0 Processors, order no. 57254, rev 3.00, Sep 26, 2024, pages 102, 118, 119 and 199. <a href="https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/software-optimization-guides/57254-PUB_3.00.zip" target="_blank">https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/software-optimization-guides/57254-PUB_3.00.zip</a> <a href="#fnref:263" class="footnote-back-ref">↩</a></p></li> <li id="fn:264"><p>AMD, PPR for AMD Family 19h Model 61h, Revision B1 processors, document no. 56713, rev 3.05, mar 8 2023, page 116. Archived on Apr 25, 2023. <a href="https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip" target="_blank">https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip</a> <a href="#fnref:264" class="footnote-back-ref">↩</a></p></li> <li id="fn:265"><p>If the downgrade from 512-bit to 256-bit datapath is enabled, then AVX-512 instructions that work on 512-bit data items will be split into two 256-bit parts that will be issued over two consecutive cycles. This datapath downgrade can help improve power efficiency for some workloads.[192] <a href="#fnref:265" class="footnote-back-ref">↩</a></p></li> <li id="fn:266"><p>AMD, Technical Update Regarding Speculative Return Stack Overflow, rev 2.0, feb 2024. Archived on Apr 12, 2024. <a href="https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf" target="_blank">https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf</a> <a href="#fnref:266" class="footnote-back-ref">↩</a></p></li> <li id="fn:267"><p>AMD, Technical Update Regarding Speculative Return Stack Overflow, rev 2.0, feb 2024. Archived on Apr 12, 2024. <a href="https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf" target="_blank">https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf</a> <a href="#fnref:267" class="footnote-back-ref">↩</a></p></li> <li id="fn:268"><p>AMD, Technical Update Regarding Speculative Return Stack Overflow, rev 2.0, feb 2024. Archived on Apr 12, 2024. <a href="https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf" target="_blank">https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf</a> <a href="#fnref:268" class="footnote-back-ref">↩</a></p></li> <li id="fn:269"><p>AMD, Technical Update Regarding Speculative Return Stack Overflow, rev 2.0, feb 2024. Archived on Apr 12, 2024. <a href="https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf" target="_blank">https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf</a> <a href="#fnref:269" class="footnote-back-ref">↩</a></p></li> <li id="fn:270"><p>AMD, Technical Update Regarding Speculative Return Stack Overflow, rev 2.0, feb 2024. Archived on Apr 12, 2024. <a href="https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf" target="_blank">https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf</a> <a href="#fnref:270" class="footnote-back-ref">↩</a></p></li> <li id="fn:271"><p>Ferrie, Peter. "Attacks on Virtual Machine Emulators" (PDF). Symantec. Symantec Advanced Threat Research. Archived from the original (PDF) on 2007-02-07. Retrieved 15 March 2017. <a href="https://web.archive.org/web/20070207103157/http://www.symantec.com/avcenter/reference/Virtual_Machine_Threats.pdf" target="_blank">https://web.archive.org/web/20070207103157/http://www.symantec.com/avcenter/reference/Virtual_Machine_Threats.pdf</a> <a href="#fnref:271" class="footnote-back-ref">↩</a></p></li> <li id="fn:272"><p>Sandpile, x86 architecture CPUID. Retrieved 22 December 2022. <a href="https://sandpile.org/x86/cpuid.htm" target="_blank">https://sandpile.org/x86/cpuid.htm</a> <a href="#fnref:272" class="footnote-back-ref">↩</a></p></li> <li id="fn:273"><p>instlatx64, CPUID dump of AMD A4-5000, lists "HELLO KITTY" string for CPUID leaf 8FFFFFFFh. Retrieved 22 December 2022. <a href="http://users.atw.hu/instlatx64/AuthenticAMD/AuthenticAMD0700F01_K16_Kabini_CPUID.txt" target="_blank">http://users.atw.hu/instlatx64/AuthenticAMD/AuthenticAMD0700F01_K16_Kabini_CPUID.txt</a> <a href="#fnref:273" class="footnote-back-ref">↩</a></p></li> <li id="fn:274"><p>IDT, WinChip 2B Processor Data Sheet, v0.9, April 1999, chapter 3.3.3, page 31. <a href="https://www.ardent-tool.com/CPU/docs/IDT_Centaur/WinChip2/w2b_datasheet.pdf" target="_blank">https://www.ardent-tool.com/CPU/docs/IDT_Centaur/WinChip2/w2b_datasheet.pdf</a> <a href="#fnref:274" class="footnote-back-ref">↩</a></p></li> <li id="fn:275"><p>VIA, PadLock Programming Guide rev. 1.66, aug 4, 2005, page 5. Archived from the original on May 26, 2010 <a href="https://web.archive.org/web/20100526054140/http://linux.via.com.tw/support/beginDownload.action?eleid=181&fid=261" target="_blank">https://web.archive.org/web/20100526054140/http://linux.via.com.tw/support/beginDownload.action?eleid=181&fid=261</a> <a href="#fnref:275" class="footnote-back-ref">↩</a></p></li> <li id="fn:276"><p>OpenEuler 1.0 LTS kernel sources, /arch/x86/include/asm/cpufeatures.h lines 147-178. Archived on Jul 30, 2023. <a href="https://gitee.com/openeuler/kernel/blob/openEuler-1.0-LTS/arch/x86/include/asm/cpufeatures.h#L147" target="_blank">https://gitee.com/openeuler/kernel/blob/openEuler-1.0-LTS/arch/x86/include/asm/cpufeatures.h#L147</a> <a href="#fnref:276" class="footnote-back-ref">↩</a></p></li> <li id="fn:277"><p>Zhaoxin, Padlock instruction set reference, 26 Dec 2024. Archived from the original on 15 Mar 2025. <a href="https://web.archive.org/web/20250315101352/https://www.zhaoxin.com/Admin/Others/DownloadsPage.aspx?nid=31&id=3202&tag=0&ref=kfzzc&t=b3f041e6f23d9f48" target="_blank">https://web.archive.org/web/20250315101352/https://www.zhaoxin.com/Admin/Others/DownloadsPage.aspx?nid=31&id=3202&tag=0&ref=kfzzc&t=b3f041e6f23d9f48</a> <a href="#fnref:277" class="footnote-back-ref">↩</a></p></li> <li id="fn:278"><p>Zhaoxin, GMI reference, 26 Dec 2024. Archived from the original on 15 Mar 2025. <a href="https://web.archive.org/web/20250315101213/https://www.zhaoxin.com/Admin/Others/DownloadsPage.aspx?nid=31&id=3152&tag=0&ref=kfzzc&t=32531cd65e657254" target="_blank">https://web.archive.org/web/20250315101213/https://www.zhaoxin.com/Admin/Others/DownloadsPage.aspx?nid=31&id=3152&tag=0&ref=kfzzc&t=32531cd65e657254</a> <a href="#fnref:278" class="footnote-back-ref">↩</a></p></li> <li id="fn:279"><p>On VIA Nehemiah and Antaur CPUs (CentaurHauls Family 6 Model 9 only),[202] bits 0,1,4,5 are used differently: Bit 0: Alternate Instruction Set (AIS) present Bit 1: AIS enabled Bit 4: LongHaul MSR (MSR 0x110A) present Bit 5: FEMMS instruction (opcode 0F 0E) present <a href="/wiki/VIA_C3#Nehemiah_cores" target="_blank">/wiki/VIA_C3#Nehemiah_cores</a> <a href="#fnref:279" class="footnote-back-ref">↩</a></p></li> <li id="fn:280"><p>On VIA Nehemiah and Antaur CPUs (CentaurHauls Family 6 Model 9 only),[202] bits 0,1,4,5 are used differently: Bit 0: Alternate Instruction Set (AIS) present Bit 1: AIS enabled Bit 4: LongHaul MSR (MSR 0x110A) present Bit 5: FEMMS instruction (opcode 0F 0E) present <a href="/wiki/VIA_C3#Nehemiah_cores" target="_blank">/wiki/VIA_C3#Nehemiah_cores</a> <a href="#fnref:280" class="footnote-back-ref">↩</a></p></li> <li id="fn:281"><p>On VIA Nehemiah and Antaur CPUs (CentaurHauls Family 6 Model 9 only),[202] bits 0,1,4,5 are used differently: Bit 0: Alternate Instruction Set (AIS) present Bit 1: AIS enabled Bit 4: LongHaul MSR (MSR 0x110A) present Bit 5: FEMMS instruction (opcode 0F 0E) present <a href="/wiki/VIA_C3#Nehemiah_cores" target="_blank">/wiki/VIA_C3#Nehemiah_cores</a> <a href="#fnref:281" class="footnote-back-ref">↩</a></p></li> <li id="fn:282"><p>On VIA Nehemiah and Antaur CPUs (CentaurHauls Family 6 Model 9 only),[202] bits 0,1,4,5 are used differently: Bit 0: Alternate Instruction Set (AIS) present Bit 1: AIS enabled Bit 4: LongHaul MSR (MSR 0x110A) present Bit 5: FEMMS instruction (opcode 0F 0E) present <a href="/wiki/VIA_C3#Nehemiah_cores" target="_blank">/wiki/VIA_C3#Nehemiah_cores</a> <a href="#fnref:282" class="footnote-back-ref">↩</a></p></li> <li id="fn:283"><p>"GCC-mirror/GCC". GitHub. 13 March 2022. <a href="https://github.com/gcc-mirror/gcc/blob/master/gcc/config/i386/cpuid.h" target="_blank">https://github.com/gcc-mirror/gcc/blob/master/gcc/config/i386/cpuid.h</a> <a href="#fnref:283" class="footnote-back-ref">↩</a></p></li> <li id="fn:284"><p>"ARM Information Center". Infocenter.arm.com. Retrieved 2013-04-11. <a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0395b/CIHCAGHH.html" target="_blank">http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0395b/CIHCAGHH.html</a> <a href="#fnref:284" class="footnote-back-ref">↩</a></p></li> <li id="fn:285"><p>IBM System/370 Principles Of Operation (PDF) (First ed.). IBM. June 1970. p. 29. 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MIPS Technologies, Inc. 2001-03-12. <a href="http://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol3.pdf" target="_blank">http://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol3.pdf</a> <a href="#fnref:288" class="footnote-back-ref">↩</a></p></li> <li id="fn:289"><p>"PowerPC Operating Environment Architecture, book III" (PDF). <a href="http://moss.csc.ncsu.edu/~mueller/cluster/ps3/SDK3.0/docs/arch/PPC_Vers202_Book3_public.pdf" target="_blank">http://moss.csc.ncsu.edu/~mueller/cluster/ps3/SDK3.0/docs/arch/PPC_Vers202_Book3_public.pdf</a> <a href="#fnref:289" class="footnote-back-ref">↩</a></p></li> <li id="fn:290"><p>"The RISC-V Instruction Set Manual Volume II: Privileged Architecture Version 1.7" (PDF). May 9, 2015. section 3.1.1. <a href="https://people.eecs.berkeley.edu/~krste/papers/riscv-priv-spec-1.7.pdf#page=23" target="_blank">https://people.eecs.berkeley.edu/~krste/papers/riscv-priv-spec-1.7.pdf#page=23</a> <a href="#fnref:290" class="footnote-back-ref">↩</a></p></li> <li id="fn:291"><p>S. Darwish, Ahmed. "[ANNOUNCE] x86-cpuid.org: A machine-readable CPUID repository". Linux Kernel Mailing List archive. Retrieved 20 July 2024. <a href="https://lore.kernel.org/lkml/ZpkckA2SHa1r3Bor@lx-t490" target="_blank">https://lore.kernel.org/lkml/ZpkckA2SHa1r3Bor@lx-t490</a> <a href="#fnref:291" class="footnote-back-ref">↩</a></p></li> </ol>