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SSE4
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<h2 id="sse4-subsets">SSE4 subsets</h2> <p>Intel SSE4 consists of 54 instructions. A subset consisting of 47 instructions, referred to as <i>SSE4.1</i> in some Intel documentation, is available in <a href="/facts/Penryn_(microarchitecture)/rjDFXcwf">Penryn</a>. Additionally, <i>SSE4.2</i>, a second subset consisting of the seven remaining instructions, is first available in <a href="/facts/Nehalem_(microarchitecture)/UPsI457h">Nehalem</a>-based <a href="/facts/Core_i7/5qT6deUr">Core i7</a>. Intel credits feedback from developers as playing an important role in the development of the instruction set. </p><p>Starting with <a href="/facts/K10_(microarchitecture)/2hQAazep">Barcelona</a>-based processors, <a href="/facts/AMD/CB1G7QTb">AMD</a> introduced the <i>SSE4a</i> instruction set, which has four SSE4 instructions and four new SSE instructions. These instructions are not found in Intel's processors supporting SSE4.1 and AMD processors only started supporting Intel's SSE4.1 and SSE4.2 (the full SSE4 instruction set) in the <a href="/facts/Bulldozer_(microarchitecture)/fUPzoGrd">Bulldozer</a>-based FX processors. With SSE4a the misaligned SSE feature was also introduced which meant unaligned load instructions were as fast as aligned versions on aligned addresses. It also allowed disabling the alignment check on non-load SSE operations accessing memory.<a class="footnote-ref" id="fnref:6" href="#fn:6"><sup>6</sup></a> Intel later introduced similar speed improvements to unaligned SSE in their Nehalem processors, but did not introduce misaligned access by non-load SSE instructions until <a href="/facts/Advanced_Vector_Extensions/znDpc6Vt">AVX</a>.<a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a> </p> <h2 id="name-confusion">Name confusion</h2> <p>What is now known as <a href="/facts/SSSE3/xlRTcz4I">SSSE3</a> (Supplemental Streaming <a href="/facts/SIMD/gQHWQSpo">SIMD</a> Extensions 3), introduced in the <a href="/facts/Intel_Core_2/9gJP9o8p">Intel Core 2</a> processor line, was referred to as SSE4 by some media until Intel came up with the SSSE3 moniker. Internally dubbed Merom New Instructions, Intel originally did not plan to assign a special name to them, which was criticized by some journalists.<a class="footnote-ref" id="fnref:8" href="#fn:8"><sup>8</sup></a> Intel eventually cleared up the confusion and reserved the SSE4 name for their next instruction set extension.<a class="footnote-ref" id="fnref:9" href="#fn:9"><sup>9</sup></a> </p><p>Intel is using the marketing term <i>HD Boost</i> to refer to SSE4.<a class="footnote-ref" id="fnref:10" href="#fn:10"><sup>10</sup></a> </p> <h2 id="new-instructions">New instructions</h2> <p>Unlike all previous iterations of SSE, SSE4 contains instructions that execute operations which are not specific to multimedia applications. It features a number of instructions whose action is determined by a constant field and a set of instructions that take XMM0 as an implicit third operand. </p><p>Several of these instructions are enabled by the single-cycle shuffle engine in Penryn. (Shuffle operations reorder bytes within a register.) </p> <h3>SSE4.1</h3> <p>These instructions were introduced with <a href="/facts/Penryn_(microarchitecture)/rjDFXcwf">Penryn microarchitecture</a>, the 45 nm shrink of Intel's <a href="/facts/Core_(microarchitecture)/fuKkuVsP">Core microarchitecture</a>. Support is indicated via the CPUID.01H:ECX.SSE41[Bit 19] flag. </p> <table><tbody><tr><th scope="col">Instruction</th><th scope="col">Description</th></tr><tr><td>MPSADBW</td><td>Compute eight offset sums of absolute differences, four at a time (i.e., |x0−y0|+|x1−y1|+|x2−y2|+|x3−y3|, |x0−y1|+|x1−y2|+|x2−y3|+|x3−y4|, ..., |x0−y7|+|x1−y8|+|x2−y9|+|x3−y10|); this operation is important for some <a href="/facts/High-definition_video/3CoUBum1">HD</a> <a href="/facts/Codec/C7b7Am8t">codecs</a>, and allows an 8×8 block difference to be computed in fewer than seven cycles.<a class="footnote-ref" id="fnref:11" href="#fn:11"><sup>11</sup></a> One bit of a three-bit immediate operand indicates whether y0 .. y10 or y4 .. y14 should be used from the destination operand, the other two whether x0..x3, x4..x7, x8..x11 or x12..x15 should be used from the source.</td></tr><tr><td>PHMINPOSUW</td><td>Sets the bottom unsigned 16-bit word of the destination to the smallest unsigned 16-bit word in the source, and the next-from-bottom to the index of that word in the source.</td></tr><tr><td>PMULDQ</td><td>Packed 32-bit signed "long" multiplication, two (1st and 3rd) out of four packed integers multiplied giving two packed 64-bit results.</td></tr><tr><td>PMULLD</td><td>Packed 32-bit signed "low" multiplication, four packed sets of integers multiplied giving four packed 32-bit results.</td></tr><tr><td>DPPS, DPPD</td><td><a href="/facts/Dot_product_instruction/L26C9A1Y">Dot product</a> for AOS (Array of Structs) data. This takes an immediate operand consisting of four (or two for DPPD) bits to select which of the entries in the input to multiply and accumulate, and another four (or two for DPPD) to select whether to put 0 or the dot-product in the appropriate field of the output.</td></tr><tr><td>BLENDPS, BLENDPD, BLENDVPS, BLENDVPD, PBLENDVB, PBLENDW</td><td>Conditional copying of elements in one location with another, based (for non-V form) on the bits in an immediate operand, and (for V form) on the bits in register XMM0.</td></tr><tr><td>PMINSB, PMAXSB, PMINUW, PMAXUW, PMINUD, PMAXUD, PMINSD, PMAXSD</td><td>Packed minimum/maximum for different integer operand types</td></tr><tr><td>ROUNDPS, ROUNDSS, ROUNDPD, ROUNDSD</td><td>Round values in a floating-point register to integers, using one of four rounding modes specified by an immediate operand</td></tr><tr><td>INSERTPS, PINSRB, PINSRD/PINSRQ, EXTRACTPS, PEXTRB, PEXTRD/PEXTRQ</td><td>The INSERTPS and PINSR instructions read 8, 16 or 32 bits from an x86 register or memory location and inserts it into a field in the destination register given by an immediate operand. EXTRACTPS and PEXTR read a field from the source register and insert it into an x86 register or memory location. For example, PEXTRD eax, [xmm0], 1; EXTRACTPS [addr+4*eax], xmm1, 1 stores the first field of xmm1 in the address given by the first field of xmm0.</td></tr><tr><td>PMOVSXBW, PMOVZXBW, PMOVSXBD, PMOVZXBD, PMOVSXBQ, PMOVZXBQ, PMOVSXWD, PMOVZXWD, PMOVSXWQ, PMOVZXWQ, PMOVSXDQ, PMOVZXDQ</td><td>Packed sign/zero extension to wider types</td></tr><tr><td>PTEST</td><td>This is similar to the TEST instruction, in that it sets the <a href="/facts/Zero_flag/HSE5Ttls">Z flag</a> to the result of an AND between its operands: ZF is set, if DEST AND SRC is equal to 0. Additionally it sets the C flag if (NOT DEST) AND SRC equals zero.<p>This is equivalent to setting the Z flag if none of the bits masked by SRC are set, and the C flag if all of the bits masked by SRC are set.</p></td></tr><tr><td>PCMPEQQ</td><td>Quadword (64 bits) compare for equality</td></tr><tr><td>PACKUSDW</td><td>Convert signed DWORDs into unsigned WORDs with saturation.</td></tr><tr><td>MOVNTDQA</td><td>Efficient read from write-combining memory area into SSE register; this is useful for retrieving results from peripherals attached to the memory bus.</td></tr></tbody></table> <h3>SSE4.2</h3> <p>SSE4.2 added STTNI (String and Text New Instructions),<a class="footnote-ref" id="fnref:12" href="#fn:12"><sup>12</sup></a> several new instructions that perform character searches and comparison on two operands of 16 bytes at a time. These were designed (among other things) to speed up the parsing of <a href="/facts/XML/clNgUfWk">XML</a> documents.<a class="footnote-ref" id="fnref:13" href="#fn:13"><sup>13</sup></a> It also added a CRC32 instruction to compute <a href="/facts/Cyclic_redundancy_check/u2exo4sv">cyclic redundancy checks</a> as used in certain data transfer protocols. These instructions were first implemented in the <a href="/facts/Nehalem_(microarchitecture)/UPsI457h">Nehalem</a>-based <a href="/facts/Intel_Core_i7/5qT6deUr">Intel Core i7</a> product line, and complete the SSE4 instruction set. AMD on the other hand first added support starting with the <a href="/facts/Bulldozer_(microarchitecture)/fUPzoGrd">Bulldozer microarchitecture</a>. Support is indicated via the CPUID.01H:ECX.SSE42[Bit 20] flag. </p><p><a href="/facts/Windows_11,_version_24H2/hJeC6AcL">Windows 11 24H2</a> requires the CPU to support SSE4.2, otherwise the Windows kernel is unbootable.<a class="footnote-ref" id="fnref:14" href="#fn:14"><sup>14</sup></a> </p> <table><tbody><tr><th scope="col">Instruction</th><th scope="col">Description</th></tr><tr><td>CRC32</td><td>Accumulate <a href="/facts/CRC32/u2exo4sv">CRC32</a>C value using the polynomial 0x11EDC6F41 (or, without the high order bit, 0x1EDC6F41).<a class="footnote-ref" id="fnref:15" href="#fn:15"><sup>15</sup></a><a class="footnote-ref" id="fnref:16" href="#fn:16"><sup>16</sup></a></td></tr><tr><td>PCMPESTRI</td><td>Packed Compare Explicit Length Strings, Return Index</td></tr><tr><td>PCMPESTRM</td><td>Packed Compare Explicit Length Strings, Return Mask</td></tr><tr><td>PCMPISTRI</td><td>Packed Compare Implicit Length Strings, Return Index</td></tr><tr><td>PCMPISTRM</td><td>Packed Compare Implicit Length Strings, Return Mask</td></tr><tr><td>PCMPGTQ</td><td>Compare Packed Signed 64-bit data For Greater Than</td></tr></tbody></table> <h3>POPCNT and LZCNT</h3> <p>These instructions operate on integer rather than SSE registers, because they are not SIMD instructions, but appear at the same time and although introduced by AMD with the SSE4a instruction set, they are counted as separate extensions with their own dedicated CPUID bits to indicate support. Intel implements POPCNT beginning with the <a href="/facts/Nehalem_(microarchitecture)/UPsI457h">Nehalem</a> microarchitecture and LZCNT beginning with the <a href="/facts/Haswell_(microarchitecture)/C19Wlzhm">Haswell</a> microarchitecture. AMD implements both, beginning with the <a href="/facts/AMD_K10/2hQAazep">Barcelona microarchitecture</a>. </p><p>AMD calls this pair of instructions <a href="/facts/Bit_Manipulation_Instruction_Sets/LJAm1LWC"><i>Advanced Bit Manipulation</i> (ABM)</a>. </p><p>The encoding of LZCNT takes the same encoding path as the encoding of the BSR (bit scan reverse) instruction. This results in an issue where LZCNT called on some CPUs not supporting it, such as Intel CPUs prior to Haswell, may incorrectly execute the BSR operation instead of raising an <i>invalid instruction</i> exception. This is an issue as the result values of LZCNT and BSR are different. </p><p>Trailing zeros can be counted using the BSF (bit scan forward) or TZCNT instructions. </p><p><a href="/facts/Windows_11,_version_24H2/hJeC6AcL">Windows 11 24H2</a> requires the CPU to support POPCNT, otherwise the Windows kernel is unbootable.<a class="footnote-ref" id="fnref:17" href="#fn:17"><sup>17</sup></a> </p> <table><tbody><tr><th scope="col">Instruction</th><th scope="col">Description</th></tr><tr><td>POPCNT</td><td><a href="/facts/Hamming_weight/dJIW7qg4">Population count</a> (count number of bits set to 1). Support is indicated via the CPUID.01H:ECX.POPCNT[Bit 23] flag.<a class="footnote-ref" id="fnref:18" href="#fn:18"><sup>18</sup></a></td></tr><tr><td>LZCNT</td><td><a href="/facts/Leading_zero_count/hBDYDy8z">Leading zero count</a>. Support is indicated via the CPUID.80000001H:ECX.ABM[Bit 5] flag.<a class="footnote-ref" id="fnref:19" href="#fn:19"><sup>19</sup></a></td></tr></tbody></table> <h3>SSE4a</h3> <p>The SSE4a instruction group was introduced in AMD's <a href="/facts/AMD_K10/2hQAazep">Barcelona microarchitecture</a>. These instructions are not available in Intel processors. Support is indicated via the CPUID.80000001H:ECX.SSE4A[Bit 6] flag.<a class="footnote-ref" id="fnref:20" href="#fn:20"><sup>20</sup></a> </p> <table><tbody><tr><th scope="col">Instruction</th><th scope="col">Description</th></tr><tr><td>EXTRQ/INSERTQ</td><td>Combined mask-shift instructions.<a class="footnote-ref" id="fnref:21" href="#fn:21"><sup>21</sup></a></td></tr><tr><td>MOVNTSD/MOVNTSS</td><td>Scalar streaming store instructions.<a class="footnote-ref" id="fnref:22" href="#fn:22"><sup>22</sup></a></td></tr></tbody></table> <h2 id="supporting-cpus">Supporting CPUs</h2> <p class="note">See also: <a href="/facts/X86-64/cyWvUFlP">X86-64 § Microarchitecture levels</a></p> <h3>X86-64 v1</h3> <ul><li><a href="/facts/Intel_Corporation/SMF0gJJX">Intel</a> <ul><li><a href="/facts/Penryn_(microarchitecture)/rjDFXcwf">Penryn</a> processors (SSE4.1 supported, except <a href="/facts/Pentium_Dual-Core/bI3RQyVv">Pentium Dual-Core</a> and <a href="/facts/Celeron/kX00LpnM">Celeron</a>)</li></ul></li> <li><a href="/facts/Advanced_Micro_Devices/CB1G7QTb">AMD</a> <ul><li><a href="/facts/Bobcat_(processor)/EweFKE9J">Bobcat-based</a> processors (SSE4a, POPCNT and LZCNT supported)</li> <li><a href="/facts/AMD_10h/2hQAazep">K10-based</a> processors (SSE4a, POPCNT and LZCNT supported)</li></ul></li></ul> <ul><li><a href="/facts/VIA_Technologies/g6REHNFE">VIA</a> <ul><li><a href="/facts/VIA_Nano/82nYJeBy">Nano</a> 3000, X2, QuadCore processors (SSE4.1 supported)</li></ul></li></ul> <h3>X86-64 v2</h3> <ul><li><a href="/facts/Intel_Corporation/SMF0gJJX">Intel</a> <ul><li>Low-power processors (SSE4.1, SSE4.2 and POPCNT supported) <ul><li><a href="/facts/Silvermont_(microarchitecture)/Ffu5eJuS">Silvermont</a> processors</li> <li><a href="/facts/Goldmont/hJSdoIJq">Goldmont</a> processors</li> <li><a href="/facts/Goldmont_Plus/4m3vxejV">Goldmont Plus</a> processors</li> <li><a href="/facts/Tremont_(microarchitecture)/wKQGk6sj">Tremont</a> processors</li></ul></li> <li><a href="/facts/Nehalem_(microarchitecture)/UPsI457h">Nehalem</a> and <a href="/facts/Westmere_(microarchitecture)/yB4HcYdY">Westmere</a> processors (SSE4.1, SSE4.2 and POPCNT supported, except <a href="/facts/Pentium/czINY469">Pentium</a> and <a href="/facts/Celeron/kX00LpnM">Celeron</a>)</li> <li><a href="/facts/Sandy_Bridge_(microarchitecture)/os1WwI9l">Sandy Bridge</a> and <a href="/facts/Ivy_Bridge_(microarchitecture)/VklHpEK1">Ivy Bridge</a> processors (SSE4.1, SSE4.2 and POPCNT supported, include <a href="/facts/Pentium/czINY469">Pentium</a> and <a href="/facts/Celeron/kX00LpnM">Celeron</a>)</li></ul></li> <li><a href="/facts/Advanced_Micro_Devices/CB1G7QTb">AMD</a> <ul><li>"Cat" low-power processors (SSE4a, SSE4.1, SSE4.2, POPCNT and LZCNT supported) <ul><li><a href="/facts/Jaguar_(microarchitecture)/PkCbNj9a">Jaguar-based</a> processors</li> <li><a href="/facts/Puma_(microarchitecture)/ujJ1MBg1">Puma-based</a> processors</li></ul></li> <li>"Heavy Equipment" processors (SSE4a, SSE4.1, SSE4.2, POPCNT and LZCNT supported) <ul><li><a href="/facts/Bulldozer_(microarchitecture)/fUPzoGrd">Bulldozer-based</a> processors</li> <li><a href="/facts/Piledriver_(microarchitecture)/Fhxly06H">Piledriver-based</a> processors<a class="footnote-ref" id="fnref:23" href="#fn:23"><sup>23</sup></a></li> <li><a href="/facts/Steamroller_(microarchitecture)/SxtLaauz">Steamroller-based</a> processors</li></ul></li></ul></li> <li><a href="/facts/VIA_Technologies/g6REHNFE">VIA</a> <ul><li><a href="/facts/VIA_Nano/82nYJeBy">Nano</a> QuadCore C4000-series processors (SSE4.1, SSE4.2 supported)</li> <li><a href="/facts/VIA_Eden/FI5wu2wE">Eden</a> X4 processors (SSE4.1, SSE4.2 supported)</li></ul></li> <li><a href="/facts/Zhaoxin/2wpVktlp">Zhaoxin</a> <ul><li>ZX-C processors and newer (SSE4.1, SSE4.2 supported)</li></ul></li></ul> <h3>X86-64 v3</h3> <ul><li><a href="/facts/Intel_Corporation/SMF0gJJX">Intel</a> <ul><li><a href="/facts/Gracemont_(microarchitecture)/we3xguWv">Gracemont</a> processors (SSE4.1, SSE4.2, POPCNT and LZCNT supported)</li> <li><a href="/facts/Haswell_(microarchitecture)/C19Wlzhm">Haswell</a> and <a href="/facts/Broadwell_(microarchitecture)/32jqNWRS">Broadwell</a> processors (SSE4.1, SSE4.2, POPCNT and LZCNT supported)</li></ul></li> <li><a href="/facts/Advanced_Micro_Devices/CB1G7QTb">AMD</a> <ul><li><a href="/facts/Excavator_(microarchitecture)/Bzj9WKGV">Excavator-based</a> processors (SSE4a, SSE4.1, SSE4.2, POPCNT and LZCNT supported)</li> <li><a href="/facts/Zen_(microarchitecture)/AjBvqDT7">Zen</a>, <a href="/facts/Zen%2B/1bJfQtRR">Zen+</a>, <a href="/facts/Zen_2/pdL7I80c">Zen 2</a>, and <a href="/facts/Zen_3/szGTAfyB">Zen 3</a> based processors (SSE4a, SSE4.1, SSE4.2, POPCNT and LZCNT supported)</li></ul></li></ul> <h3>X86-64 v4</h3> <ul><li><a href="/facts/Intel_Corporation/SMF0gJJX">Intel</a> <ul><li><a href="/facts/Skylake_(microarchitecture)/qpcDcebM">Skylake</a> processors and newer (SSE4.1, SSE4.2, POPCNT and LZCNT supported)</li></ul></li> <li><a href="/facts/Advanced_Micro_Devices/CB1G7QTb">AMD</a> <ul><li><a href="/facts/Zen_4/UJXLYNuq">Zen4-based</a> processors and newer (SSE4a, SSE4.1, SSE4.2, POPCNT and LZCNT supported)</li></ul></li></ul> <h2 id="external-links">External links</h2> <ul><li><a href="https://www.intel.com/content/dam/develop/external/us/en/documents/d9156103-705230.pdf">SSE4 Programming Reference</a> by Intel</li> <li><a href="http://halobates.de/pcmpstr-js/pcmp.html">PCMPSTR calculator for the SSE 4.2 string instructions</a> archived at <a href="https://ghostarchive.org/archive/qQEXl?kreymer=true">Ghostarchive.org</a> at May 10, 2022</li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>Intel Streaming SIMD Extensions 4 (SSE4) Instruction Set Innovation Archived May 30, 2009, at the Wayback Machine, Intel. <a href="http://www.intel.com/technology/architecture-silicon/sse4-instructions/index.htm" target="_blank">http://www.intel.com/technology/architecture-silicon/sse4-instructions/index.htm</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>Tuning for Intel SSE4 for the 45nm Next Generation Intel Core Microarchitecture Archived March 8, 2021, at the Wayback Machine, Intel. <a href="https://intel.wingateweb.com/published/BMAS005/BMAS005_100Eng.pdf" target="_blank">https://intel.wingateweb.com/published/BMAS005/BMAS005_100Eng.pdf</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>"Intel SSE4 Programming Reference" (PDF). Archived (PDF) from the original on February 15, 2020. Retrieved December 26, 2014. <a href="https://software.intel.com/sites/default/files/m/8/b/8/D9156103.pdf" target="_blank">https://software.intel.com/sites/default/files/m/8/b/8/D9156103.pdf</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>Intel Streaming SIMD Extensions 4 (SSE4) Instruction Set Innovation Archived May 30, 2009, at the Wayback Machine, Intel. <a href="http://www.intel.com/technology/architecture-silicon/sse4-instructions/index.htm" target="_blank">http://www.intel.com/technology/architecture-silicon/sse4-instructions/index.htm</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>Intel Streaming SIMD Extensions 4 (SSE4) Instruction Set Innovation Archived May 30, 2009, at the Wayback Machine, Intel. <a href="http://www.intel.com/technology/architecture-silicon/sse4-instructions/index.htm" target="_blank">http://www.intel.com/technology/architecture-silicon/sse4-instructions/index.htm</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>""Barcelona" Processor Feature: SSE Misaligned Access". AMD. Archived from the original on August 9, 2016. Retrieved March 3, 2015. <a href="https://web.archive.org/web/20160809220231/http://developer.amd.com/community/blog/2008/04/14/barcelona-processor-feature-sse-misaligned-access/" target="_blank">https://web.archive.org/web/20160809220231/http://developer.amd.com/community/blog/2008/04/14/barcelona-processor-feature-sse-misaligned-access/</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>"Inside Intel Nehalem Microarchitecture". Archived from the original on April 2, 2015. Retrieved March 3, 2015. <a href="http://www.hardwaresecrets.com/article/Inside-Intel-Nehalem-Microarchitecture/535/7" target="_blank">http://www.hardwaresecrets.com/article/Inside-Intel-Nehalem-Microarchitecture/535/7</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> <li id="fn:8"><p>My Experience With "Conroe" Archived October 15, 2013, at the Wayback Machine, DailyTech <a href="http://www.dailytech.com/article.aspx?newsid=3348" target="_blank">http://www.dailytech.com/article.aspx?newsid=3348</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></p></li> <li id="fn:9"><p>Extending the World's Most Popular Processor Architecture Archived November 24, 2011, at the Wayback Machine, Intel <a href="ftp://download.intel.com/technology/architecture/new-instructions-paper.pdf" target="_blank">ftp://download.intel.com/technology/architecture/new-instructions-paper.pdf</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></p></li> <li id="fn:10"><p>"Intel - Data Center Solutions, IOT, and PC Innovation". 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