Menu
Home Explore People Places Arts History Plants & Animals Science Life & Culture Technology
On this page
Socket FS1
CPU socket for laptop AMD CPUs

The Socket FS1 is for notebooks using AMD APU processors codenamed Llano, Trinity and Richland (Socket FS1r2).

"Llano"-branded products combine K10 with Cedar (VLIW5), UVD 3 video acceleration and AMD Eyefinity-based multi-monitor support of up to three DisplayPort monitors.

"Trinity"- and "Richland"-branded products Piledriver with Northern Islands (VLIW4), UVD 3 and VCE 1 video acceleration and AMD Eyefinity-based multi-monitor support of up to four DisplayPort monitors.

While the AMD desktop CPUs are available in a 722-pin package Socket AM1 (FS1b), it is not clear whether these desktop CPUs will be compatible with Socket FS1 or vice versa.

It is the last pin grid array socket for AMD's mobile processors - all mobile processors in microarchitectures succeeding Piledriver are exclusively available in BGA packaging, for example Steamroller-based mobile processors uses Socket FP3 socket, which is a μBGA socket. Intel also adopted same practice, starting with Broadwell microarchitecture.

Related Image Collections Add Image
Profiles
1 Image
We don't have any YouTube videos related to Socket FS1 yet.
We don't have any PDF documents related to Socket FS1 yet.
We don't have any Books related to Socket FS1 yet.
We don't have any archived web articles related to Socket FS1 yet.

Feature overview for AMD APUs

The following table shows features of AMD's processors with 3D graphics, including APUs (see also: List of AMD processors with 3D graphics).

[ VisualEditor ]
  • view
  • talk
  • edit
PlatformHigh, standard and low powerLow and ultra-low power
CodenameServerBasicToronto
MicroKyoto
DesktopPerformanceRaphaelPhoenix
MainstreamLlanoTrinityRichlandKaveriKaveri Refresh (Godavari)CarrizoBristol RidgeRaven RidgePicassoRenoirCezanne
Entry
BasicKabiniDalí
MobilePerformanceRenoirCezanneRembrandtDragon Range
MainstreamLlanoTrinityRichlandKaveriCarrizoBristol RidgeRaven RidgePicassoRenoirLucienneCezanneBarcelóPhoenix
EntryDalíMendocino
BasicDesna, Ontario, ZacateKabini, TemashBeema, MullinsCarrizo-LStoney RidgePollock
EmbeddedTrinityBald EagleMerlin Falcon,Brown FalconGreat Horned OwlGrey HawkOntario, ZacateKabiniSteppe Eagle, Crowned Eagle, LX-FamilyPrairie FalconBanded KestrelRiver Hawk
ReleasedAug 2011Oct 2012Jun 2013Jan 20142015Jun 2015Jun 2016Oct 2017Jan 2019Mar 2020Jan 2021Jan 2022Sep 2022Jan 2023Jan 2011May 2013Apr 2014May 2015Feb 2016Apr 2019Jul 2020Jun 2022Nov 2022
CPU microarchitectureK10PiledriverSteamrollerExcavator"Excavator+"1ZenZen+Zen 2Zen 3Zen 3+Zen 4BobcatJaguarPumaPuma+2"Excavator+"ZenZen+"Zen 2+"
ISAx86-64 v1x86-64 v2x86-64 v3x86-64 v4x86-64 v1x86-64 v2x86-64 v3
SocketDesktopPerformance—AM5——
Mainstream—AM4——
EntryFM1FM2FM2+FM2+3, AM4AM4—
Basic——AM1—FP5—
OtherFS1FS1+, FP2FP3FP4FP5FP6FP7FL1FP7 FP7r2 FP8FT1FT3FT3bFP4FP5FT5FP5FT6
PCI Express version2.03.04.05.04.02.03.0
CXL——
Fab. (nm)GF 32SHP(HKMG SOI)GF 28SHP(HKMG bulk)GF 14LPP(FinFET bulk)GF 12LP(FinFET bulk)TSMC N7(FinFET bulk)TSMC N6 (FinFET bulk)CCD: TSMC N5 (FinFET bulk)cIOD: TSMC N6(FinFET bulk)TSMC 4nm (FinFET bulk)TSMC N40(bulk)TSMC N28(HKMG bulk)GF 28SHP(HKMG bulk)GF 14LPP(FinFET bulk)GF 12LP(FinFET bulk)TSMC N6 (FinFET bulk)
Die area (mm2)2282462452452502104156180210CCD: (2x) 70cIOD: 12217875 (+ 28 FCH)107?125149~100
Min TDP (W)351712101565354.543.95106128
Max APU TDP (W)10095654517054182565415
Max stock APU base clock (GHz)33.84.14.13.73.83.63.73.84.03.34.74.31.752.222.23.22.61.23.352.8
Max APUs per node511
Max core dies per CPU1211
Max CCX per core die1211
Max cores per CCX482424
Max CPU6 cores per APU481682424
Max threads per CPU core1212
Integer pipeline structure3+32+24+24+2+11+3+3+1+21+1+1+12+24+24+2+1
i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHF
IOMMU7—v2v1v2
BMI1, AES-NI, CLMUL, and F16C—
MOVBE—
AVIC, BMI2, RDRAND, and MWAITX/MONITORX—
SME8, TSME9, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing——
GMET, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT——
MPK, VAES——
SGX——
FPUs per core10.5110.51
Pipes per FPU22
FPU pipe width128-bit256-bit80-bit128-bit256-bit
CPU instruction set SIMD levelSSE4a10AVXAVX2AVX-512SSSE3AVXAVX2
3DNow!3DNow!+——
PREFETCH/PREFETCHW
GFNI——
AMX—
FMA4, LWP, TBM, and XOP————
FMA3
AMD XDNA——
L1 data cache per core (KiB)64163232
L1 data cache associativity (ways)2488
L1 instruction caches per core10.5110.51
Max APU total L1 instruction cache (KiB)2561281922565122566412896128
L1 instruction cache associativity (ways)23482348
L2 caches per core10.5110.51
Max APU total L2 cache (MiB)424161212
L2 cache associativity (ways)168168
Max on-die L3 cache per CCX (MiB)—41632—4
Max 3D V-Cache per CCD (MiB)—64——
Max total in-CCD L3 cache per APU (MiB)4816644
Max. total 3D V-Cache per APU (MiB)—64——
Max. board L3 cache per APU (MiB)——
Max total L3 cache per APU (MiB)48161284
APU L3 cache associativity (ways)1616
L3 cache schemeVictimVictim
Max. L4 cache——
Max stock DRAM supportDDR3-1866DDR3-2133DDR3-2133, DDR4-2400DDR4-2400DDR4-2933DDR4-3200, LPDDR4-4266DDR5-4800, LPDDR5-6400DDR5-5200DDR5-5600, LPDDR5x-7500DDR3L-1333DDR3L-1600DDR3L-1866DDR3-1866, DDR4-2400DDR4-2400DDR4-1600DDR4-3200LPDDR5-5500
Max DRAM channels per APU21212
Max stock DRAM bandwidth (GB/s) per APU29.86634.13238.40046.93268.256102.40083.200120.00010.66612.80014.93319.20038.40012.80051.20088.000
GPU microarchitectureTeraScale 2 (VLIW5)TeraScale 3 (VLIW4)GCN 2nd genGCN 3rd genGCN 5th gen11RDNA 2RDNA 3TeraScale 2 (VLIW5)GCN 2nd genGCN 3rd gen12GCN 5th genRDNA 2
GPU instruction setTeraScale instruction setGCN instruction setRDNA instruction setTeraScale instruction setGCN instruction setRDNA instruction set
Max stock GPU base clock (MHz)60080084486611081250140021002400400538600?847900120060013001900
Max stock GPU base GFLOPS13480614.4648.1886.71134.517601971.22150.43686.4102.486???345.6460.8230.41331.2486.4
3D engine14Up to 400:20:8Up to 384:24:6Up to 512:32:8Up to 704:44:1615Up to 512:32:8768:48:8128:8:480:8:4128:8:4Up to 192:12:8Up to 192:12:4192:12:4Up to 512:?:?128:?:?
IOMMUv1IOMMUv2IOMMUv1?IOMMUv2
Video decoderUVD 3.0UVD 4.2UVD 6.0VCN 1.016VCN 2.117VCN 2.218VCN 3.1?UVD 3.0UVD 4.0UVD 4.2UVD 6.2VCN 1.0VCN 3.1
Video encoder—VCE 1.0VCE 2.0VCE 3.1—VCE 2.0VCE 3.4
AMD Fluid Motion
GPU power savingPowerPlayPowerTunePowerPlayPowerTune19
TrueAudio—20?—
FreeSync1212
HDCP21?1.42.22.3?1.42.22.3
PlayReady22—3.0 not yet—3.0 not yet
Supported displays232–32–433 (desktop)4 (mobile, embedded)42344
/drm/radeon242526——
/drm/amdgpu2728—29—30

See also

References

  1. "AMD Announces the 7th Generation APU: Excavator mk2 in Bristol Ridge and Stoney Ridge for Notebooks". 31 May 2016. Retrieved 3 January 2020. https://www.anandtech.com/show/10362/amd-7th-generation-apu-bristol-ridge-stoney-ridge-for-notebooks ↩

  2. "AMD Mobile "Carrizo" Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015" (Press release). 20 November 2014. Retrieved 16 February 2015. https://www.amd.com/en-us/press-releases/Pages/amd-mobile-carrizo-2014nov20.aspx ↩

  3. For FM2+ Excavator models: A8-7680, A6-7480 & Athlon X4 845. ↩

  4. "The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List". TechARP.com. Retrieved 13 December 2017. https://www.techarp.com/guides/mobile-cpu-comparison-guide/5/ ↩

  5. A PC would be one node. ↩

  6. An APU combines a CPU and a GPU. Both have cores. ↩

  7. Requires firmware support. ↩

  8. Requires firmware support. ↩

  9. Requires firmware support. ↩

  10. No SSE4. No SSSE3. ↩

  11. "AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver". VideoCardz.com. Retrieved 6 June 2017. http://videocardz.com/62250/amd-vega10-and-vega11-gpus-spotted-in-opencl-driver/ ↩

  12. "AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver". VideoCardz.com. Retrieved 6 June 2017. http://videocardz.com/62250/amd-vega10-and-vega11-gpus-spotted-in-opencl-driver/ ↩

  13. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation. /wiki/Single-precision_floating-point_format ↩

  14. Unified shaders : texture mapping units : render output units /wiki/Unified_shader_model ↩

  15. Cutress, Ian (1 February 2018). "Zen Cores and Vega: Ryzen APUs for AM4 – AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm". Anandtech. Retrieved 7 February 2018. https://www.anandtech.com/show/12233/amd-tech-day-at-ces-2018-roadmap-revealed-with-ryzen-apus-zen-on-12nm-vega-on-7nm/3 ↩

  16. Larabel, Michael (17 November 2017). "Radeon VCN Encode Support Lands in Mesa 17.4 Git". Phoronix. Retrieved 20 November 2017. https://www.phoronix.com/scan.php?page=news_item&px=Radeon-VCN-Encode-Lands ↩

  17. "AMD Ryzen 5000G 'Cezanne' APU Gets First High-Res Die Shots, 10.7 Billion Transistors In A 180mm2 Package". wccftech. Aug 12, 2021. Retrieved August 25, 2021. https://wccftech.com/amd-ryzen-5000g-cezanne-apu-first-high-res-die-shots-10-7-billion-transistors/ ↩

  18. "AMD Ryzen 5000G 'Cezanne' APU Gets First High-Res Die Shots, 10.7 Billion Transistors In A 180mm2 Package". wccftech. Aug 12, 2021. Retrieved August 25, 2021. https://wccftech.com/amd-ryzen-5000g-cezanne-apu-first-high-res-die-shots-10-7-billion-transistors/ ↩

  19. Tony Chen; Jason Greaves, "AMD's Graphics Core Next (GCN) Architecture" (PDF), AMD, retrieved 13 August 2016 http://meseec.ce.rit.edu/551-projects/fall2014/3-4.pdf ↩

  20. "A technical look at AMD's Kaveri architecture". Semi Accurate. Retrieved 6 July 2014. http://semiaccurate.com/2014/01/15/technical-look-amds-kaveri-architecture/ ↩

  21. To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup. ↩

  22. To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup. ↩

  23. To feed more than two displays, the additional panels must have native DisplayPort support.[10] Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed. /wiki/DisplayPort ↩

  24. DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version. /wiki/Direct_Rendering_Manager ↩

  25. Airlie, David (26 November 2009). "DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33". Retrieved 16 January 2016. http://airlied.livejournal.com/68805.html ↩

  26. "Radeon feature matrix". freedesktop.org. Retrieved 10 January 2016. http://xorg.freedesktop.org/wiki/RadeonFeature/ ↩

  27. DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version. /wiki/Direct_Rendering_Manager ↩

  28. Deucher, Alexander (16 September 2015). "XDC2015: AMDGPU" (PDF). Retrieved 16 January 2016. http://www.x.org/wiki/Events/XDC2015/Program/deucher_zhou_amdgpu.pdf ↩

  29. Michel Dänzer (17 November 2016). "[ANNOUNCE] xf86-video-amdgpu 1.2.0". lists.x.org. https://lists.x.org/archives/xorg-announce/2016-November/002741.html ↩

  30. Michel Dänzer (17 November 2016). "[ANNOUNCE] xf86-video-amdgpu 1.2.0". lists.x.org. https://lists.x.org/archives/xorg-announce/2016-November/002741.html ↩