Multi-core processor

<h2 id="terminology">Terminology</h2>
The terms multi-core and dual-core most commonly refer to some sort of <a href="/facts/Central_processing_unit/Jxp1bqMV">central processing unit</a> (CPU), but are sometimes also applied to <a href="/facts/Digital_signal_processor/YuBXweos">digital signal processors</a> (DSP) and <a href="/facts/System_on_a_chip/1RVvVe6N">system on a chip</a> (SoC). The terms are generally used only to refer to multi-core microprocessors that are manufactured on the same integrated circuit <a href="/facts/Die_(integrated_circuit)/XWvdlltE">die</a>; separate microprocessor dies in the same package are generally referred to by another name, such as <a href="/facts/Multi-chip_module/AzyVaNNp">multi-chip module</a>. This article uses the terms "multi-core" and "dual-core" for CPUs manufactured on the same integrated circuit, unless otherwise noted.
In contrast to multi-core systems, the term multi-CPU refers to multiple physically separate processing-units (which often contain special circuitry to facilitate communication between each other).
The terms <a href="/facts/Manycore_processor/ozoxeNzT">many-core</a> and massively multi-core are sometimes used to describe multi-core architectures with an especially high number of cores (tens to thousands<a class="footnote-ref" id="fnref:10" href="#fn:10">10</a>).<a class="footnote-ref" id="fnref:11" href="#fn:11">11</a>
Some systems use many <a href="/facts/Soft_microprocessor/pCmb601M">soft microprocessor</a> cores placed on a single <a href="/facts/Field-programmable_gate_array/M8LSGcAU">FPGA</a>. Each "core" can be considered a "<a href="/facts/Semiconductor_intellectual_property_core/yx66l6wL">semiconductor intellectual property core</a>" as well as a CPU core.

<h2 id="development">Development</h2>
While manufacturing technology improves, reducing the size of individual gates, physical limits of <a href="/facts/Semiconductor/zFf3mGTE">semiconductor</a>-based <a href="/facts/Microelectronics/HzCusb86">microelectronics</a> have become a major design concern. These physical limitations can cause significant heat dissipation and data synchronization problems. Various other methods are used to improve CPU performance. Some <a href="/facts/Instruction-level_parallelism/2W8qvN8K">instruction-level parallelism</a> (ILP) methods such as <a href="/facts/Superscalar/gPxRAb25">superscalar</a> <a href="/facts/Instruction_pipelining/3zy6CcX1">pipelining</a> are suitable for many applications, but are inefficient for others that contain difficult-to-predict code. Many applications are better suited to <a href="/facts/Thread-level_parallelism/z2znIYK1">thread-level parallelism</a> (TLP) methods, and multiple independent CPUs are commonly used to increase a system's overall TLP. A combination of increased available space (due to refined manufacturing processes) and the demand for increased TLP led to the development of multi-core CPUs.

<h3>Early Innovations: The Stanford Hydra Project</h3>
In the 1990s, <a href="/facts/Kunle_Olukotun/Q8qkyHdm">Kunle Olukotun</a> led the Stanford Hydra Chip Multiprocessor (CMP) research project. This initiative was among the first to demonstrate the viability of integrating multiple processors on a single chip, a concept that laid the groundwork for today's multicore processors. The Hydra project introduced support for thread-level speculation (TLS), enabling more efficient parallel execution of programs.

<h3>Commercial incentives</h3>
Several business motives drive the development of multi-core architectures. For decades, it was possible to improve performance of a CPU by shrinking the area of the integrated circuit (IC), which reduced the cost per device on the IC. Alternatively, for the same circuit area, more transistors could be used in the design, which increased functionality, especially for <a href="/facts/Complex_instruction_set_computing/Ucvyh2xq">complex instruction set computing</a> (CISC) architectures. <a href="/facts/Clock_rate/w055Woaj">Clock rates</a> also increased by orders of magnitude in the decades of the late 20th century, from several megahertz in the 1980s to several gigahertz in the early 2000s.
As the rate of clock speed improvements slowed, increased use of parallel computing in the form of multi-core processors has been pursued to improve overall processing performance. Multiple cores were used on the same CPU chip, which could then lead to better sales of CPU chips with two or more cores. For example, <a href="/facts/Intel/SMF0gJJX">Intel</a> has produced a 48-core processor for research in cloud computing; each core has an <a href="/facts/X86/Kypq5fgu">x86</a> architecture.<a class="footnote-ref" id="fnref:12" href="#fn:12">12</a><a class="footnote-ref" id="fnref:13" href="#fn:13">13</a>

<h3>Technical factors</h3>
Since computer manufacturers have long implemented <a href="/facts/Symmetric_multiprocessing/T9CahUsN">symmetric multiprocessing</a> (SMP) designs using discrete CPUs, the issues regarding implementing multi-core processor architecture and supporting it with software are well known.
Additionally:

<ul><li>Using a proven processing-core design without architectural changes reduces design risk significantly.</li>
<li>For general-purpose processors, much of the motivation for multi-core processors comes from greatly diminished gains in processor performance from increasing the <a href="/facts/Frequency_scaling/hVsx3aXI">operating frequency</a>. This is due to three primary factors:<a class="footnote-ref" id="fnref:14" href="#fn:14">14</a>
<ol><li>The memory wall; the increasing gap between processor and memory speeds. This, in effect, pushes for cache sizes to be larger in order to mask the latency of memory. This helps only to the extent that memory bandwidth is not the bottleneck in performance.</li>
<li>The ILP wall; the increasing difficulty of finding enough <a href="/facts/Instruction-level_parallelism/2W8qvN8K">parallelism in a single instruction stream</a> to keep a high-performance single-core processor busy.</li>
<li>The power wall; the trend of consuming exponentially increasing power (and thus also generating exponentially increasing heat) with each factorial increase of operating frequency. This increase can be mitigated by "<a href="/facts/Die_shrink/fgJ8nL4b">shrinking</a>" the processor by using smaller traces for the same logic. The power wall poses manufacturing, system design and deployment problems that have not been justified in the face of the diminished gains in performance due to the memory wall and ILP wall.</li></ol></li></ul>
In order to continue delivering regular performance improvements for general-purpose processors, manufacturers such as <a href="/facts/Intel/SMF0gJJX">Intel</a> and <a href="/facts/AMD/CB1G7QTb">AMD</a> have turned to multi-core designs, sacrificing lower manufacturing-costs for higher performance in some applications and systems. Multi-core architectures are being developed, but so are the alternatives. An especially strong contender for established markets is the further integration of peripheral functions into the chip.

<h3>Advantages</h3>
The proximity of multiple CPU cores on the same die allows the <a href="/facts/Cache_coherency/MhUD576q">cache coherency</a> circuitry to operate at a much higher clock rate than what is possible if the signals have to travel off-chip. Combining equivalent CPUs on a single die significantly improves the performance of <a href="/facts/Cache_snooping/NUxKS0mb">cache snoop</a> (alternative: <a href="/facts/Bus_snooping/NUxKS0mb">Bus snooping</a>) operations. Put simply, this means that <a href="/facts/Discrete_signal/RR8wpS9e">signals</a> between different CPUs travel shorter distances, and therefore those signals <a href="/facts/Degradation_(telecommunications)/90GMHHzg">degrade</a> less. These higher-quality signals allow more data to be sent in a given time period, since individual signals can be shorter and do not need to be repeated as often.
Assuming that the die can physically fit into the package, multi-core CPU designs require much less <a href="/facts/Printed_circuit_board/muSR2p43">printed circuit board</a> (PCB) space than do multi-chip <a href="/facts/Symmetric_multiprocessing/T9CahUsN">SMP</a> designs. Also, a dual-core processor uses slightly less power than two coupled single-core processors, principally because of the decreased power required to drive signals external to the chip. Furthermore, the cores share some circuitry, like the L2 cache and the interface to the <a href="/facts/Front-side_bus/LgYSB7Wl">front-side bus</a> (FSB). In terms of competing technologies for the available silicon die area, multi-core design can make use of proven CPU core library designs and produce a product with lower risk of design error than devising a new wider-core design. Also, adding more cache suffers from diminishing returns.
Multi-core chips also allow higher performance at lower energy. This can be a big factor in mobile devices that operate on batteries. Since each core in a multi-core CPU is generally more energy-efficient, the chip becomes more efficient than having a single large monolithic core. This allows higher performance with less energy. A challenge in this, however, is the additional overhead of writing parallel code.<a class="footnote-ref" id="fnref:15" href="#fn:15">15</a>

<h3>Disadvantages</h3>
Maximizing the usage of the computing resources provided by multi-core processors requires adjustments both to the <a href="/facts/Operating_system/8XTuvMh2">operating system</a> (OS) support and to existing application software. Also, the ability of multi-core processors to increase application performance depends on the use of multiple threads within applications.
Integration of a multi-core chip can lower the chip production yields. They are also more difficult to manage thermally than lower-density single-core designs. Intel has partially countered this first problem by creating its quad-core designs by combining two dual-core ones on a single die with a unified cache, hence any two working dual-core dies can be used, as opposed to producing four cores on a single die and requiring all four to work to produce a quad-core CPU. From an architectural point of view, ultimately, single CPU designs may make better use of the silicon surface area than multiprocessing cores, so a development commitment to this architecture may carry the risk of obsolescence. Finally, raw processing power is not the only constraint on system performance. Two processing cores sharing the same system bus and memory bandwidth limits the real-world performance advantage.

<h2 id="hardware">Hardware</h2>
<h3>Trends</h3>
The trend in processor development has been towards an ever-increasing number of cores, as processors with hundreds or even thousands of cores become theoretically possible.<a class="footnote-ref" id="fnref:16" href="#fn:16">16</a> In addition, multi-core chips mixed with <a href="/facts/Simultaneous_multithreading/bk8ec9yn">simultaneous multithreading</a>, memory-on-chip, and special-purpose <a href="/facts/Heterogeneous_computing/FYkECQ75">"heterogeneous"</a> (or asymmetric) cores promise further performance and efficiency gains, especially in processing multimedia, recognition and networking applications. For example, a <a href="/facts/ARM_big.LITTLE/YIWq2bWY">big.LITTLE</a> core includes a high-performance core (called 'big') and a low-power core (called 'LITTLE'). There is also a trend towards improving energy-efficiency by focusing on performance-per-watt with advanced fine-grain or ultra fine-grain <a href="/facts/Power_management/fWv2k2sP">power management</a> and dynamic <a href="/facts/Dynamic_voltage_scaling/BNbaFmEL">voltage</a> and <a href="/facts/Dynamic_frequency_scaling/lIt5XxBU">frequency scaling</a> (i.e. <a href="/facts/Laptop/3EFwTAb2">laptop</a> computers and <a href="/facts/Portable_media_player/2yHdHHKv">portable media players</a>).
Chips designed from the outset for a large number of cores (rather than having evolved from single core designs) are sometimes referred to as <a href="/facts/Manycore_processor/ozoxeNzT">manycore</a> designs, emphasising qualitative differences.

<h3>Architecture</h3>
The composition and balance of the cores in multi-core architecture show great variety. Some architectures use one core design repeated consistently ("homogeneous"), while others use a mixture of different cores, each optimized for a different, "<a href="/facts/Heterogeneous_computing/FYkECQ75">heterogeneous</a>" role.
How multiple cores are implemented and integrated significantly affects both the developer's programming skills and the consumer's expectations of apps and interactivity versus the device.<a class="footnote-ref" id="fnref:17" href="#fn:17">17</a> A device advertised as being octa-core will only have independent cores if advertised as True Octa-core, or similar styling, as opposed to being merely two sets of quad-cores each with fixed clock speeds.<a class="footnote-ref" id="fnref:18" href="#fn:18">18</a><a class="footnote-ref" id="fnref:19" href="#fn:19">19</a>
The article "CPU designers debate multi-core future" by Rick Merritt, EE Times 2008,<a class="footnote-ref" id="fnref:20" href="#fn:20">20</a> includes these comments:

<blockquote>Chuck Moore [...] suggested computers should be like cellphones, using a variety of specialty cores to run modular software scheduled by a high-level applications programming interface.
[...] Atsushi Hasegawa, a senior chief engineer at <a href="/facts/Renesas/ujhb9Dcz">Renesas</a>, generally agreed. He suggested the cellphone's use of many specialty cores working in concert is a good model for future multi-core designs.

[...] <a href="/facts/Anant_Agarwal/M5Xh8B7V">Anant Agarwal</a>, founder and chief executive of startup <a href="/facts/Tilera/hJNRnFzw">Tilera</a>, took the opposing view. He said multi-core chips need to be homogeneous collections of general-purpose cores to keep the software model simple.</blockquote>
<h2 id="software-effects">Software effects</h2>
An outdated version of an anti-virus application may create a new thread for a scan process, while its <a href="/facts/Graphical_user_interface/wBlQFWDP">GUI</a> thread waits for commands from the user (e.g. cancel the scan). In such cases, a multi-core architecture is of little benefit for the application itself due to the single thread doing all the heavy lifting and the inability to balance the work evenly across multiple cores. Programming truly multithreaded code often requires complex co-ordination of threads and can easily introduce subtle and difficult-to-find bugs due to the interweaving of processing on data shared between threads (see <a href="/facts/Thread-safety/fx3ULqUw">thread-safety</a>). Consequently, such code is much more difficult to debug than single-threaded code when it breaks. There has been a perceived lack of motivation for writing consumer-level threaded applications because of the relative rarity of consumer-level demand for maximum use of computer hardware. Also, serial tasks like decoding the <a href="/facts/Entropy_encoding/44I0n8F8">entropy encoding</a> algorithms used in <a href="/facts/Video_codec/psfSuqg7">video codecs</a> are impossible to parallelize because each result generated is used to help create the next result of the entropy decoding algorithm.
Given the increasing emphasis on multi-core chip design, stemming from the grave thermal and power consumption problems posed by any further significant increase in processor clock speeds, the extent to which software can be multithreaded to take advantage of these new chips is likely to be the single greatest constraint on computer performance in the future. If developers are unable to design software to fully exploit the resources provided by multiple cores, then they will ultimately reach an insurmountable performance ceiling.
The telecommunications market had been one of the first that needed a new design of parallel datapath packet processing because there was a very quick adoption of these multiple-core processors for the datapath and the control plane. These MPUs are going to replace<a class="footnote-ref" id="fnref:21" href="#fn:21">21</a> the traditional Network Processors that were based on proprietary <a href="/facts/Microcode/CJQUvR7T">microcode</a> or <a href="/facts/Picocode/XQEsr2X3">picocode</a>.
<a href="/facts/Parallel_programming/nQzcpzQt">Parallel programming</a> techniques can benefit from multiple cores directly. Some existing <a href="/facts/Parallel_programming_model/20l85p0g">parallel programming models</a> such as <a href="/facts/Cilk_Plus/nIftzSWW">Cilk Plus</a>, <a href="/facts/OpenMP/69IpI80o">OpenMP</a>, <a href="/facts/OpenHMPP/SULM1YzU">OpenHMPP</a>, <a href="/facts/Algorithmic_skeleton/nv5LcDId">FastFlow</a>, Skandium, <a href="/facts/Message_Passing_Interface/BEuBgDpm">MPI</a>, and <a href="/facts/Erlang_(programming_language)/2PuxmzT3">Erlang</a> can be used on multi-core platforms. Intel introduced a new abstraction for C++ parallelism called <a href="/facts/Threading_Building_Blocks/6DChhaHg">TBB</a>. Other research efforts include the <a href="/facts/Sieve_C%252B%252B_Parallel_Programming_System/pLw2bA4U">Codeplay Sieve System</a>, Cray's <a href="/facts/Chapel_(programming_language)/AwKpNMuX">Chapel</a>, Sun's <a href="/facts/Fortress_programming_language/7CYvHCCk">Fortress</a>, and IBM's <a href="/facts/X10_(programming_language)/tD3mktjx">X10</a>.
Multi-core processing has also affected the ability of modern computational software development. Developers programming in newer languages might find that their modern languages do not support multi-core functionality. This then requires the use of <a href="/facts/List_of_numerical_libraries/p5kgpwob">numerical libraries</a> to access code written in languages like <a href="/facts/C_(programming_language)/Ky2No763">C</a> and <a href="/facts/Fortran/m1KqjcMU">Fortran</a>, which perform math computations faster than newer languages like <a href="/facts/C_Sharp_(programming_language)/UC2gxeyb">C#</a>. Intel's MKL and AMD's <a href="/facts/AMD_Core_Math_Library/PYDKBF5V">ACML</a> are written in these native languages and take advantage of multi-core processing. Balancing the application workload across processors can be problematic, especially if they have different performance characteristics. There are different conceptual models to deal with the problem, for example using a coordination language and program building blocks (programming libraries or higher-order functions). Each block can have a different native implementation for each processor type. Users simply program using these abstractions and an intelligent compiler chooses the best implementation based on the context.<a class="footnote-ref" id="fnref:22" href="#fn:22">22</a>
Managing <a href="/facts/Concurrent_computing/yVzQBPr9">concurrency</a> acquires a central role in developing parallel applications. The basic steps in designing parallel applications are:

Partitioning
The partitioning stage of a design is intended to expose opportunities for parallel execution. Hence, the focus is on defining a large number of small tasks in order to yield what is termed a fine-grained decomposition of a problem.
Communication
The tasks generated by a partition are intended to execute concurrently but cannot, in general, execute independently. The computation to be performed in one task will typically require data associated with another task. Data must then be transferred between tasks so as to allow computation to proceed. This information flow is specified in the communication phase of a design.
Agglomeration
In the third stage, development moves from the abstract toward the concrete. Developers revisit decisions made in the partitioning and communication phases with a view to obtaining an algorithm that will execute efficiently on some class of parallel computer. In particular, developers consider whether it is useful to combine, or agglomerate, tasks identified by the partitioning phase, so as to provide a smaller number of tasks, each of greater size. They also determine whether it is worthwhile to replicate data and computation.
Mapping
In the fourth and final stage of the design of parallel algorithms, the developers specify where each task is to execute. This mapping problem does not arise on uniprocessors or on shared-memory computers that provide automatic task scheduling.
On the other hand, on the <a href="/facts/Server-side/JqukWyaA">server side</a>, multi-core processors are ideal because they allow many users to connect to a site simultaneously and have independent <a href="/facts/Thread_(computer_science)/hh8WHyPd">threads</a> of execution. This allows for Web servers and application servers that have much better <a href="/facts/Throughput/6zAUsXqw">throughput</a>.

<h3>Licensing</h3>
Vendors may license some software "per processor". This can give rise to ambiguity, because a "processor" may consist either of a single core or of a combination of cores.

<ul><li>Initially, for some of its enterprise software, <a href="/facts/Microsoft/nGIDDXdx">Microsoft</a> continued to use a per-<a href="/facts/CPU_socket/ndWcsnq6">socket</a> licensing system. However, for some software such as <a href="/facts/BizTalk/GxsfTH6e">BizTalk Server 2013</a>, <a href="/facts/Microsoft_SQL_Server/eCdt2JBL">SQL Server 2014</a>, and <a href="/facts/Windows_Server_2016/LBMMCjYC">Windows Server 2016</a>, Microsoft has shifted to per-core licensing.<a class="footnote-ref" id="fnref:23" href="#fn:23">23</a></li>
<li><a href="/facts/Oracle_Corporation/0z14FygH">Oracle Corporation</a> counts an AMD X2 or an Intel dual-core CPU as a single processor but uses other metrics for other types, especially for processors with more than two cores.<a class="footnote-ref" id="fnref:24" href="#fn:24">24</a></li></ul>
<h2 id="embedded-applications">Embedded applications</h2>

<a href="/facts/Embedded_computing/a4muX1wU">Embedded computing</a> operates in an area of processor technology distinct from that of "mainstream" PCs. The same technological drives towards multi-core apply here too. Indeed, in many cases the application is a "natural" fit for multi-core technologies, if the task can easily be partitioned between the different processors.
In addition, embedded software is typically developed for a specific hardware release, making issues of <a href="/facts/Software_portability/tWKVGCBb">software portability</a>, legacy code or supporting independent developers less critical than is the case for PC or enterprise computing. As a result, it is easier for developers to adopt new technologies and as a result there is a greater variety of multi-core processing architectures and suppliers.

<h2 id="network-processors">Network processors</h2>
As of 2010, multi-core <a href="/facts/Network_processors/SW5Lv8UM">network processors</a> have become mainstream, with companies such as <a href="/facts/Freescale_Semiconductor/mRjBBbeX">Freescale Semiconductor</a>, <a href="/facts/Cavium_Networks/JYaGIL4Y">Cavium Networks</a>, Wintegra and <a href="/facts/Broadcom/pbh0q7ht">Broadcom</a> all manufacturing products with eight processors. For the system developer, a key challenge is how to exploit all the cores in these devices to achieve maximum networking performance at the system level, despite the performance limitations inherent in a <a href="/facts/Symmetric_multiprocessing/T9CahUsN">symmetric multiprocessing</a> (SMP) operating system. Companies such as <a href="/facts/6WIND/xvj1m8NC">6WIND</a> provide portable packet processing software designed so that the networking data plane runs in a fast path environment outside the operating system of the network device.<a class="footnote-ref" id="fnref:25" href="#fn:25">25</a>

<h2 id="digital-signal-processing">Digital signal processing</h2>
In <a href="/facts/Digital_signal_processing/PEG7azr8">digital signal processing</a> the same trend applies: <a href="/facts/Texas_Instruments/88NUhuHF">Texas Instruments</a> has the three-core TMS320C6488 and four-core TMS320C5441, <a href="/facts/Freescale/mRjBBbeX">Freescale</a> the four-core MSC8144 and six-core MSC8156 (and both have stated they are working on eight-core successors). Newer entries include the Storm-1 family from <a href="https://web.archive.org/web/20101210220716/http://www.streamprocessors.com/streamprocessors/Home.html">Stream Processors, Inc</a> with 40 and 80 general purpose ALUs per chip, all programmable in C as a SIMD engine and <a href="/facts/Picochip/LEhWDMG1">Picochip</a> with 300 processors on a single die, focused on communication applications.

<h2 id="heterogeneous-systems">Heterogeneous systems</h2>
In <a href="/facts/Heterogeneous_computing/FYkECQ75">heterogeneous computing</a>, where a system uses more than one kind of processor or cores, multi-core solutions are becoming more common: <a href="/facts/Xilinx/rbXfxqqG">Xilinx</a> Zynq UltraScale+ MPSoC has a quad-core ARM Cortex-A53 and dual-core ARM Cortex-R5. Software solutions such as OpenAMP are being used to help with inter-processor communication.
Mobile devices may use the <a href="/facts/ARM_big.LITTLE/YIWq2bWY">ARM big.LITTLE</a> architecture.

<h2 id="hardware-examples">Hardware examples</h2>

<h3>Commercial</h3>
<ul><li><a href="/facts/Adapteva/AcrgoDAm">Adapteva</a> Epiphany, a many-core processor architecture which allows up to 4096 processors on-chip, although only a 16-core version has been commercially produced.</li>
<li>Aeroflex Gaisler <a href="/facts/LEON/AT23bfmM">LEON3</a>, a multi-core <a href="/facts/SPARC/m7KhEtET">SPARC</a> that also exists in a <a href="/facts/LEON/AT23bfmM">fault-tolerant version</a>.</li>
<li><a href="/facts/Ageia/zHH7oytF">Ageia</a> <a href="/facts/PhysX/FabGhdvx">PhysX</a>, a multi-core <a href="/facts/Physics_processing_unit/cay9UPA0">physics processing unit</a>.</li>
<li><a href="/facts/Ambric/esGgccfU">Ambric</a> Am2045, a 336-core <a href="/facts/Massively_parallel_processor_array/GXJQ6fGS">massively parallel processor array</a> (MPPA)</li>
<li><a href="/facts/Advanced_Micro_Devices/CB1G7QTb">AMD</a>
<ul><li><a href="/facts/AMD_Accelerated_Processing_Unit/hdApEUQw">A-Series</a>, dual-, triple-, and quad-core of Accelerated Processor Units (APU).</li>
<li><a href="/facts/Athlon_64_FX/3JLpVnQd">Athlon 64 FX</a> and <a href="/facts/Athlon_64_X2/aB8h01HY">Athlon 64 X2</a> single- and dual-core desktop processors.</li>
<li><a href="/facts/Athlon_II/5HNz5k86">Athlon II</a>, dual-, triple-, and quad-core desktop processors.</li>
<li><a href="/facts/AMD_FX/uPMHuACf">FX-Series</a>, quad-, 6-, and 8-core desktop processors.</li>
<li><a href="/facts/Opteron/IF1ueyIJ">Opteron</a>, single-, dual-, quad-, 6-, 8-, 12-, and 16-core server/workstation processors.</li>
<li><a href="/facts/AMD_Phenom/TaGxakcd">Phenom</a>, dual-, triple-, and quad-core processors.</li>
<li><a href="/facts/Phenom_II/6YW9Nnz9">Phenom II</a>, dual-, triple-, quad-, and 6-core desktop processors.</li>
<li><a href="/facts/Sempron/hk5blISe">Sempron</a>, single-, dual-, and quad-core entry level processors.<a class="footnote-ref" id="fnref:26" href="#fn:26">26</a></li>
<li><a href="/facts/AMD_Turion/CNf3tLud">Turion</a>, single- and dual-core laptop processors.</li>
<li><a href="/facts/Ryzen/0hKNcAra">Ryzen</a>, dual-, quad-, 6-, 8-, 12-, 16-, 24-, 32-, and 64-core desktop, mobile, and embedded platform processors.</li>
<li><a href="/facts/Epyc/5d30N0BK">Epyc</a>, quad-, 8-, 12-, 16-, 24-, 32-, and 64-core server and embedded processors.</li>
<li><a href="/facts/Radeon/U6y80fWr">Radeon</a> and <a href="/facts/AMD_FireStream/SknXMN6C">FireStream</a> GPU/<a href="/facts/GPGPU/roBwsPY2">GPGPU</a>.</li></ul></li>
<li>Analog Devices <a href="/facts/Blackfin/9pc3fLf8">Blackfin</a> BF561, a symmetrical dual-core processor</li>
<li><a href="/facts/ARM_architecture/SALsYA79">ARM</a> MPCore is a fully synthesizable multi-core container for <a href="/facts/ARM11_MPCore/RBYoh2hU">ARM11 MPCore</a> and <a href="/facts/ARM_Cortex-A9_MPCore/7frBGbbK">ARM Cortex-A9 MPCore</a> processor cores, intended for high-performance embedded and entertainment applications.</li>
<li><a href="/facts/ASOCS/JPauPtlw">ASOCS</a> ModemX, up to 128 cores, wireless applications.</li>
<li><a href="/facts/Azul_Systems/WQwozozw">Azul Systems</a>
<ul><li>Vega 1, a 24-core processor, released in 2005.</li>
<li>Vega 2, a 48-core processor, released in 2006.</li>
<li>Vega 3, a 54-core processor, released in 2008.</li></ul></li>
<li>Broadcom
<ul><li>SiByte SB1250, SB1255, SB1455</li>
<li>BCM2836, BCM2837, BCM2710 and BCM2711 quad-core ARM SoC (designed for different <a href="/facts/Raspberry_Pi/Ie6Lx9n5">Raspberry Pi</a> models)</li></ul></li>
<li>Cadence Design Systems <a href="/facts/Tensilica/PkKN657D">Tensilica</a> Xtensa LX6, available in a dual-core configuration in <a href="/facts/Espressif_Systems/QWDp3psY">Espressif Systems</a>'s <a href="/facts/ESP32/gW5SX9df">ESP32</a></li>
<li><a href="/facts/ClearSpeed/7Got5VGk">ClearSpeed</a>
<ul><li>CSX700, 192-core processor, released in 2008 (32/64-bit floating point; Integer ALU).</li></ul></li>
<li>Cradle Technologies CT3400 and CT3600, both multi-core DSPs.</li>
<li><a href="/facts/Cavium_Networks/JYaGIL4Y">Cavium Networks</a> Octeon, a 32-core <a href="/facts/MIPS_architecture/efV4KgK4">MIPS</a> MPU.</li>
<li><a href="http://www.coherentlogix.com/">Coherent Logix</a> <a href="http://www.coherentlogix.com/products/hyperx-processors/">hx3100 Processor</a>, a 100-core DSP/GPP processor.</li>
<li><a href="/facts/Freescale_Semiconductor/mRjBBbeX">Freescale Semiconductor</a> QorIQ series processors, up to 8 cores, <a href="/facts/Power_ISA/GLy1WS0m">Power ISA</a> <a href="/facts/Manycore_processor/ozoxeNzT">MPU</a>.</li>
<li>Hewlett-Packard <a href="/facts/PA-8800/f5sE1Izr">PA-8800</a> and <a href="/facts/PA-8900/f5sE1Izr">PA-8900</a>, dual core <a href="/facts/PA-RISC/gjDs1HEh">PA-RISC</a> processors.</li>
<li><a href="/facts/IBM/QszA7nwd">IBM</a>
<ul><li><a href="/facts/POWER4/dBBnIW7g">POWER4</a>, a dual-core <a href="/facts/PowerPC/DqmM9y50">PowerPC</a> processor, released in 2001.</li>
<li><a href="/facts/POWER5/bvj1ELch">POWER5</a>, a dual-core PowerPC processor, released in 2004.</li>
<li><a href="/facts/POWER6/GqfSuMVM">POWER6</a>, a dual-core PowerPC processor, released in 2007.</li>
<li><a href="/facts/POWER7/GKnhcYKC">POWER7</a>, a 4, 6 and 8-core PowerPC processor, released in 2010.</li>
<li><a href="/facts/POWER8/kokdP5VT">POWER8</a>, a 12-core PowerPC processor, released in 2013.</li>
<li><a href="/facts/POWER9/1xMKJHsX">POWER9</a>, a 12 or 24-core PowerPC processor, released in 2017.</li>
<li><a href="/facts/Power10/rJcQsWeR">Power10</a>, a 15 or 30-core PowerPC processor, released in 2021.</li>
<li><a href="/facts/PowerPC_970/nRyX1JxX">PowerPC 970</a>MP, a dual-core PowerPC processor, used in the Apple <a href="/facts/Power_Mac_G5/DfREoJlg">Power Mac G5</a>.</li>
<li><a href="/facts/Xenon_(processor)/W8u6cvA2">Xenon</a>, a triple-core, <a href="/facts/Simultaneous_multithreading/bk8ec9yn">SMT</a>-capable, PowerPC microprocessor used in the Microsoft <a href="/facts/Xbox_360/dYlE3mL5">Xbox 360</a> game console.</li>
<li><a href="/facts/IBM_z10/wqrYKC7C">z10</a>, a quad-core <a href="/facts/Z%2fArchitecture/FcKYkGn9">z/Architecture</a> processor, released in 2008.</li>
<li><a href="/facts/IBM_z196/Fwmwz4uu">z196</a>, a quad-core z/Architecture processor, released in 2010.</li>
<li><a href="/facts/IBM_zEC12_(microprocessor)/YbGjYcWL">zEC12</a>, a six-core z/Architecture processor, released in 2012.</li>
<li><a href="/facts/IBM_z13_(microprocessor)/IADWWL7U">z13</a>, an eight-core z/Architecture processor, released in 2015.</li>
<li><a href="/facts/IBM_z14_(microprocessor)/k4TR73g0">z14</a>, a ten-core z/Architecture processor, released in 2017.</li>
<li><a href="/facts/IBM_z15_(microprocessor)/V7NBwPB5">z15</a>, a twelve-core z/Architecture processor, released in 2019.</li>
<li><a href="/facts/IBM_Telum_(microprocessor)/8Bes12cz">Telum</a>, an eight-core z/Architecture processor, released in 2021.</li></ul></li>
<li><a href="/facts/Infineon/LAAXwhcC">Infineon</a>
<ul><li><a href="/facts/Infineon_AURIX/ARHsXdF4">AURIX</a></li>
<li>Danube, a dual-core, MIPS-based, <a href="/facts/Home_gateway/sgQeFhbD">home gateway</a> processor.</li></ul></li>
<li><a href="/facts/Intel/SMF0gJJX">Intel</a>
<ul><li><a href="/facts/Intel_Atom/1rB5zJyz">Atom</a>, single, dual-core, quad-core, 8-, 12-, and 16-core processors for <a href="/facts/Netbook/aExm3tmc">netbooks</a>, <a href="/facts/Nettop/mJYFkQg4">nettops</a>, embedded applications, and <a href="/facts/Mobile_Internet_device/WsbHtJBR">mobile internet devices</a> (MIDs).<a class="footnote-ref" id="fnref:27" href="#fn:27">27</a></li>
<li><a href="/facts/Atom_(system_on_chip)/CJDxJ6Ve">Atom SoC (system on a chip)</a>, single-core, dual-core, and quad-core processors for smartphones and tablets.<a class="footnote-ref" id="fnref:28" href="#fn:28">28</a></li>
<li><a href="/facts/Celeron/kX00LpnM">Celeron</a>, the first dual-core (and, later, quad-core) processor for the budget/entry-level market.<a class="footnote-ref" id="fnref:29" href="#fn:29">29</a><a class="footnote-ref" id="fnref:30" href="#fn:30">30</a></li>
<li><a href="/facts/Core_Duo/lwa8VSdT">Core Duo</a>, a dual-core processor.<a class="footnote-ref" id="fnref:31" href="#fn:31">31</a></li>
<li><a href="/facts/Core_2_Duo/lwa8VSdT">Core 2 Duo</a>, a dual-core processor.<a class="footnote-ref" id="fnref:32" href="#fn:32">32</a></li>
<li><a href="/facts/Core_2_Quad/lwa8VSdT">Core 2 Quad</a>, 2 dual-core dies packaged in a multi-chip module.<a class="footnote-ref" id="fnref:33" href="#fn:33">33</a></li>
<li><a href="/facts/Core_i3/WzEJtfJd">Core i3</a>, <a href="/facts/Core_i5/YYnBYKoR">Core i5</a>, <a href="/facts/Core_i7/5qT6deUr">Core i7</a> and <a href="/facts/List_of_Intel_Core_i9_microprocessors/k1CmRVss">Core i9</a>, a family of dual-, quad-, 6-, 8-, 10-, 12-, 14-, 16-, and 18-core processors, and the successor of the <a href="/facts/Core_2_Duo/lwa8VSdT">Core 2 Duo</a> and the <a href="/facts/Core_2_Quad/lwa8VSdT">Core 2 Quad</a>.<a class="footnote-ref" id="fnref:34" href="#fn:34">34</a></li>
<li><a href="/facts/Itanium/0wkjSDpe">Itanium</a>, single, dual-core, quad-core, and 8-core processors.<a class="footnote-ref" id="fnref:35" href="#fn:35">35</a></li>
<li><a href="/facts/Pentium/czINY469">Pentium</a>, single, dual-core, and quad-core processors for the entry-level market.<a class="footnote-ref" id="fnref:36" href="#fn:36">36</a></li>
<li><a href="/facts/Teraflops_Research_Chip/fp2yVaKM">Teraflops Research Chip</a> (Polaris), a 3.16 GHz, 80-core processor prototype, which the company originally stated would be released by 2011.<a class="footnote-ref" id="fnref:37" href="#fn:37">37</a></li>
<li><a href="/facts/Xeon/j1M8Hp6D">Xeon</a> dual-, quad-, 6-, 8-, 10-, 12-, 14-, 15-, 16-, 18-, 20-, 22-, 24-, 26-, 28-, 32-, 48-, and 56-core processors.<a class="footnote-ref" id="fnref:38" href="#fn:38">38</a><a class="footnote-ref" id="fnref:39" href="#fn:39">39</a><a class="footnote-ref" id="fnref:40" href="#fn:40">40</a><a class="footnote-ref" id="fnref:41" href="#fn:41">41</a><a class="footnote-ref" id="fnref:42" href="#fn:42">42</a><a class="footnote-ref" id="fnref:43" href="#fn:43">43</a></li>
<li><a href="/facts/Intel_MIC/Fv5dhyKc">Xeon Phi</a> 57-, 60-, 61-, 64-, 68-, and 72-core processors.<a class="footnote-ref" id="fnref:44" href="#fn:44">44</a><a class="footnote-ref" id="fnref:45" href="#fn:45">45</a></li></ul></li>
<li>IntellaSys
<ul><li>SEAforth 40C18, a 40-core processor.<a class="footnote-ref" id="fnref:46" href="#fn:46">46</a></li>
<li>SEAforth24, a 24-core processor designed by <a href="/facts/Charles_H._Moore/9rsgu4PF">Charles H. Moore</a>.</li></ul></li>
<li><a href="/facts/Kalray/I59JrMsS">Kalray</a>
<ul><li>MPPA-256, 256-core processor, released 2012 (256 usable VLIW cores, Network-on-Chip (NoC), 32/64-bit IEEE 754 compliant FPU)</li></ul></li>
<li>NetLogic Microsystems
<ul><li>XLP, a 32-core, quad-threaded <a href="/facts/MIPS64/efV4KgK4">MIPS64</a> processor.</li>
<li>XLR, an eight-core, quad-threaded MIPS64 processor.</li>
<li>XLS, an eight-core, quad-threaded MIPS64 processor.</li></ul></li>
<li><a href="/facts/Samsung_Electronics/STxnmHwl">Samsung Electronics</a>
<ul><li><a href="/facts/Samsung_Exynos/VSMI3vDf">Samsung Exynos</a></li></ul></li>
<li><a href="/facts/Nvidia/8QfCgqbu">Nvidia</a>
<ul><li><a href="/facts/GeForce_30_series/nu7rYwhJ">RTX 3090</a> (128 SM cores, 10496 CUDA cores;<a class="footnote-ref" id="fnref:47" href="#fn:47">47</a> plus other more specialized cores).</li></ul></li>
<li><a href="/facts/Parallax_Propeller/KkCzK2jL">Parallax Propeller P8X32</a>, an eight-core <a href="/facts/Microcontroller/MKrnAhnm">microcontroller</a>.</li>
<li><a href="/facts/PicoChip/LEhWDMG1">picoChip</a> PC200 series 200–300 cores per device for DSP & wireless.</li>
<li><a href="/facts/Plurality_(company)/I5JNmEMz">Plurality</a> HAL series tightly coupled 16-256 cores, L1 shared memory, hardware synchronized processor.</li>
<li>Rapport <a href="/facts/Kilocore/ypdHePbm">Kilocore</a> KC256, a 257-core microcontroller with a PowerPC core and 256 8-bit "processing elements".</li>
<li>Raspberry Pi Ltd. <a href="/facts/RP2040/NoFyG2Yf">RP2040</a>, a dual <a href="/facts/ARM_Cortex-M0%252B/prW99nkV">ARM Cortex-M0+</a> microcontroller</li>
<li><a href="/facts/SiCortex/c4xKl81k">SiCortex</a> "SiCortex node" has six MIPS64 cores on a single chip.</li>
<li><a href="/facts/SiFive/MnPxjdWI">SiFive</a>
<ul><li>U74 includes 4 cores</li></ul></li>
<li><a href="/facts/Sony/7x4tCtBd">Sony</a>/<a href="/facts/IBM/QszA7nwd">IBM</a>/<a href="/facts/Toshiba/QHRaw8Tr">Toshiba</a>'s <a href="/facts/Cell_(microprocessor)/p2MIQjMc">Cell</a> processor, a nine-core processor with one general purpose <a href="/facts/PowerPC/DqmM9y50">PowerPC</a> core and eight specialized SPUs (Synergistic Processing Unit) optimized for vector operations used in the Sony <a href="/facts/PlayStation_3/obhuo97V">PlayStation 3</a>.</li>
<li><a href="/facts/Sun_Microsystems/VJ9EzEFd">Sun Microsystems</a>
<ul><li><a href="/facts/MAJC/jWodknUB">MAJC</a> 5200, two-core VLIW processor.</li>
<li><a href="/facts/UltraSPARC_IV/lNkFf4ms">UltraSPARC IV</a> and UltraSPARC IV+, dual-core processors.</li>
<li><a href="/facts/UltraSPARC_T1/mfxg7MjI">UltraSPARC T1</a>, an eight-core, 32-thread processor.</li>
<li><a href="/facts/UltraSPARC_T2/GEuRGo8t">UltraSPARC T2</a>, an eight-core, 64-concurrent-thread processor.</li>
<li><a href="/facts/UltraSPARC_T3/DWJgEvyL">UltraSPARC T3</a>, a sixteen-core, 128-concurrent-thread processor.</li>
<li><a href="/facts/SPARC_T4/kTyoPJnW">SPARC T4</a>, an eight-core, 64-concurrent-thread processor.</li>
<li><a href="/facts/SPARC_T5/Pco2qWFe">SPARC T5</a>, a sixteen-core, 128-concurrent-thread processor.</li></ul></li>
<li>Sunway
<ul><li><a href="/facts/Sunway_SW26010/g8xjmW9I">Sunway SW26010</a>, a 260-core processor used in the <a href="/facts/Sunway_TaihuLight/7TLEatpK">Sunway TaihuLight</a>.</li></ul></li>
<li><a href="/facts/Texas_Instruments/88NUhuHF">Texas Instruments</a>
<ul><li><a href="/facts/Texas_Instruments_TMS320/ILsPTHCJ">TMS320C80 MVP</a>, a five-core multimedia video processor.</li>
<li>TMS320TMS320C66, 2-, 4-, 8-core DSP.</li></ul></li>
<li><a href="/facts/Tilera/hJNRnFzw">Tilera</a>
<ul><li><a href="/facts/TILE64/RHhjYnWb">TILE64</a>, a 64-core 32-bit processor.</li>
<li><a href="/facts/TILE-Gx/92TpGJ1r">TILE-Gx</a>, a 72-core 64-bit processor.</li></ul></li>
<li>XMOS <a href="/facts/Software_Defined_Silicon/QluHmnd6">Software Defined Silicon</a> quad-core XS1-G4.</li></ul>
<h3>Free</h3>
<ul><li><a href="/facts/OpenSPARC/6cokbgCP">OpenSPARC</a></li></ul>
<h3>Academic</h3>
<ul><li><a href="/facts/Stanford/JEQeF9z2">Stanford</a>, 4-core Hydra processor<a class="footnote-ref" id="fnref:48" href="#fn:48">48</a></li>
<li><a href="/facts/MIT/Xk49vNA8">MIT</a>, 16-core <a href="http://groups.csail.mit.edu/cag/raw/">RAW</a> processor</li>
<li><a href="/facts/University_of_California%2c_Davis/LTCyhaP5">University of California, Davis</a>, <a href="/facts/Asynchronous_array_of_simple_processors/beVk7CXa">Asynchronous array of simple processors</a> (AsAP)
<ul><li>36-core 610 MHz <a href="/facts/Asynchronous_array_of_simple_processors/beVk7CXa">AsAP</a></li>
<li>167-core 1.2 GHz <a href="/facts/Asynchronous_array_of_simple_processors/beVk7CXa">AsAP2</a></li></ul></li>
<li><a href="/facts/University_of_Washington/36PG6qkG">University of Washington</a>, <a href="http://wavescalar.cs.washington.edu/">Wavescalar</a> processor</li>
<li><a href="/facts/University_of_Texas%2c_Austin/6NApstxT">University of Texas, Austin</a>, <a href="/facts/TRIPS_architecture/tzQ3Dd5L">TRIPS</a> processor</li>
<li><a href="/facts/Link%25C3%25B6ping_University/VMySqUQe">Linköping University</a>, Sweden, ePUMA processor</li>
<li><a href="/facts/UC_Davis/LTCyhaP5">UC Davis</a>, Kilocore, a 1000 core 1.78 GHz processor on a 32 nm IBM process<a class="footnote-ref" id="fnref:49" href="#fn:49">49</a></li></ul>
<h2 id="benchmarks">Benchmarks</h2>
The research and development of multicore processors often compares many options, and benchmarks are developed to help such evaluations. Existing benchmarks include SPLASH-2, PARSEC, and COSMIC for heterogeneous systems.<a class="footnote-ref" id="fnref:50" href="#fn:50">50</a>

<h2 id="see-also">See also</h2>

<ul><li><a href="/facts/CPU_shielding/sKkC5IdY">CPU shielding</a></li>
<li><a href="/facts/CUDA/fvPpolot">CUDA</a></li>
<li><a href="/facts/GPGPU/roBwsPY2">GPGPU</a></li>
<li><a href="/facts/Hyper-threading/hjqGgK8V">Hyper-threading</a></li>
<li><a href="/facts/Manycore_processor/ozoxeNzT">Manycore processor</a></li>
<li><a href="/facts/Multicore_Association/Qoyzl0l2">Multicore Association</a></li>
<li><a href="/facts/Computer_multitasking/Q4acPNMv">Multitasking</a></li>
<li><a href="/facts/OpenCL/ns8y6np7">OpenCL</a> (Open Computing Language) – a framework for heterogeneous execution</li>
<li><a href="/facts/Parallel_random_access_machine/G1pCFgWP">Parallel random access machine</a></li>
<li><a href="/facts/Partitioned_global_address_space/wE3AwgJL">Partitioned global address space</a> (PGAS)</li>
<li><a href="/facts/Race_condition/bvNpgy4F">Race condition</a></li>
<li><a href="/facts/Thread_(computer_science)/hh8WHyPd">Thread</a></li></ul>

<h2 id="notes">Notes</h2>
<ol><li>^ <a href="/facts/Digital_signal_processor/YuBXweos">Digital signal processors</a> (DSPs) have used multi-core architectures for much longer than high-end general-purpose processors. A typical example of a DSP-specific implementation would be a combination of a <a href="/facts/Reduced_instruction_set_computing/aQbGM62p">RISC</a> CPU and a DSP <a href="/facts/Microprocessor/Fx9CaQht">MPU</a>. This allows for the design of products that require a general-purpose processor for user interfaces and a DSP for real-time data processing; this type of design is common in <a href="/facts/Mobile_phone/H3EcqD9h">mobile phones</a>. In other applications, a growing number of companies have developed multi-core DSPs with very large numbers of processors.</li>
<li>^ Two types of <a href="/facts/Operating_system/8XTuvMh2">operating systems</a> are able to use a dual-CPU multiprocessor: partitioned multiprocessing and <a href="/facts/Symmetric_multiprocessing/T9CahUsN">symmetric multiprocessing</a> (SMP). In a partitioned architecture, each CPU boots into separate segments of physical memory and operate independently; in an SMP OS, processors work in a shared space, executing threads within the OS independently.</li></ol>

<h2 id="further-reading">Further reading</h2>
<ul><li>Khondker S. Hasan; Nicolas G. Grounds; John K. Antonio (July 2011). Predicting CPU Availability of a Multi-core Processor Executing Concurrent Java Threads. 17th International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA-11). Las Vegas, Nevada, USA. pp. 551–557. <a href="/facts/Hdl_(identifier)/rdebSxmC">hdl</a>:<a href="https://hdl.handle.net/10657.1%2F2440">10657.1/2440</a>.</li>
<li>Khondker S. Hasan; John Antonio; Sridhar Radhakrishnan (February 2014). A New Composite CPU/Memory Model for Predicting Efficiency of Multi-core Processing. The 20th IEEE International Conference on High Performance Computer Architecture (HPCA-14) workshop. Orlando, FL, USA. <a href="/facts/Doi_(identifier)/muM9Etpq">doi</a>:<a href="https://doi.org/10.13140%2FRG.2.1.3051.9207">10.13140/RG.2.1.3051.9207</a>.</li></ul>
<h2 id="external-links">External links</h2>
<ul><li><a href="http://www.makeuseof.com/tag/processor-core-makeuseof-explains-2/">"What Is a Processor Core?"</a>—MakeUseOf</li>
<li><a href="https://web.archive.org/web/20110424130713/http://embedded-computing.com/embedded-moves-multicore">"Embedded moves to multicore"</a>—Embedded Computing Design</li>
<li><a href="https://spectrum.ieee.org/multicore-is-bad-news-for-supercomputers">"Multicore Is Bad News for Supercomputers"</a>—<a href="/facts/IEEE_Spectrum/tmbdcCq5">IEEE Spectrum</a></li>
<li><a href="https://www.slideshare.net/Talbott/architecting-solutions-for-the-manycore-future">Architecting solutions for the Manycore future</a>, published on Feb 19, 2010 (more than one dead link in the slide)</li></ul>

<h2 id="references">References</h2>

<ol>
<li id="fn:1">Rouse, Margaret (March 27, 2007). "Definition: multi-core processor". TechTarget. Archived from the original on August 5, 2010. Retrieved March 6, 2013. <a href="https://web.archive.org/web/20100805052158/http://searchdatacenter.techtarget.com/sDefinition/0,,sid80_gci1015740,00.html" target="_blank">https://web.archive.org/web/20100805052158/http://searchdatacenter.techtarget.com/sDefinition/0,,sid80_gci1015740,00.html</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></li>
<li id="fn:2">Schauer, Bryan. "Multicore Processors – A Necessity" (PDF). Archived from the original (PDF) on 2011-11-25. <a href="https://web.archive.org/web/20111125035151/http://www.csa.com/discoveryguides/multicore/review.pdf" target="_blank">https://web.archive.org/web/20111125035151/http://www.csa.com/discoveryguides/multicore/review.pdf</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></li>
<li id="fn:3">Smith, Ryan. "NVIDIA Announces the GeForce RTX 30 Series: Ampere For Gaming, Starting With RTX 3080 & RTX 3090". www.anandtech.com. Retrieved 2020-09-15. <a href="https://www.anandtech.com/show/16057/nvidia-announces-the-geforce-rtx-30-series-ampere-for-gaming-starting-with-rtx-3080-rtx-3090" target="_blank">https://www.anandtech.com/show/16057/nvidia-announces-the-geforce-rtx-30-series-ampere-for-gaming-starting-with-rtx-3080-rtx-3090</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></li>
<li id="fn:4">"Sunway TaihuLight - Sunway MPP, Sunway SW26010 260C 1.45GHz, Sunway | TOP500". www.top500.org. Retrieved 2020-09-15. <a href="https://www.top500.org/system/178764/" target="_blank">https://www.top500.org/system/178764/</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></li>
<li id="fn:5">Suleman, Aater (May 20, 2011). "What makes parallel programming hard?". FutureChips. Archived from the original on May 29, 2011. Retrieved March 6, 2013. <a href="https://web.archive.org/web/20110529133159/http://www.futurechips.org/tips-for-power-coders/parallel-programming.html" target="_blank">https://web.archive.org/web/20110529133159/http://www.futurechips.org/tips-for-power-coders/parallel-programming.html</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></li>
<li id="fn:6">Duran, A (2011). "Ompss: a proposal for programming heterogeneous multi-core architectures". Parallel Processing Letters. 21 (2): 173–193. doi:10.1142/S0129626411000151. <a href="/wiki/Doi_(identifier)" target="_blank">/wiki/Doi_(identifier)</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></li>
<li id="fn:7">"Definition of dual core". PCMAG. Retrieved 2023-10-27. <a href="https://www.pcmag.com/encyclopedia/term/dual-core" target="_blank">https://www.pcmag.com/encyclopedia/term/dual-core</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></li>
<li id="fn:8">"Intel taking its six-core processors mainstream in 2018 with Coffee Lake family". ZDNET. Retrieved 2023-10-27. <a href="https://www.zdnet.com/article/intel-taking-its-six-core-processors-mainstream-in-2018-with-coffee-lake-family/" target="_blank">https://www.zdnet.com/article/intel-taking-its-six-core-processors-mainstream-in-2018-with-coffee-lake-family/</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></li>
<li id="fn:9">Alan Dexter (2022-04-05). "Six-core CPUs are now more popular than quad-core chips on Steam". PC Gamer. Retrieved 2024-05-22. <a href="https://www.pcgamer.com/six-core-cpus-are-now-more-popular-than-quad-core-chips-on-steam/" target="_blank">https://www.pcgamer.com/six-core-cpus-are-now-more-popular-than-quad-core-chips-on-steam/</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></li>
<li id="fn:10">Schor, David (November 2017). "The 2,048-core PEZY-SC2 sets a Green500 record". WikiChip. <a href="https://fuse.wikichip.org/news/191/the-2048-core-pezy-sc2-sets-a-green500-record/" target="_blank">https://fuse.wikichip.org/news/191/the-2048-core-pezy-sc2-sets-a-green500-record/</a> <a href="#fnref:10" class="footnote-back-ref">↩</a></li>
<li id="fn:11">Vajda, András (2011-06-10). Programming Many-Core Chips. Springer. p. 3. ISBN 978-1-4419-9739-5. <a href="978-1-4419-9739-5" target="_blank">978-1-4419-9739-5</a> <a href="#fnref:11" class="footnote-back-ref">↩</a></li>
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<li id="fn:24">Compare:
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<li id="fn:25">"6WINDGATE Software: Network Optimization Software – SDN Software – Control Plane Software | 6WIND". <a href="http://www.6wind.com/products/6windgate/" target="_blank">http://www.6wind.com/products/6windgate/</a> <a href="#fnref:25" class="footnote-back-ref">↩</a></li>
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</ol>

Multi-core processor open-in-new

Multi-core processor