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Logic gate
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<h2 id="history-and-development">History and development</h2> <p>The <a href="/facts/Binary_number_system/a6JDSRPs">binary number system</a> was refined by <a href="/facts/Gottfried_Wilhelm_Leibniz/cTc2er83">Gottfried Wilhelm Leibniz</a> (published in 1705), influenced by the ancient <i><a href="/facts/I_Ching/jfEBTfKo">I Ching</a></i>'s binary system.<a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a><a class="footnote-ref" id="fnref:8" href="#fn:8"><sup>8</sup></a> Leibniz established that using the binary system combined the principles of <a href="/facts/Arithmetic/hvHwkbMV">arithmetic</a> and <a href="/facts/Logic/8JnpJLtt">logic</a>. </p><p>The <a href="/facts/Analytical_engine/Ts9xduLI">analytical engine</a> devised by <a href="/facts/Charles_Babbage/T3jklQcd">Charles Babbage</a> in 1837 used mechanical logic gates based on gears.<a class="footnote-ref" id="fnref:9" href="#fn:9"><sup>9</sup></a> </p><p>In an 1886 letter, <a href="/facts/Charles_Sanders_Peirce/z76dNqhM">Charles Sanders Peirce</a> described how logical operations could be carried out by electrical switching circuits.<a class="footnote-ref" id="fnref:10" href="#fn:10"><sup>10</sup></a> Early <a href="/facts/Electromechanical_computer/4TvyCu8c">Electromechanical computers</a> were constructed from <a href="/facts/Switch/vqbNDgYm">switches</a> and <a href="/facts/Relay_logic/eEs4FXVn">relay logic</a> rather than the later innovations of <a href="/facts/Vacuum_tube/VHd1BNLq">vacuum tubes</a> (thermionic valves) or <a href="/facts/Transistor/Bmr8zwL0">transistors</a> (from which later electronic computers were constructed). <a href="/facts/Ludwig_Wittgenstein/wN9bAgMz">Ludwig Wittgenstein</a> introduced a version of the 16-row <a href="/facts/Truth_table/4KsmArDW">truth table</a> as proposition 5.101 of <i><a href="/facts/Tractatus_Logico-Philosophicus/rSWRMIBg">Tractatus Logico-Philosophicus</a></i> (1921). <a href="/facts/Walther_Bothe/sUnzEYxY">Walther Bothe</a>, inventor of the <a href="/facts/Coincidence_circuit/QHy3BNm7">coincidence circuit</a>,<a class="footnote-ref" id="fnref:11" href="#fn:11"><sup>11</sup></a> got part of the 1954 <a href="/facts/Nobel_Prize/3z1Y3oFL">Nobel Prize</a> in physics, for the first modern electronic AND gate in 1924. <a href="/facts/Konrad_Zuse/yrvbaEg3">Konrad Zuse</a> designed and built electromechanical logic gates for his computer <a href="/facts/Z1_(computer)/LDe34zlW">Z1</a> (from 1935 to 1938). </p><p>From 1934 to 1936, <a href="/facts/NEC/YnlUsMBA">NEC</a> engineer <a href="/facts/Akira_Nakashima/vxyCyhfX">Akira Nakashima</a>, <a href="/facts/Claude_Shannon/EremsCws">Claude Shannon</a> and <a href="/facts/Victor_Shestakov/HkLyIgCu">Victor Shestakov</a> introduced <a href="/facts/Switching_circuit_theory/6ogJWSyx">switching circuit theory</a> in a series of papers showing that <a href="/facts/Two-element_Boolean_algebra/8nIWUpwd">two-valued</a> <a href="/facts/Boolean_algebra/VkCToAmg">Boolean algebra</a>, which they discovered independently, can describe the operation of switching circuits.<a class="footnote-ref" id="fnref:12" href="#fn:12"><sup>12</sup></a><a class="footnote-ref" id="fnref:13" href="#fn:13"><sup>13</sup></a><a class="footnote-ref" id="fnref:14" href="#fn:14"><sup>14</sup></a><a class="footnote-ref" id="fnref:15" href="#fn:15"><sup>15</sup></a> Using this property of electrical switches to implement logic is the fundamental concept that underlies all electronic digital <a href="/facts/Computer/SQe1aK05">computers</a>. Switching circuit theory became the foundation of <a href="/facts/Digital_circuit/vWgfC29C">digital circuit</a> design, as it became widely known in the electrical engineering community during and after <a href="/facts/World_War_II/2efV5L1U">World War II</a>, with theoretical rigor superseding the <i>ad hoc</i> methods that had prevailed previously.<a class="footnote-ref" id="fnref:16" href="#fn:16"><sup>16</sup></a> </p><p>In 1948, <a href="/facts/John_Bardeen/kbj763Fh">Bardeen</a> and <a href="/facts/Walter_Houser_Brattain/zjTKLjpA">Brattain</a> patented an insulated-gate transistor (IGFET) with an inversion layer. Their concept forms the basis of CMOS technology today.<a class="footnote-ref" id="fnref:17" href="#fn:17"><sup>17</sup></a> In 1957 Frosch and Derick were able to manufacture <a href="/facts/PMOS_logic/DWmuIrcn">PMOS</a> and <a href="/facts/NMOS_logic/6hup3T21">NMOS</a> planar gates.<a class="footnote-ref" id="fnref:18" href="#fn:18"><sup>18</sup></a> Later a team at Bell Labs demonstrated a working MOS with PMOS and NMOS gates.<a class="footnote-ref" id="fnref:19" href="#fn:19"><sup>19</sup></a> Both types were later combined and adapted into <a href="/facts/Complementary_MOS/NJIWYgBl">complementary MOS</a> (CMOS) logic by <a href="/facts/Chih-Tang_Sah/FB1gaIkg">Chih-Tang Sah</a> and <a href="/facts/Frank_Wanlass/KH8KerJI">Frank Wanlass</a> at <a href="/facts/Fairchild_Semiconductor/TUD8v4P0">Fairchild Semiconductor</a> in 1963.<a class="footnote-ref" id="fnref:20" href="#fn:20"><sup>20</sup></a> </p> <h2 id="symbols">Symbols</h2> <p>There are two sets of symbols for elementary logic gates in common use, both defined in <a href="/facts/ANSI/p3d1TQCb">ANSI</a>/<a href="/facts/IEEE/UddC4pUW">IEEE</a> Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives from <a href="/facts/United_States_Military_Standard/Y7a53qCL">United States Military Standard</a> MIL-STD-806 of the 1950s and 1960s.<a class="footnote-ref" id="fnref:21" href="#fn:21"><sup>21</sup></a> It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.<a class="footnote-ref" id="fnref:22" href="#fn:22"><sup>22</sup></a> The IEC standard, <a href="/facts/IEC/zRXRn5Lu">IEC</a> 60617-12, has been adopted by other standards, such as <a href="/facts/European_Committee_for_Standardization/BwwUrMgy">EN</a> 60617-12:1999 in Europe, <a href="/facts/British_Standard/BI8HMUjL">BS</a> EN 60617-12:1999 in the United Kingdom, and <a href="/facts/DIN/BGemsWax">DIN</a> EN 60617-12:1998 in Germany. </p><p>The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor. </p><p>IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.<a class="footnote-ref" id="fnref:23" href="#fn:23"><sup>23</sup></a> These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another. </p><p>In the 1980s, schematics were the predominant method to design both <a href="/facts/Circuit_boards/muSR2p43">circuit boards</a> and custom ICs known as <a href="/facts/Gate_array/NsnPf9c0">gate arrays</a>. Today custom ICs and the <a href="/facts/Field-programmable_gate_array/M8LSGcAU">field-programmable gate array</a> are typically designed with <a href="/facts/Hardware_description_language/g19KvKCu">Hardware Description Languages</a> (HDL) such as <a href="/facts/Verilog/efVqbKXg">Verilog</a> or <a href="/facts/VHDL/H6Exdjfs">VHDL</a>. </p> <table><tbody><tr><th>Type</th><th>Distinctive shape(IEEE Std 91/91a-1991)</th><th>Rectangular shape(IEEE Std 91/91a-1991)(IEC 60617-12:1997)</th><th><a href="/facts/Boolean_algebra/VkCToAmg">Boolean algebra</a> between A and B</th><th><a href="/facts/Truth_table/4KsmArDW">Truth table</a></th></tr><tr><th colspan="5">Single-input gates</th></tr><tr><td><a href="/facts/Buffer_gate/BEFPzgF3">Buffer</a></td><td></td><td></td><td> A {\displaystyle {A}} </td><td><table><tbody><tr><td>Input</td><td>Output</td></tr><tr><td>A</td><td>Q</td></tr><tr><td>0</td><td>0</td></tr><tr><td>1</td><td>1</td></tr></tbody></table></td></tr><tr><td><a href="/facts/NOT_gate/pGk3qGTI">NOT</a>(inverter)</td><td></td><td></td><td> A ¯ {\displaystyle {\overline {A}}} or ¬ A {\displaystyle \neg A} </td><td><table><tbody><tr><td>Input</td><td>Output</td></tr><tr><td>A</td><td>Q</td></tr><tr><td>0</td><td>1</td></tr><tr><td>1</td><td>0</td></tr></tbody></table></td></tr><tr><td colspan="5">In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a <i>bubble</i> and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the <i>positive logic convention</i> or <i>negative logic convention</i> is being used (high voltage level = 1 or low voltage level = 1, respectively). The <i>wedge</i> is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called <i>Direct Polarity Indication</i>. See IEEE Std 91/91A and IEC 60617-12. Both the <i>bubble</i> and the <i>wedge</i> can be used on distinctive-shape and <a href="/facts/Rectangular/mdLfIGKA">rectangular</a>-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the <i>bubble</i> is meaningful.</td></tr><tr><th colspan="5"><a href="/facts/Logical_conjunction/62uyyn1d">Conjunction</a> and <a href="/facts/Disjunction/jbI2EGlM">disjunction</a></th></tr><tr><td><a href="/facts/AND_gate/tVKQD0w1">AND</a></td><td></td><td></td><td> A ⋅ B {\displaystyle A\cdot B} or A ∧ B {\displaystyle A\land B} </td><td><table><tbody><tr><td colspan="2">Input</td><td>Output</td></tr><tr><td>A</td><td>B</td><td>Q</td></tr><tr><td>0</td><td>0</td><td>0</td></tr><tr><td>0</td><td>1</td><td>0</td></tr><tr><td>1</td><td>0</td><td>0</td></tr><tr><td>1</td><td>1</td><td>1</td></tr></tbody></table></td></tr><tr><td><a href="/facts/OR_gate/ox2lHgIM">OR</a></td><td></td><td></td><td> A + B {\displaystyle A+B} or A ∨ B {\displaystyle A\lor B} </td><td><table><tbody><tr><td colspan="2">Input</td><td>Output</td></tr><tr><td>A</td><td>B</td><td>Q</td></tr><tr><td>0</td><td>0</td><td>0</td></tr><tr><td>0</td><td>1</td><td>1</td></tr><tr><td>1</td><td>0</td><td>1</td></tr><tr><td>1</td><td>1</td><td>1</td></tr></tbody></table></td></tr><tr><th colspan="5"><a href="/facts/Alternative_denial/rpXH07u4">Alternative denial</a> and <a href="/facts/Joint_denial/HKhNW8Qc">joint denial</a></th></tr><tr><td><a href="/facts/NAND_gate/g6FUuhJT">NAND</a></td><td></td><td></td><td> A ⋅ B ¯ {\displaystyle {\overline {A\cdot B}}} or A ↑ B {\displaystyle A\uparrow B} </td><td><table><tbody><tr><td colspan="2">Input</td><td>Output</td></tr><tr><td>A</td><td>B</td><td>Q</td></tr><tr><td>0</td><td>0</td><td>1</td></tr><tr><td>0</td><td>1</td><td>1</td></tr><tr><td>1</td><td>0</td><td>1</td></tr><tr><td>1</td><td>1</td><td>0</td></tr></tbody></table></td></tr><tr><td><a href="/facts/NOR_gate/3l3MqaMI">NOR</a></td><td></td><td></td><td> A + B ¯ {\displaystyle {\overline {A+B}}} or A ↓ B {\displaystyle A\downarrow B} </td><td><table><tbody><tr><td colspan="2">Input</td><td>Output</td></tr><tr><td>A</td><td>B</td><td>Q</td></tr><tr><td>0</td><td>0</td><td>1</td></tr><tr><td>0</td><td>1</td><td>0</td></tr><tr><td>1</td><td>0</td><td>0</td></tr><tr><td>1</td><td>1</td><td>0</td></tr></tbody></table></td></tr><tr><th colspan="5"><a href="/facts/Exclusive_or/FHyr7hGQ">Exclusive or</a> and <a href="/facts/Biconditional/AghYtFSh">biconditional</a></th></tr><tr><td><a href="/facts/XOR_gate/WSfdqTcA">XOR</a></td><td></td><td></td><td> A ⊕ B {\displaystyle A\oplus B} or A ⊻ B {\displaystyle A\veebar B} </td><td><table><tbody><tr><td colspan="2">Input</td><td>Output</td></tr><tr><td>A</td><td>B</td><td>Q</td></tr><tr><td>0</td><td>0</td><td>0</td></tr><tr><td>0</td><td>1</td><td>1</td></tr><tr><td>1</td><td>0</td><td>1</td></tr><tr><td>1</td><td>1</td><td>0</td></tr></tbody></table></td></tr><tr><td colspan="5">The output of a two input exclusive-OR is true only when the two input values are <i>different</i>, and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol.</td></tr><tr><td><a href="/facts/XNOR/LW793PwY">XNOR</a></td><td></td><td></td><td> A ⊕ B ¯ {\displaystyle {\overline {A\oplus B}}} or A ⊙ B {\displaystyle {A\odot B}} </td><td><table><tbody><tr><td colspan="2">Input</td><td>Output</td></tr><tr><td>A</td><td>B</td><td>Q</td></tr><tr><td>0</td><td>0</td><td>1</td></tr><tr><td>0</td><td>1</td><td>0</td></tr><tr><td>1</td><td>0</td><td>0</td></tr><tr><td>1</td><td>1</td><td>1</td></tr></tbody></table></td></tr><tr><th colspan="5"><a href="/facts/Material_conditional/hYf4b7AE">Implication</a> and <a href="/facts/Material_nonimplication/a3MtvWGl">Nonimplication</a></th></tr><tr><td><a href="/facts/IMPLY/kpHxqy4J">IMPLY</a><a class="footnote-ref" id="fnref:24" href="#fn:24"><sup>24</sup></a><a class="footnote-ref" id="fnref:25" href="#fn:25"><sup>25</sup></a></td><td></td><td></td><td> A ¯ + B {\displaystyle {\overline {A}}+B} or A → B {\displaystyle A\rightarrow B} </td><td><table><tbody><tr><td colspan="2">Input</td><td>Output</td></tr><tr><td>A</td><td>B</td><td>Q</td></tr><tr><td>0</td><td>0</td><td>1</td></tr><tr><td>0</td><td>1</td><td>1</td></tr><tr><td>1</td><td>0</td><td>0</td></tr><tr><td>1</td><td>1</td><td>1</td></tr></tbody></table></td></tr><tr><td><a href="/facts/NIMPLY/wUPhuHVV">NIMPLY</a></td><td></td><td></td><td> A ⋅ B ¯ {\displaystyle A\cdot {\overline {B}}} or A ↛ B {\displaystyle A\nrightarrow B} </td><td><table><tbody><tr><td colspan="2">Input</td><td>Output</td></tr><tr><td>A</td><td>B</td><td>Q</td></tr><tr><td>0</td><td>0</td><td>0</td></tr><tr><td>0</td><td>1</td><td>0</td></tr><tr><td>1</td><td>0</td><td>1</td></tr><tr><td>1</td><td>1</td><td>0</td></tr></tbody></table></td></tr><tr><td colspan="5">IMPLY and NIMPLY are not <a href="/facts/Commutative/WaYxJLxd">commutative</a>, meaning that changing the order of the operands may change the result. For instance, A → B ¯ {\displaystyle A\rightarrow {\overline {B}}} is false, but A ¯ → B {\displaystyle {\overline {A}}\rightarrow B} is true; likewise, A ↛ B ¯ {\displaystyle A\nrightarrow {\overline {B}}} is true, but A ¯ ↛ B {\displaystyle {\overline {A}}\nrightarrow B} is false.</td></tr></tbody></table> <h2 id="de-morgan-equivalent-symbols">De Morgan equivalent symbols</h2> <p>By use of <a href="/facts/De_Morgan%2527s_laws/dj3F8xpt">De Morgan's laws</a>, an <i>AND</i> function is identical to an <i>OR</i> function with negated inputs and outputs. Likewise, an <i>OR</i> function is identical to an <i>AND</i> function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. </p><p>This leads to an alternative set of symbols for basic gates that use the opposite core symbol (<i>AND</i> or <i>OR</i>) but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated. </p><p>A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor. </p><p>De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons. </p> <h2 id="truth-tables">Truth tables</h2> <p>Output comparison of various logic gates: </p> 1-input logic gates<table><tbody><tr><td colspan="1">Input</td><td colspan="2">Output</td></tr><tr><td>A</td><td>Buffer</td><td>Inverter</td></tr><tr><td>0</td><td>0</td><td>1</td></tr><tr><td>1</td><td>1</td><td>0</td></tr></tbody></table> 2-input logic gates<table><tbody><tr><td colspan="2">Input</td><td colspan="8">Output</td></tr><tr><td>A</td><td>B</td><td>AND</td><td>NAND</td><td>OR</td><td>NOR</td><td>XOR</td><td>XNOR</td><td>IMPLY</td><td>NIMPLY</td></tr><tr><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td></tr><tr><td>0</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td></tr><tr><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td></tr><tr><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td></tr></tbody></table> <h2 id="universal-logic-gates">Universal logic gates</h2> <p class="note">Further information on the theoretical basis: <a href="/facts/Functional_completeness/ncyHAsHH">Functional completeness</a></p> <p><a href="/facts/Charles_Sanders_Peirce/z76dNqhM">Charles Sanders Peirce</a> (during 1880–1881) showed that <a href="/facts/NOR_logic/GhHdKb4q">NOR gates alone</a> (or alternatively <a href="/facts/NAND_logic/ye1XC5Ac">NAND gates alone</a>) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.<a class="footnote-ref" id="fnref:26" href="#fn:26"><sup>26</sup></a> The first published proof was by <a href="/facts/Henry_M._Sheffer/YF8RpQKG">Henry M. Sheffer</a> in 1913, so the NAND logical operation is sometimes called <i><a href="/facts/Sheffer_stroke/rpXH07u4">Sheffer stroke</a></i>; the <a href="/facts/Logical_NOR/HKhNW8Qc">logical NOR</a> is sometimes called <i><a href="/facts/Peirce%2527s_arrow/HKhNW8Qc">Peirce's arrow</a></i>.<a class="footnote-ref" id="fnref:27" href="#fn:27"><sup>27</sup></a> Consequently, these gates are sometimes called <i>universal logic gates</i>.<a class="footnote-ref" id="fnref:28" href="#fn:28"><sup>28</sup></a> </p> <table><tbody><tr><th>type</th><th>NAND construction</th><th>NOR construction</th></tr><tr><td>NOT</td><td></td><td></td></tr><tr><td>AND</td><td></td><td></td></tr><tr><td>NAND</td><td></td><td></td></tr><tr><td>OR</td><td></td><td></td></tr><tr><td>NOR</td><td></td><td></td></tr><tr><td>XOR</td><td></td><td></td></tr><tr><td>XNOR</td><td></td><td></td></tr><tr><td>IMPLY</td><td></td><td></td></tr><tr><td>NIMPLY</td><td></td><td></td></tr></tbody></table> <h2 id="data-storage-and-sequential-logic">Data storage and sequential logic</h2> <p class="note">Main article: <a href="/facts/Sequential_logic/Rcs4thlu">Sequential logic</a></p> <p>Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "<a href="/facts/Latch_(electronics)/vA99xjM7">latch</a>" circuit. Latching circuitry is used in <a href="/facts/Static_random-access_memory/Pmyo4V5e">static random-access memory</a>. More complicated designs that use <a href="/facts/Clock_signal/9UfTzGHx">clock signals</a> and that change only on a rising or falling edge of the clock are called edge-triggered "<a href="/facts/Flip-flop_(electronics)/vA99xjM7">flip-flops</a>". Formally, a flip-flop is called a <a href="/facts/Bistable_circuit/vA99xjM7">bistable circuit</a>, because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, to store a multiple-bit value, is known as a register. When using any of these gate setups the overall system has memory; it is then called a <a href="/facts/Sequential_logic/Rcs4thlu">sequential logic</a> system since its output can be influenced by its previous state(s), i.e. by the <i>sequence</i> of input states. In contrast, the output from <a href="/facts/Combinational_logic/L1kaaVK5">combinational logic</a> is purely a combination of its present inputs, unaffected by the previous input and output states. </p><p>These logic circuits are used in computer <a href="/facts/Computer_memory/hQKVQ51J">memory</a>. They vary in performance, based on factors of <a href="/facts/Speed/I3qgMPfs">speed</a>, complexity, and reliability of storage, and many different types of designs are used based on the application. </p> <h2 id="manufacturing">Manufacturing</h2> <p class="note">See also: <a href="/facts/Unconventional_computing/XkJjTK0a">Unconventional computing</a> and <a href="/facts/Semiconductor_device_fabrication/Jd23Mu1z">Semiconductor device fabrication</a></p> <h3>Electronic gates</h3> <p>A <a href="/facts/Functionally_complete/ncyHAsHH">functionally complete</a> logic system may be composed of <a href="/facts/Relay/NQcb9usW">relays</a>, <a href="/facts/Thermionic_valve/VHd1BNLq">valves</a> (vacuum tubes), or <a href="/facts/Transistor/Bmr8zwL0">transistors</a>. </p><p>Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-<a href="/facts/Gain_(electronics)/CWbehg27">gain</a> <a href="/facts/Voltage/EN2po6N2">voltage</a> <a href="/facts/Amplifier/pnRgxncC">amplifier</a>, which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate. </p> <p>For small-scale logic, designers now use prefabricated logic gates from families of devices such as the <a href="/facts/Transistor%25E2%2580%2593transistor_logic/z4bvHotl">TTL</a> <a href="/facts/7400_series/mDqHhWyc">7400 series</a> by <a href="/facts/Texas_Instruments/88NUhuHF">Texas Instruments</a>, the <a href="/facts/CMOS/NJIWYgBl">CMOS</a> <a href="/facts/4000_series/x505SAg7">4000 series</a> by <a href="/facts/RCA/NWyjNN6R">RCA</a>, and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by <a href="/facts/Programmable_logic_device/7dIVypm9">programmable logic devices</a>, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of <a href="/facts/Programmable_logic_device/7dIVypm9">programmable logic devices</a> such as <a href="/facts/FPGA/M8LSGcAU">FPGAs</a> has reduced the 'hard' property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed. </p><p>An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered. </p><p>The output of one gate can only drive a finite number of inputs to other gates, a number called the '<a href="/facts/Fan-out/lCm5joyw">fan-out</a> limit'. Also, there is always a delay, called the '<a href="/facts/Propagation_delay/tUcrAwwe">propagation delay</a>', from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed <a href="/facts/Synchronous_circuit/k3yddBIN">synchronous circuits</a>. Additional delay can be caused when many inputs are connected to an output, due to the distributed <a href="/facts/Capacitance/0pH046TL">capacitance</a> of all the inputs and wiring and the finite amount of current that each output can provide. </p> <h4>Logic families</h4> <p class="note">Main article: <a href="/facts/Logic_family/QlEgIecX">Logic family</a></p> <p>There are several <a href="/facts/Logic_families/QlEgIecX">logic families</a> with different characteristics (power consumption, speed, cost, size) such as: <a href="/facts/Diode_logic/vV8MehjW">RDL</a> (resistor–diode logic), <a href="/facts/Resistor%25E2%2580%2593transistor_logic/V9JGuspy">RTL</a> (resistor-transistor logic), <a href="/facts/DTL/DmLg6WBK">DTL</a> (diode–transistor logic), <a href="/facts/Transistor%25E2%2580%2593transistor_logic/z4bvHotl">TTL</a> (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors. </p><p>The simplest family of logic gates uses <a href="/facts/Bipolar_transistors/9BMcGv5Q">bipolar transistors</a>, and is called <a href="/facts/Resistor%25E2%2580%2593transistor_logic/V9JGuspy">resistor–transistor logic</a> (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early <a href="/facts/Integrated_circuit/fjn6vg7C">integrated circuits</a>. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in <a href="/facts/Diode%25E2%2580%2593transistor_logic/DmLg6WBK">diode–transistor logic</a> (DTL). <a href="/facts/Transistor%25E2%2580%2593transistor_logic/z4bvHotl">Transistor–transistor logic</a> (TTL) then supplanted DTL. </p> <p>As integrated circuits became more complex, bipolar transistors were replaced with smaller <a href="/facts/Field-effect_transistor/TerYC6Nz">field-effect transistors</a> (<a href="/facts/MOSFET/eTDJT2Km">MOSFETs</a>); see <a href="/facts/PMOS_logic/DWmuIrcn">PMOS</a> and <a href="/facts/NMOS_logic/6hup3T21">NMOS</a>. To reduce power consumption still further, most contemporary chip implementations of digital systems now use <a href="/facts/CMOS/NJIWYgBl">CMOS</a> logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation. </p><p>Other types of logic gates include, but are not limited to:<a class="footnote-ref" id="fnref:29" href="#fn:29"><sup>29</sup></a> </p> <table><tbody><tr><th>Logic family</th><th>Abbreviation</th><th>Description</th></tr><tr><td><a href="/facts/Diode_logic/vV8MehjW">Diode logic</a></td><td>DL</td><td></td></tr><tr><td>Tunnel diode logic</td><td>TDL</td><td>Exactly the same as diode logic but can perform at a higher speed.</td></tr><tr><td>Neon logic</td><td>NL</td><td>Uses neon bulbs or 3-element neon trigger tubes to perform logic.</td></tr><tr><td>Core diode logic</td><td>CDL</td><td>Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level.</td></tr><tr><td>4Layer Device Logic</td><td>4LDL</td><td>Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required.</td></tr><tr><td><a href="/facts/Direct-coupled_transistor_logic/sMeWoLDX">Direct-coupled transistor logic</a></td><td>DCTL</td><td>Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic.</td></tr><tr><td><a href="/facts/Metal%25E2%2580%2593oxide%25E2%2580%2593semiconductor/eTDJT2Km">Metal–oxide–semiconductor</a> logic</td><td>MOS</td><td>Uses <a href="/facts/MOSFET/eTDJT2Km">MOSFETs</a> (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes <a href="/facts/PMOS_logic/DWmuIrcn">PMOS logic</a>, <a href="/facts/NMOS_logic/6hup3T21">NMOS logic</a>, <a href="/facts/Complementary_MOS/NJIWYgBl">complementary MOS</a> (CMOS), and <a href="/facts/BiCMOS/RF6LspQ0">BiCMOS</a> (bipolar CMOS).</td></tr><tr><td><a href="/facts/Current-mode_logic/nBzkH5vL">Current-mode logic</a></td><td>CML</td><td>Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels.</td></tr><tr><td><a href="/facts/Quantum_dot_cellular_automaton/4fLjbAwL">Quantum-dot cellular automata</a></td><td>QCA</td><td>Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds.</td></tr><tr><td>Ferroelectric FET</td><td>FeFET</td><td>FeFET transistors can retain their state to speed recovery in case of a power loss.<a class="footnote-ref" id="fnref:30" href="#fn:30"><sup>30</sup></a></td></tr></tbody></table> <h4>Three-state logic gates</h4> <p class="note">Main article: <a href="/facts/Three-state_logic/SD6wXHNN">Three-state logic</a></p> <p>A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on <a href="/facts/Bus_(computing)/R45TKwS7">buses</a> of the <a href="/facts/CPU/Jxp1bqMV">CPU</a> to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a <a href="/facts/Multiplexer/lVro0Sfz">multiplexer</a>, which may be physically distributed over separate devices or plug-in cards. </p><p>In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit. </p> <h3>Non-electronic logic gates</h3> <p>Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the <a href="/facts/Harvard_Mark_I/0d0yAVjb">Harvard Mark I</a>, were built from <a href="/facts/Relay_logic/eEs4FXVn">relay logic</a> gates, using electro-mechanical <a href="/facts/Relay/NQcb9usW">relays</a>. Logic gates can be made using <a href="/facts/Pneumatic/QzkvCCpk">pneumatic</a> devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.<a class="footnote-ref" id="fnref:31" href="#fn:31"><sup>31</sup></a> Various types of fundamental logic gates have been constructed using molecules (<a href="/facts/Molecular_logic_gate/Hoasat7d">molecular logic gates</a>), which are based on chemical inputs and spectroscopic outputs.<a class="footnote-ref" id="fnref:32" href="#fn:32"><sup>32</sup></a> Logic gates have been made out of <a href="/facts/DNA/nB89Iauz">DNA</a> (see <a href="/facts/DNA_nanotechnology/7hzv1IlN">DNA nanotechnology</a>)<a class="footnote-ref" id="fnref:33" href="#fn:33"><sup>33</sup></a> and used to create a computer called MAYA (see <a href="/facts/MAYA-II/rzyTAkpg">MAYA-II</a>). Logic gates can be made from <a href="/facts/Quantum_mechanical/BRc3Mzgr">quantum mechanical</a> effects, see <a href="/facts/Quantum_logic_gate/EFV5sPCU">quantum logic gate</a>. <a href="/facts/Photonic_logic/aPl6UjC9">Photonic logic</a> gates use <a href="/facts/Nonlinear_optical/maerngXd">nonlinear optical</a> effects. </p><p>In principle any method that leads to a gate that is <a href="/facts/Functionally_complete/ncyHAsHH">functionally complete</a> (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates). </p> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/And-inverter_graph/rwu5wt8S">And-inverter graph</a></li> <li><a href="/facts/Boolean_algebra_topics/zFWKrPUu">Boolean algebra topics</a></li> <li><a href="/facts/Boolean_function/uT7E8pqC">Boolean function</a></li> <li><a href="/facts/Depletion-load_NMOS_logic/9xAIaQtl">Depletion-load NMOS logic</a></li> <li><a href="/facts/Digital_circuit/vWgfC29C">Digital circuit</a></li> <li><a href="/facts/Electronic_symbol/xbGK3TQH">Electronic symbol</a></li> <li><a href="/facts/Espresso_heuristic_logic_minimizer/nXDA6pv0">Espresso heuristic logic minimizer</a></li> <li><a href="/facts/Emitter-coupled_logic/wAN1uEgH">Emitter-coupled logic</a></li> <li><a href="/facts/Fan-out/lCm5joyw">Fan-out</a></li> <li><a href="/facts/Field-programmable_gate_array/M8LSGcAU">Field-programmable gate array</a> (FPGA)</li> <li><a href="/facts/Flip-flop_(electronics)/vA99xjM7">Flip-flop (electronics)</a></li> <li><a href="/facts/Functional_completeness/ncyHAsHH">Functional completeness</a></li> <li><a href="/facts/Integrated_injection_logic/6YUwQ4Rs">Integrated injection logic</a></li> <li><a href="/facts/Karnaugh_map/saFd8oNl">Karnaugh map</a></li> <li><a href="/facts/Combinational_logic/L1kaaVK5">Combinational logic</a></li> <li><a href="/facts/List_of_4000_series_integrated_circuits/dlI3sVjC">List of 4000 series integrated circuits</a></li> <li><a href="/facts/List_of_7400_series_integrated_circuits/WBoUynkg">List of 7400 series integrated circuits</a></li> <li><a href="/facts/Logic_family/QlEgIecX">Logic family</a></li> <li><a href="/facts/Logic_level/aa9GrAPg">Logic level</a></li> <li><a href="/facts/Logical_graph/IMH9yIvX">Logical graph</a></li> <li><a href="/facts/Magnetic_logic/qFSAl1kW">Magnetic logic</a></li> <li><a href="/facts/NMOS_logic/6hup3T21">NMOS logic</a></li> <li><a href="/facts/Parametron/lARR99HU">Parametron</a></li> <li><a href="/facts/Processor_design/HeNbj78g">Processor design</a></li> <li><a href="/facts/Programmable_logic_controller/bqh0GAdb">Programmable logic controller</a> (PLC)</li> <li><a href="/facts/Programmable_logic_device/7dIVypm9">Programmable logic device</a> (PLD)</li> <li><a href="/facts/Propositional_calculus/MNt5v31V">Propositional calculus</a></li> <li><a href="/facts/Race_hazard/bvNpgy4F">Race hazard</a></li> <li><a href="/facts/Reversible_computing/yEum13Vs">Reversible computing</a></li> <li><a href="/facts/Superconducting_computing/VjdLaVDr">Superconducting computing</a></li> <li><a href="/facts/Truth_table/4KsmArDW">Truth table</a></li> <li><a href="/facts/Unconventional_computing/XkJjTK0a">Unconventional computing</a></li></ul> <h2 id="further-reading">Further reading</h2> <ul><li>Bostock, Geoff (1988). <a href="https://books.google.com/books?id=XEFTAAAAMAAJ"><i>Programmable logic devices: technology and applications</i></a>. <a href="/facts/McGraw-Hill/oG8VpKJT">McGraw-Hill</a>. <a href="/facts/ISBN_(identifier)/15AdSPa9">ISBN</a> 978-0-07-006611-3.</li> <li>Brown, Stephen D.; Francis, Robert J.; Rose, Jonathan; Vranesic, Zvonko G. (1992). <a href="https://books.google.com/books?id=8s4M-qYOWZIC"><i>Field Programmable Gate Arrays</i></a>. <a href="/facts/Kluwer_Academic/nAesf6nT">Kluwer Academic</a>. <a href="/facts/ISBN_(identifier)/15AdSPa9">ISBN</a> 978-0-7923-9248-4.</li></ul> <h2 id="external-links">External links</h2> Wikiversity has learning resources about <i>Logic gates</i> <ul><li> Media related to Logic gates at Wikimedia Commons</li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>Jaeger (1997). Microelectronic Circuit Design. McGraw-Hill. pp. 226–233. ISBN 0-07-032482-4. <a href="0-07-032482-4" target="_blank">0-07-032482-4</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>Kanellos, Michael (2003-02-11). "Moore's Law to roll on for another decade". CNET. From Integrated circuit <a href="https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/" target="_blank">https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>Zhang, Ting; Cheng, Ying; Guo, Jian-Zhong; Xu, Jian-yi; Liu, Xiao-jun (2015), "Acoustic logic gates and Boolean operation based on self-collimating acoustic beams", Applied Physics Letters, 106 (11), Bibcode:2015ApPhL.106k3503Z, doi:10.1063/1.4915338, retrieved 2024-08-17 <a href="https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext" target="_blank">https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>Wang, Lei; Li, Baowen (2007). "Thermal Logic Gates: Computation with Phonons". Physical Review Letters. 99 (17): 177208. arXiv:0709.0032. Bibcode:2007PhRvL..99q7208W. doi:10.1103/PhysRevLett.99.177208. PMID 17995368. S2CID 10934270. <a href="https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208" target="_blank">https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>Deschamps, Jean-Pierre; Valderrama, Elena; Terés, Lluís (2016-10-12). Digital Systems: From Logic Gates to Processors. Springer. ISBN 978-3-319-41198-9. <a href="978-3-319-41198-9" target="_blank">978-3-319-41198-9</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>Tinder, Richard F. (2000). Engineering digital design (2nd ed.). Academic Press. pp. 317–319. ISBN 0-12-691295-5. <a href="0-12-691295-5" target="_blank">0-12-691295-5</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>Nylan, Michael (2001). The Five "Confucian" Classics. Yale University Press. pp. 204–206. ISBN 978-0-300-08185-5. Retrieved 2010-06-08. <a href="978-0-300-08185-5" target="_blank">978-0-300-08185-5</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> <li id="fn:8"><p>Perkins, Franklin (2004). "Exchange with China". Leibniz and China: A Commerce of Light. Cambridge University Press. p. 117. ISBN 9780521830249. ... one of the traditional orderings of the hexagrams, the xiantian tu ordering made by Shao Yong, was, with a few modifications, the same order found in Leibniz's binary arithmetic. <a href="9780521830249" target="_blank">9780521830249</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></p></li> <li id="fn:9"><p>Julio Sanchez; Maria P. Canton (2017-12-19). Embedded Systems Circuits and Programming. CRC Press. p. 17. ISBN 978-1-4398-7931-3. <a href="978-1-4398-7931-3" target="_blank">978-1-4398-7931-3</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></p></li> <li id="fn:10"><p>Peirce, C. S., "Letter, Peirce to A. Marquand", dated 1886, Writings of Charles S. Peirce, v. 5, 1993, pp. 420–423. See Burks, Arthur W. (1978). "Review: Charles S. Peirce, The new elements of mathematics". Bulletin of the American Mathematical Society. 84 (5): 913–918 [917]. doi:10.1090/S0002-9904-1978-14533-9. <a href="/wiki/Allan_Marquand" target="_blank">/wiki/Allan_Marquand</a> <a href="#fnref:10" class="footnote-back-ref">↩</a></p></li> <li id="fn:11"><p>Luisa Bonolis; Walther Bothe and Bruno Rossi: The birth and development of coincidence methods in cosmic-ray physics. Am. J. Phys. 1 November 2011; 79 (11): 1133–1150. <a href="#fnref:11" class="footnote-back-ref">↩</a></p></li> <li id="fn:12"><p>Yamada, Akihiko (2004). "History of Research on Switching Theory in Japan". IEEJ Transactions on Fundamentals and Materials. 124 (8). Institute of Electrical Engineers of Japan: 720–726. Bibcode:2004IJTFM.124..720Y. doi:10.1541/ieejfms.124.720. <a href="https://www.jstage.jst.go.jp/article/ieejfms/124/8/124_8_720/_article" target="_blank">https://www.jstage.jst.go.jp/article/ieejfms/124/8/124_8_720/_article</a> <a href="#fnref:12" class="footnote-back-ref">↩</a></p></li> <li id="fn:13"><p>"Switching Theory/Relay Circuit Network Theory/Theory of Logical Mathematics". IPSJ Computer Museum. Information Processing Society of Japan. <a href="http://museum.ipsj.or.jp/en/computer/dawn/0002.html" target="_blank">http://museum.ipsj.or.jp/en/computer/dawn/0002.html</a> <a href="#fnref:13" class="footnote-back-ref">↩</a></p></li> <li id="fn:14"><p>Stanković, Radomir S.; Astola, Jaakko T.; Karpovsky, Mark G. (2007). Some Historical Remarks on Switching Theory. CiteSeerX 10.1.1.66.1248. <a href="/wiki/CiteSeerX_(identifier)" target="_blank">/wiki/CiteSeerX_(identifier)</a> <a href="#fnref:14" class="footnote-back-ref">↩</a></p></li> <li id="fn:15"><p>Stanković, Radomir S. [in German]; Astola, Jaakko Tapio [in Finnish], eds. (2008). Reprints from the Early Days of Information Sciences: TICSP Series On the Contributions of Akira Nakashima to Switching Theory (PDF). Tampere International Center for Signal Processing (TICSP) Series. Vol. 40. Tampere University of Technology, Tampere, Finland. ISBN 978-952-15-1980-2. ISSN 1456-2774. Archived from the original (PDF) on 2021-03-08.{{cite book}}: CS1 maint: location missing publisher (link) (3+207+1 pages) 10:00 min <a href="978-952-15-1980-2" target="_blank">978-952-15-1980-2</a> <a href="#fnref:15" class="footnote-back-ref">↩</a></p></li> <li id="fn:16"><p>Stanković, Radomir S. [in German]; Astola, Jaakko Tapio [in Finnish], eds. (2008). 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