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Heterogeneous System Architecture
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<h2 id="rationale">Rationale</h2> <p>The rationale behind HSA is to ease the burden on programmers when offloading calculations to the GPU. Originally driven solely by AMD and called the FSA, the idea was extended to encompass processing units other than GPUs, such as other manufacturers' <a href="/facts/Digital_signal_processor/YuBXweos">DSPs</a>, as well. </p> <p>Modern GPUs are very well suited to perform <a href="/facts/Single_instruction,_multiple_data/gQHWQSpo">single instruction, multiple data</a> (SIMD) and <a href="/facts/Single_instruction,_multiple_threads/kRaRt8NX">single instruction, multiple threads</a> (SIMT), while modern CPUs are still being optimized for branching. etc. </p> <h2 id="overview">Overview</h2> <p>Originally introduced by <a href="/facts/Embedded_system/a4muX1wU">embedded systems</a> such as the <a href="/facts/Cell_Broadband_Engine/p2MIQjMc">Cell Broadband Engine</a>, sharing system memory directly between multiple system actors makes heterogeneous computing more mainstream. Heterogeneous computing itself refers to systems that contain multiple processing units – <a href="/facts/Central_processing_unit/Jxp1bqMV">central processing units</a> (CPUs), <a href="/facts/Graphics_processing_unit/PTK1RQVp">graphics processing units</a> (GPUs), <a href="/facts/Digital_signal_processor/YuBXweos">digital signal processors</a> (DSPs), or any type of <a href="/facts/Application-specific_integrated_circuit/YGUXpX50">application-specific integrated circuits</a> (ASICs). The system architecture allows any accelerator, for instance a <a href="/facts/GPU/PTK1RQVp">graphics processor</a>, to operate at the same processing level as the system's CPU. </p><p>Among its main features, HSA defines a unified <a href="/facts/Virtual_address_space/ILxbMjgv">virtual address space</a> for compute devices: where GPUs traditionally have their own memory, separate from the main (CPU) memory, HSA requires these devices to share <a href="/facts/Page_(computer_memory)/CNGruG1H">page tables</a> so that devices can exchange data by sharing <a href="/facts/Pointer_(computer_programming)/fPoNzy9b">pointers</a>. This is to be supported by custom <a href="/facts/Memory_management_unit/tJQtAQzI">memory management units</a>.<a class="footnote-ref" id="fnref:8" href="#fn:8"><sup>8</sup></a>: 6–7 To render interoperability possible and also to ease various aspects of programming, HSA is intended to be <a href="/facts/Instruction_set/8p8vwUeE">ISA</a>-agnostic for both CPUs and accelerators, and to support high-level programming languages. </p><p>So far, the HSA specifications cover: </p> <h3>HSA Intermediate Layer</h3> <p>HSAIL (Heterogeneous System Architecture Intermediate Language), a <a href="/facts/P-code_machine/zLuq653K">virtual instruction set</a> for parallel programs </p> <ul><li>similar[<i>according to whom?</i>] to <a href="/facts/LLVM_Intermediate_Representation/nPmcspQN">LLVM Intermediate Representation</a> and <a href="/facts/Standard_Portable_Intermediate_Representation/pCMkf78P">SPIR</a> (used by <a href="/facts/OpenCL/ns8y6np7">OpenCL</a> and <a href="/facts/Vulkan_(API)/e188Vdpc">Vulkan</a>)</li> <li>finalized to a specific instruction set by a <a href="/facts/Just-in-time_compilation/rEYDsd8l">JIT compiler</a></li> <li>make late decisions on which core(s) should run a task</li> <li>explicitly parallel</li> <li>supports exceptions, virtual functions and other high-level features</li> <li>debugging support</li></ul> <h3>HSA memory model</h3> <ul><li>compatible with <a href="/facts/C%2B%2B11/fI3YCoKQ">C++11</a>, OpenCL, <a href="/facts/Java_(programming_language)/9ScgFyAL">Java</a> and <a href="/facts/.NET_Framework/J6QDAUhP">.NET</a> memory models</li> <li>relaxed consistency</li> <li>designed to support both managed languages (e.g. Java) and unmanaged languages (e.g. <a href="/facts/C_(programming_language)/Ky2No763">C</a>)</li> <li>will make it much easier to develop 3rd-party compilers for a wide range of heterogeneous products programmed in <a href="/facts/Fortran/m1KqjcMU">Fortran</a>, C++, <a href="/facts/C%2B%2B_AMP/nJcwEMzp">C++ AMP</a>, Java, et al.</li></ul> <h3>HSA dispatcher and run-time</h3> <ul><li>designed to enable heterogeneous task queueing: a work queue per core, distribution of work into queues, load balancing by work stealing</li> <li>any core can schedule work for any other, including itself</li> <li>significant reduction of overhead of scheduling work for a core</li></ul> <p>Mobile devices are one of the HSA's application areas, in which it yields improved power efficiency.<a class="footnote-ref" id="fnref:9" href="#fn:9"><sup>9</sup></a> </p> <h3>Block diagrams</h3> <p>The illustrations below compare CPU-GPU coordination under HSA versus under traditional architectures. </p> <h2 id="software-support">Software support</h2> <p>Some of the HSA-specific features implemented in the hardware need to be supported by the <a href="/facts/Operating_system_kernel/uEj4U3Rz">operating system kernel</a> and specific device drivers. For example, support for AMD <a href="/facts/Radeon/U6y80fWr">Radeon</a> and <a href="/facts/AMD_FirePro/1y6natzA">AMD FirePro</a> graphics cards, and <a href="/facts/AMD_Accelerated_Processing_Unit/hdApEUQw">APUs</a> based on <a href="/facts/Graphics_Core_Next/WYNvhDUP">Graphics Core Next</a> (GCN), was merged into version 3.19 of the <a href="/facts/Linux_kernel_mainline/dlkduHuA">Linux kernel mainline</a>, released on 8 February 2015.<a class="footnote-ref" id="fnref:10" href="#fn:10"><sup>10</sup></a> Programs do not interact directly with amdkfd, but queue their jobs utilizing the HSA runtime.<a class="footnote-ref" id="fnref:11" href="#fn:11"><sup>11</sup></a> This very first implementation, known as amdkfd, focuses on <a href="/facts/AMD_Accelerated_Processing_Unit/hdApEUQw">"Kaveri"</a> or "Berlin" APUs and works alongside the existing Radeon kernel graphics driver. </p><p>Additionally, amdkfd supports <i>heterogeneous queuing</i> (HQ), which aims to simplify the distribution of computational jobs among multiple CPUs and GPUs from the programmer's perspective. Support for <i>heterogeneous memory management</i> (<i>HMM</i>), suited only for graphics hardware featuring version 2 of the AMD's <a href="/facts/IOMMU/lvVkzUyw">IOMMU</a>, was accepted into the Linux kernel mainline version 4.14.<a class="footnote-ref" id="fnref:12" href="#fn:12"><sup>12</sup></a> </p><p>Integrated support for HSA platforms has been announced for the "Sumatra" release of <a href="/facts/OpenJDK/KDzob3aF">OpenJDK</a>, due in 2015.<a class="footnote-ref" id="fnref:13" href="#fn:13"><sup>13</sup></a> </p><p><a href="/facts/AMD_APP_SDK/LX4huLRf">AMD APP SDK</a> is AMD's proprietary software development kit targeting <a href="/facts/Parallel_computing/nQzcpzQt">parallel computing</a>, available for Microsoft Windows and Linux. Bolt is a C++ template library optimized for heterogeneous computing.<a class="footnote-ref" id="fnref:14" href="#fn:14"><sup>14</sup></a> </p><p><a href="/facts/GPUOpen/MX8uasuY">GPUOpen</a> comprehends a couple of other software tools related to HSA. <a href="/facts/CodeXL/TMMYCNWH">CodeXL</a> version 2.0 includes an HSA profiler.<a class="footnote-ref" id="fnref:15" href="#fn:15"><sup>15</sup></a> </p> <h2 id="hardware-support">Hardware support</h2> <h3>AMD</h3> <p>As of February 2015<a href="https://en.wikipedia.org/w/index.php?title=Heterogeneous_System_Architecture&action=edit">[update]</a>, only AMD's "Kaveri" A-series APUs (cf. <a href="/facts/List_of_AMD_Accelerated_Processing_Unit_microprocessors/62q8zqca">"Kaveri" desktop processors</a> and <a href="/facts/List_of_AMD_Accelerated_Processing_Unit_microprocessors/62q8zqca">"Kaveri" mobile processors</a>) and Sony's <a href="/facts/PlayStation_4/wMtdFnoP">PlayStation 4</a> allowed the <a href="/facts/Graphics_processing_unit/PTK1RQVp">integrated GPU</a> to access memory via version 2 of the AMD's IOMMU. Earlier APUs (Trinity and Richland) included the version 2 IOMMU functionality, but only for use by an external GPU connected via PCI Express. </p><p>Post-2015 Carrizo and Bristol Ridge APUs also include the version 2 IOMMU functionality for the integrated GPU. </p><p>The following table shows features of <a href="/facts/AMD/CB1G7QTb">AMD</a>'s processors with 3D graphics, including <a href="/facts/AMD_APU/hdApEUQw">APUs</a> (see also: <a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">List of AMD processors with 3D graphics</a>). </p> [ <a href="https://en.wikipedia.org/w/index.php?title=Template:Features_of_AMD_Processors_with_3D_Graphics&veaction=edit">VisualEditor</a> ] <ul><li>view</li><li>talk</li><li>edit</li></ul> <table><tbody><tr><th colspan="3">Platform</th><th colspan="14">High, standard and low power</th><th colspan="9">Low and ultra-low power</th></tr><tr><th rowspan="11">Codename</th><th rowspan="2">Server</th><th>Basic</th><th colspan="5"></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Toronto</a></th><th colspan="8"></th><th colspan="9"></th></tr><tr><th>Micro</th><th colspan="14"></th><th></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Kyoto</a></th><th colspan="7"></th></tr><tr><th rowspan="4">Desktop</th><th>Performance</th><th colspan="12"></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Raphael</a></th><th rowspan="3"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Phoenix</a></th><th colspan="9" rowspan="3"></th></tr><tr><th>Mainstream</th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Llano</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Trinity</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Richland</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Kaveri</a></th><th rowspan="2"><a href="/facts/Steamroller_(microarchitecture)/SxtLaauz">Kaveri Refresh (Godavari)</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Carrizo</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Bristol Ridge</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Raven Ridge</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Picasso</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Renoir</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Cezanne</a></th><th></th></tr><tr><th>Entry</th><th colspan="2"></th></tr><tr><th>Basic</th><th colspan="14"></th><th></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Kabini</a></th><th colspan="3"></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Dalí</a></th><th colspan="3"></th></tr><tr><th rowspan="4">Mobile</th><th>Performance</th><th colspan="9"></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Renoir</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Cezanne</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Rembrandt</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Dragon Range</a></th><th></th><th rowspan="2" colspan="9"></th></tr><tr><th>Mainstream</th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Llano</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Trinity</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Richland</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Kaveri</a></th><th rowspan="2"></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Carrizo</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Bristol Ridge</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Raven Ridge</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Picasso</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Renoir</a><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Lucienne</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Cezanne</a><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Barceló</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Phoenix</a></th></tr><tr><th>Entry</th><th colspan="6"></th><th colspan="5"></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Dalí</a></th><th colspan="2"></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Mendocino</a></th></tr><tr><th>Basic</th><th colspan="14"></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Desna, Ontario, Zacate</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Kabini, Temash</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Beema, Mullins</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Carrizo-L</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Stoney Ridge</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Pollock</a></th><th></th></tr><tr><th colspan="2">Embedded</th><th></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Trinity</a></th><th></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Bald Eagle</a></th><th></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Merlin Falcon</a>,<a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Brown Falcon</a></th><th></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Great Horned Owl</a></th><th></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Grey Hawk</a></th><th colspan="4"></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Ontario, Zacate</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Kabini</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Steppe Eagle</a>, <a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Crowned Eagle</a>, <a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">LX-Family</a></th><th></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Prairie Falcon</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Banded Kestrel</a></th><th></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">River Hawk</a></th><th></th></tr><tr><td colspan="3">Released</td><td>Aug 2011</td><td>Oct 2012</td><td>Jun 2013</td><td>Jan 2014</td><td>2015</td><td>Jun 2015</td><td>Jun 2016</td><td>Oct 2017</td><td>Jan 2019</td><td>Mar 2020</td><td>Jan 2021</td><td>Jan 2022</td><td>Sep 2022</td><td>Jan 2023</td><td>Jan 2011</td><td>May 2013</td><td>Apr 2014</td><td>May 2015</td><td>Feb 2016</td><td>Apr 2019</td><td>Jul 2020</td><td>Jun 2022</td><td>Nov 2022</td></tr><tr><td colspan="3">CPU <a href="/facts/Microarchitecture/NFRd4NUL">microarchitecture</a></td><td><a href="/facts/AMD_10h/2hQAazep">K10</a></td><td colspan="2"><a href="/facts/Piledriver_(microarchitecture)/Fhxly06H">Piledriver</a></td><td colspan="2"><a href="/facts/Steamroller_(microarchitecture)/SxtLaauz">Steamroller</a></td><td><a href="/facts/Excavator_(microarchitecture)/Bzj9WKGV">Excavator</a></td><td>"<a href="/facts/Excavator_(microarchitecture)/Bzj9WKGV">Excavator+</a>"<a class="footnote-ref" id="fnref:16" href="#fn:16"><sup>16</sup></a></td><td><a href="/facts/Zen_(first_generation)/oChXIp3y">Zen</a></td><td><a href="/facts/Zen%2B/1bJfQtRR">Zen+</a></td><td><a href="/facts/Zen_2/pdL7I80c">Zen 2</a></td><td><a href="/facts/Zen_3/szGTAfyB">Zen 3</a></td><td><a href="/facts/Zen_3%2B/szGTAfyB">Zen 3+</a></td><td colspan="2"><a href="/facts/Zen_4/UJXLYNuq">Zen 4</a></td><td><a href="/facts/Bobcat_(microarchitecture)/EweFKE9J">Bobcat</a></td><td><a href="/facts/Jaguar_(microarchitecture)/PkCbNj9a">Jaguar</a></td><td><a href="/facts/Puma_(microarchitecture)/ujJ1MBg1">Puma</a></td><td><a href="/facts/Puma_(microarchitecture)/ujJ1MBg1">Puma+</a><a class="footnote-ref" id="fnref:17" href="#fn:17"><sup>17</sup></a></td><td>"<a href="/facts/Excavator_(microarchitecture)/Bzj9WKGV">Excavator+</a>"</td><td colspan="2"><a href="/facts/Zen_(first_generation)/oChXIp3y">Zen</a></td><td><a href="/facts/Zen%2B/1bJfQtRR">Zen+</a></td><td>"<a href="/facts/Zen_2/pdL7I80c">Zen 2+</a>"</td></tr><tr><td colspan="3"><a href="/facts/Instruction_set_architecture/8p8vwUeE">ISA</a></td><td><a href="/facts/X86-64/cyWvUFlP">x86-64</a> v1</td><td colspan="4"><a href="/facts/X86-64/cyWvUFlP">x86-64</a> v2</td><td colspan="7"><a href="/facts/X86-64/cyWvUFlP">x86-64</a> v3</td><td colspan="2"><a href="/facts/X86-64/cyWvUFlP">x86-64</a> v4</td><td><a href="/facts/X86-64/cyWvUFlP">x86-64</a> v1</td><td colspan="3"><a href="/facts/X86-64/cyWvUFlP">x86-64</a> v2</td><td colspan="5"><a href="/facts/X86-64/cyWvUFlP">x86-64</a> v3</td></tr><tr><td rowspan="5">Socket</td><td rowspan="4">Desktop</td><td>Performance</td><td colspan="12">—</td><td rowspan="2"><a href="/facts/Socket_AM5/x4zuI5Ck">AM5</a></td><td>—</td><td rowspan="3" colspan="9">—</td></tr><tr><td>Mainstream</td><td colspan="5">—</td><td colspan="6"><a href="/facts/Socket_AM4/MuNKCgeF">AM4</a></td><td>—</td><th>—</th></tr><tr><td>Entry</td><td><a href="/facts/Socket_FM1/vrA6VVSD">FM1</a></td><td colspan="2"><a href="/facts/Socket_FM2/olCXfpAL">FM2</a></td><td colspan="2"><a href="/facts/Socket_FM2%2B/GQlcTMJW">FM2+</a></td><td><a href="/facts/Socket_FM2%2B/GQlcTMJW">FM2+</a><a class="footnote-ref" id="fnref:18" href="#fn:18"><sup>18</sup></a>, <a href="/facts/Socket_AM4/MuNKCgeF">AM4</a></td><td colspan="5"><a href="/facts/Socket_AM4/MuNKCgeF">AM4</a></td><td colspan="3">—</td></tr><tr><td>Basic</td><td colspan="14">—</td><td>—</td><td><a href="/facts/Socket_AM1/43Q9guVD">AM1</a></td><td colspan="3">—</td><td>FP5</td><td colspan="3">—</td></tr><tr><td colspan="2">Other</td><td><a href="/facts/Socket_FS1/GGxHBYCC">FS1</a></td><td colspan="2"><a href="/facts/Socket_FS1r2/GGxHBYCC">FS1+</a>, <a href="/facts/Socket_FP2/c8WeE1u8">FP2</a></td><td colspan="2"><a href="/facts/Socket_FP3/7vDcpQfR">FP3</a></td><td colspan="2">FP4</td><td colspan="2">FP5</td><td colspan="2">FP6</td><td>FP7</td><td>FL1</td><td>FP7 FP7r2 FP8</td><td><a href="/facts/Socket_FT1/IuvuQVPW">FT1</a></td><td><a href="/facts/Socket_FT3/PC1tK41m">FT3</a></td><td colspan="2"><a href="/facts/Socket_FT3b/PC1tK41m">FT3b</a></td><td>FP4</td><td>FP5</td><td>FT5</td><td>FP5</td><td>FT6</td></tr><tr><td colspan="3"><a href="/facts/PCI_Express/ADhsLCUK">PCI Express</a> version</td><td colspan="3">2.0</td><td colspan="8">3.0</td><td>4.0</td><td>5.0</td><td>4.0</td><td colspan="4">2.0</td><td colspan="5">3.0</td></tr><tr><td colspan="3"><a href="/facts/Compute_Express_Link/YSJGcCMx">CXL</a></td><td colspan="14">—</td><td colspan="9">—</td></tr><tr><td colspan="3"><a href="/facts/Semiconductor_device_fabrication/Jd23Mu1z">Fab.</a> (<a href="/facts/Nanometre/a98sjHyu">nm</a>)</td><td colspan="3"><a href="/facts/GlobalFoundries/lFTS5fbT">GF</a> <a href="/facts/32_nm_process/CsdohJVh">32SHP</a>(<a href="/facts/HKMG/4E8qtXmp">HKMG</a> <a href="/facts/Silicon_on_insulator/fxSkXYmw">SOI</a>)</td><td colspan="4">GF <a href="/facts/32_nm_process/CsdohJVh">28SHP</a>(HKMG bulk)</td><td>GF <a href="/facts/14_nm_process/lQYsD92n">14LPP</a>(<a href="/facts/FinFET/xox63kP7">FinFET</a> bulk)</td><td>GF <a href="/facts/14_nm_process/lQYsD92n">12LP</a>(FinFET bulk)</td><td colspan="2"><a href="/facts/TSMC/B4BdojRk">TSMC</a> <a href="/facts/7_nm_process/7UatqvR9">N7</a>(FinFET bulk)</td><td>TSMC <a href="/facts/7_nm_process/7UatqvR9">N6</a> (FinFET bulk)</td><td>CCD: TSMC <a href="/facts/5_nm_process/5NndITJ3">N5</a> (FinFET bulk)cIOD: TSMC <a href="/facts/7_nm_process/7UatqvR9">N6</a>(FinFET bulk)</td><td>TSMC <a href="/facts/5_nm_process/5NndITJ3">4nm</a> (FinFET bulk)</td><td>TSMC <a href="/facts/45_nm_process/hlbmxAme">N40</a>(bulk)</td><td>TSMC <a href="/facts/32_nm_process/CsdohJVh">N28</a>(HKMG bulk)</td><td colspan="3">GF 28SHP(HKMG bulk)</td><td colspan="2">GF <a href="/facts/14_nm_process/lQYsD92n">14LPP</a>(<a href="/facts/FinFET/xox63kP7">FinFET</a> bulk)</td><td>GF <a href="/facts/14_nm_process/lQYsD92n">12LP</a>(FinFET bulk)</td><td>TSMC <a href="/facts/7_nm_process/7UatqvR9">N6</a> (FinFET bulk)</td></tr><tr><td colspan="3"><a href="/facts/Die_(integrated_circuit)/XWvdlltE">Die</a> area (mm2)</td><td>228</td><td colspan="2">246</td><td colspan="2">245</td><td>245</td><td>250</td><td colspan="2">210<a class="footnote-ref" id="fnref:19" href="#fn:19"><sup>19</sup></a></td><td>156</td><td>180</td><td>210</td><td>CCD: (2x) 70cIOD: 122</td><td>178</td><td>75 (+ 28 <a href="/facts/List_of_AMD_chipsets/AesBnfxQ">FCH</a>)</td><td colspan="2">107</td><td>?</td><td>125</td><td>149</td><td></td><td></td><td>~100</td></tr><tr><td colspan="3">Min <a href="/facts/Thermal_Design_Power/Idcy26tM">TDP</a> (W)</td><td>35</td><td colspan="4">17</td><td colspan="4">12</td><td colspan="2">10</td><td>15</td><td>65</td><td>35</td><td>4.5</td><td>4</td><td>3.95</td><td>10</td><td colspan="3">6</td><td>12</td><td>8</td></tr><tr><td colspan="3">Max APU <a href="/facts/Thermal_Design_Power/Idcy26tM">TDP</a> (W)</td><td colspan="3">100</td><td colspan="2">95</td><td colspan="6">65</td><td>45</td><td>170</td><td>54</td><td>18</td><td colspan="5">25</td><td>6</td><td>54</td><td>15</td></tr><tr><td colspan="3">Max stock APU base clock (GHz)</td><td>3</td><td>3.8</td><td>4.1</td><td colspan="2">4.1</td><td>3.7</td><td>3.8</td><td>3.6</td><td>3.7</td><td>3.8</td><td>4.0</td><td>3.3</td><td>4.7</td><td>4.3</td><td>1.75</td><td>2.2</td><td>2</td><td>2.2</td><td>3.2</td><td>2.6</td><td>1.2</td><td>3.35</td><td>2.8</td></tr><tr><td colspan="3">Max APUs per node<a class="footnote-ref" id="fnref:20" href="#fn:20"><sup>20</sup></a></td><td colspan="14">1</td><td colspan="9">1</td></tr><tr><td colspan="3">Max core dies per CPU</td><td colspan="12">1</td><td>2</td><td>1</td><td colspan="9">1</td></tr><tr><td colspan="3">Max CCX per core die</td><td colspan="9">1</td><td>2</td><td colspan="4">1</td><td colspan="9">1</td></tr><tr><td colspan="3">Max cores per CCX</td><td colspan="10">4</td><td colspan="4">8</td><td>2</td><td colspan="3">4</td><td colspan="3">2</td><td colspan="2">4</td></tr><tr><td colspan="3">Max <a href="/facts/Central_processing_unit/Jxp1bqMV">CPU</a><a class="footnote-ref" id="fnref:21" href="#fn:21"><sup>21</sup></a> <a href="/facts/Multi-core_processor/ABNb65hQ">cores</a> per APU</td><td colspan="9">4</td><td colspan="3">8</td><td>16</td><td>8</td><td>2</td><td colspan="3">4</td><td colspan="3">2</td><td colspan="2">4</td></tr><tr><td colspan="3">Max <a href="/facts/Thread_(computing)/hh8WHyPd">threads</a> per CPU core</td><td colspan="7">1</td><td colspan="7">2</td><td colspan="5">1</td><td colspan="4">2</td></tr><tr><td colspan="3">Integer pipeline structure</td><td>3+3</td><td colspan="6">2+2</td><td colspan="2">4+2</td><td>4+2+1</td><td colspan="4">1+3+3+1+2</td><td colspan="4">1+1+1+1</td><td>2+2</td><td colspan="3">4+2</td><td>4+2+1</td></tr><tr><td colspan="3">i386, i486, i586, CMOV, NOPL, i686, <a href="/facts/Physical_Address_Extension/aEr4tj4x">PAE</a>, <a href="/facts/NX_bit/MnBB93BK">NX bit</a>, CMPXCHG16B, <a href="/facts/AMD-V/utQwmdY3">AMD-V</a>, <a href="/facts/Second_Level_Address_Translation/WY0j2dRv">RVI</a>, <a href="/facts/Bit_Manipulation_Instruction_Sets/LJAm1LWC">ABM</a>, and 64-bit LAHF/SAHF</td><td colspan="14"></td><td colspan="9"></td></tr><tr><td colspan="3"><a href="/facts/IOMMU/lvVkzUyw">IOMMU</a><a class="footnote-ref" id="fnref:22" href="#fn:22"><sup>22</sup></a></td><td rowspan="2">—</td><td colspan="13">v2</td><td colspan="2">v1</td><td colspan="7">v2</td></tr><tr><td colspan="3"><a href="/facts/Bit_Manipulation_Instruction_Sets/LJAm1LWC">BMI1</a>, <a href="/facts/AES_instruction_set/NomFEB4w">AES-NI</a>, <a href="/facts/CLMUL/UzzxBF65">CLMUL</a>, and <a href="/facts/F16C/v6G70oa7">F16C</a></td><td colspan="13"></td><td rowspan="2">—</td><td colspan="9" rowspan="2"></td></tr><tr><td colspan="3">MOVBE</td><td colspan="5" rowspan="2">—</td><td rowspan="2" colspan="9"></td></tr><tr><td colspan="3"><a href="/facts/X86_virtualization/utQwmdY3">AVIC</a>, <a href="/facts/Bit_Manipulation_Instruction_Sets/LJAm1LWC">BMI2</a>, <a href="/facts/RDRAND/IdeN4y36">RDRAND</a>, and MWAITX/MONITORX</td><td colspan="4">—</td><td colspan="5"></td></tr><tr><td colspan="3">SME<a class="footnote-ref" id="fnref:23" href="#fn:23"><sup>23</sup></a>, TSME<a class="footnote-ref" id="fnref:24" href="#fn:24"><sup>24</sup></a>, <a href="/facts/Intel_ADX/7I3KDzYA">ADX</a>, <a href="/facts/Intel_SHA_extensions/qDzy2N70">SHA</a>, <a href="/facts/RDSEED/IdeN4y36">RDSEED</a>, <a href="/facts/Supervisor_Mode_Access_Prevention/H8RSCNy2">SMAP</a>, <a href="/facts/Control_register/9VGRHh3f">SMEP</a>, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing</td><td colspan="7">—</td><td colspan="7"></td><td colspan="5">—</td><td colspan="4"></td></tr><tr><td colspan="3"><a href="/facts/Second_Level_Address_Translation/WY0j2dRv">GMET</a>, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT</td><td colspan="9">—</td><td colspan="5"></td><td colspan="8">—</td><td></td></tr><tr><td colspan="3"><a href="/facts/Memory_protection/3zDwN2SG">MPK</a>, VAES</td><td colspan="10">—</td><td colspan="4"></td><td colspan="9">—</td></tr><tr><td colspan="3"><a href="/facts/Software_Guard_Extensions/HcgbyB5P">SGX</a></td><td colspan="14">—</td><td colspan="9">—</td></tr><tr><td colspan="3"><a href="/facts/Floating-point_unit/XWTW2AbF">FPUs</a> per <a href="/facts/Multi-core_processor/ABNb65hQ">core</a></td><td>1</td><td colspan="6">0.5</td><td colspan="7">1</td><td colspan="4">1</td><td>0.5</td><td colspan="4">1</td></tr><tr><td colspan="3">Pipes per FPU</td><td colspan="14">2</td><td colspan="9">2</td></tr><tr><td colspan="3">FPU pipe width</td><td colspan="9">128-bit</td><td colspan="5">256-bit</td><td>80-bit</td><td colspan="7">128-bit</td><td>256-bit</td></tr><tr><td colspan="3">CPU <a href="/facts/Instruction_set/8p8vwUeE">instruction set</a> <a href="/facts/Single_instruction,_multiple_data/gQHWQSpo">SIMD</a> level</td><td><a href="/facts/SSE4a/Tnxrl7Ph">SSE4a</a><a class="footnote-ref" id="fnref:25" href="#fn:25"><sup>25</sup></a></td><td colspan="4"><a href="/facts/Advanced_Vector_Extensions/znDpc6Vt">AVX</a></td><td colspan="7"><a href="/facts/Advanced_Vector_Extensions/znDpc6Vt">AVX2</a></td><td colspan="2"><a href="/facts/AVX-512/2KpGqI8t">AVX-512</a></td><td><a href="/facts/SSSE3/xlRTcz4I">SSSE3</a></td><td colspan="3"><a href="/facts/Advanced_Vector_Extensions/znDpc6Vt">AVX</a></td><td colspan="5"><a href="/facts/Advanced_Vector_Extensions/znDpc6Vt">AVX2</a></td></tr><tr><td colspan="3"><a href="/facts/3DNow!/QYJL2HBt">3DNow!</a></td><td><a href="/facts/3DNow!/QYJL2HBt">3DNow!+</a></td><td colspan="13">—</td><td colspan="9">—</td></tr><tr><td colspan="3"><a href="/facts/PREFETCHW/QYJL2HBt">PREFETCH/PREFETCHW</a></td><td colspan="14"></td><td colspan="9"></td></tr><tr><td colspan="3">GFNI</td><td colspan="12">—</td><td colspan="2"></td><td rowspan="2" colspan="9">—</td></tr><tr><td colspan="3"><a href="/facts/Advanced_Matrix_Extensions/qkDBQbBE">AMX</a></td><td colspan="14">—</td></tr><tr><td colspan="3"><a href="/facts/FMA4/mqglSHqk">FMA4</a>, LWP, <a href="/facts/Bit_Manipulation_Instruction_Sets/LJAm1LWC">TBM</a>, and <a href="/facts/XOP_instruction_set/Xey2cAGM">XOP</a></td><td rowspan="2">—</td><td colspan="6"></td><td colspan="7">—</td><td rowspan="2" colspan="4">—</td><td></td><td colspan="4">—</td></tr><tr><td colspan="3"><a href="/facts/FMA3/mqglSHqk">FMA3</a></td><td colspan="13"></td><td colspan="5"></td></tr><tr><td colspan="3"><a href="/facts/AMD_XDNA/Yafyvy2F">AMD XDNA</a></td><td colspan="13">—</td><td></td><td colspan="9">—</td></tr><tr><td colspan="3"><a href="/facts/L1_cache/x8BYFcdv">L1</a> data cache per core (KiB)</td><td>64</td><td colspan="4">16</td><td colspan="9">32</td><td colspan="9">32</td></tr><tr><td colspan="3">L1 data cache <a href="/facts/Cache_placement_policies/MuBjrreM">associativity</a> (ways)</td><td>2</td><td colspan="4">4</td><td colspan="9">8</td><td colspan="9">8</td></tr><tr><td colspan="3">L1 instruction caches per <a href="/facts/Multi-core_processor/ABNb65hQ">core</a></td><td>1</td><td colspan="6">0.5</td><td colspan="7">1</td><td colspan="4">1</td><td>0.5</td><td colspan="4">1</td></tr><tr><td colspan="3">Max APU total L1 instruction cache (KiB)</td><td>256</td><td colspan="2">128</td><td colspan="4">192</td><td colspan="5">256</td><td>512</td><td>256</td><td colspan="2">64</td><td colspan="2">128</td><td>96</td><td colspan="4">128</td></tr><tr><td colspan="3">L1 instruction cache <a href="/facts/Cache_placement_policies/MuBjrreM">associativity</a> (ways)</td><td colspan="3">2</td><td colspan="4">3</td><td colspan="2">4</td><td colspan="5">8</td><td colspan="4">2</td><td>3</td><td colspan="3">4</td><td>8</td></tr><tr><td colspan="3"><a href="/facts/L2_cache/x8BYFcdv">L2 caches</a> per <a href="/facts/Multi-core_processor/ABNb65hQ">core</a></td><td>1</td><td colspan="6">0.5</td><td colspan="7">1</td><td colspan="4">1</td><td>0.5</td><td colspan="4">1</td></tr><tr><td colspan="3">Max APU total L2 cache (MiB)</td><td colspan="5">4</td><td colspan="4">2</td><td colspan="3">4</td><td>16</td><td></td><td>1</td><td colspan="3">2</td><td colspan="3">1</td><td colspan="2">2</td></tr><tr><td colspan="3">L2 cache <a href="/facts/Cache_placement_policies/MuBjrreM">associativity</a> (ways)</td><td colspan="7">16</td><td colspan="7">8</td><td colspan="5">16</td><td colspan="4">8</td></tr><tr><td colspan="3">Max on-die <a href="/facts/L3_cache/x8BYFcdv">L3 cache</a> per CCX (MiB)</td><td colspan="7" rowspan="8">—</td><td colspan="3">4</td><td colspan="2">16</td><td>32</td><td></td><td colspan="6" rowspan="8">—</td><td colspan="4">4</td></tr><tr><td colspan="3">Max 3D V-Cache per CCD (MiB)</td><td colspan="5">—</td><td>64</td><td>—</td><td colspan="4">—</td></tr><tr><td colspan="3">Max total in-CCD <a href="/facts/L3_cache/x8BYFcdv">L3 cache</a> per APU (MiB)</td><td colspan="2">4</td><td>8</td><td colspan="2">16</td><td>64</td><td></td><td colspan="4">4</td></tr><tr><td colspan="3">Max. total 3D V-Cache per APU (MiB)</td><td colspan="5">—</td><td>64</td><td>—</td><td colspan="4">—</td></tr><tr><td colspan="3">Max. board <a href="/facts/L3_cache/x8BYFcdv">L3 cache</a> per APU (MiB)</td><td colspan="7">—</td><td colspan="4">—</td></tr><tr><td colspan="3">Max total <a href="/facts/L3_cache/x8BYFcdv">L3 cache</a> per APU (MiB)</td><td colspan="2">4</td><td>8</td><td colspan="2">16</td><td>128</td><td></td><td colspan="4">4</td></tr><tr><td colspan="3">APU L3 cache <a href="/facts/Cache_placement_policies/MuBjrreM">associativity</a> (ways)</td><td colspan="7">16</td><td colspan="4">16</td></tr><tr><td colspan="3">L3 cache scheme</td><td colspan="7"><a href="/facts/Victim_cache/7efuQ3PY">Victim</a></td><td colspan="4"><a href="/facts/Victim_cache/7efuQ3PY">Victim</a></td></tr><tr><td colspan="3">Max. <a href="/facts/L4_cache/x8BYFcdv">L4 cache</a></td><td colspan="14">—</td><td colspan="9">—</td></tr><tr><td colspan="3">Max stock <a href="/facts/Dynamic_random-access_memory/koI9FGo5">DRAM</a> support</td><td colspan="2"><a href="/facts/DDR3_SDRAM/1R1CTNv3">DDR3</a>-1866</td><td colspan="3">DDR3-2133</td><td>DDR3-2133, <a href="/facts/DDR4_SDRAM/70r37baX">DDR4</a>-2400</td><td>DDR4-2400</td><td colspan="2">DDR4-2933</td><td colspan="2">DDR4-3200, <a href="/facts/LPDDR/2XdLrg47">LPDDR4</a>-4266</td><td><a href="/facts/DDR5_SDRAM/N3XSGE40">DDR5</a>-4800, <a href="/facts/LPDDR/2XdLrg47">LPDDR5</a>-6400</td><td><a href="/facts/DDR5_SDRAM/N3XSGE40">DDR5</a>-5200</td><td><a href="/facts/DDR5_SDRAM/N3XSGE40">DDR5</a>-5600, <a href="/facts/LPDDR/2XdLrg47">LPDDR5x</a>-7500</td><td><a href="/facts/DDR3L/1R1CTNv3">DDR3L</a>-1333</td><td>DDR3L-1600</td><td colspan="2">DDR3L-1866</td><td>DDR3-1866, <a href="/facts/DDR4_SDRAM/70r37baX">DDR4</a>-2400</td><td>DDR4-2400</td><td>DDR4-1600</td><td>DDR4-3200</td><td>LPDDR5-5500</td></tr><tr><td colspan="3">Max <a href="/facts/Dynamic_random-access_memory/koI9FGo5">DRAM</a> channels per APU</td><td colspan="14">2</td><td colspan="5">1</td><td>2</td><td>1</td><td colspan="2">2</td></tr><tr><td colspan="3">Max stock <a href="/facts/Dynamic_random-access_memory/koI9FGo5">DRAM</a> <a href="/facts/Bandwidth_(computing)/lY6Tb4gX">bandwidth</a> (GB/s) per APU</td><td colspan="2">29.866</td><td colspan="3">34.132</td><td colspan="2">38.400</td><td colspan="2">46.932</td><td colspan="2">68.256</td><td>102.400</td><td>83.200</td><td>120.000</td><td>10.666</td><td>12.800</td><td colspan="2">14.933</td><td>19.200</td><td>38.400</td><td>12.800</td><td>51.200</td><td>88.000</td></tr><tr><td colspan="3">GPU <a href="/facts/Microarchitecture/NFRd4NUL">microarchitecture</a></td><td><a href="/facts/TeraScale_(microarchitecture)/Yt6jwq9b">TeraScale 2 (VLIW5)</a></td><td colspan="2"><a href="/facts/TeraScale_(microarchitecture)/Yt6jwq9b">TeraScale 3 (VLIW4)</a></td><td colspan="2"><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN 2nd gen</a></td><td colspan="2"><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN 3rd gen</a></td><td colspan="4"><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN 5th gen</a><a class="footnote-ref" id="fnref:26" href="#fn:26"><sup>26</sup></a></td><td colspan="2"><a href="/facts/RDNA_2/tplgu8A1">RDNA 2</a></td><td><a href="/facts/RDNA_3/tCrEHPQu">RDNA 3</a></td><td><a href="/facts/TeraScale_(microarchitecture)/Yt6jwq9b">TeraScale 2 (VLIW5)</a></td><td colspan="3"><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN 2nd gen</a></td><td><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN 3rd gen</a><a class="footnote-ref" id="fnref:27" href="#fn:27"><sup>27</sup></a></td><td colspan="3"><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN 5th gen</a></td><td><a href="/facts/RDNA_2/tplgu8A1">RDNA 2</a></td></tr><tr><td colspan="3">GPU <a href="/facts/Instruction_set/8p8vwUeE">instruction set</a></td><td colspan="3"><a href="/facts/TeraScale_(microarchitecture)/Yt6jwq9b">TeraScale</a> instruction set</td><td colspan="8"><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN instruction set</a></td><td colspan="3"><a href="/facts/RDNA_(microarchitecture)/tplgu8A1">RDNA instruction set</a></td><td><a href="/facts/TeraScale_(microarchitecture)/Yt6jwq9b">TeraScale</a> instruction set</td><td colspan="7"><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN instruction set</a></td><td><a href="/facts/RDNA_(microarchitecture)/tplgu8A1">RDNA instruction set</a></td></tr><tr><td colspan="3">Max stock GPU base clock (MHz)</td><td>600</td><td>800</td><td>844</td><td colspan="2">866</td><td colspan="2">1108</td><td>1250</td><td>1400</td><td colspan="2">2100</td><td>2400</td><td>400</td><td></td><td>538</td><td>600</td><td>?</td><td>847</td><td>900</td><td>1200</td><td>600</td><td>1300</td><td>1900</td></tr><tr><td colspan="3">Max stock GPU base <a href="/facts/GFLOPS/6zYlH68F">GFLOPS</a><a class="footnote-ref" id="fnref:28" href="#fn:28"><sup>28</sup></a></td><td>480</td><td>614.4</td><td>648.1</td><td colspan="2">886.7</td><td colspan="2">1134.5</td><td>1760</td><td>1971.2</td><td colspan="2">2150.4</td><td>3686.4</td><td>102.4</td><td></td><td>86</td><td>?</td><td>?</td><td>?</td><td>345.6</td><td>460.8</td><td>230.4</td><td>1331.2</td><td>486.4</td></tr><tr><td rowspan="2" colspan="3">3D engine<a class="footnote-ref" id="fnref:29" href="#fn:29"><sup>29</sup></a></td><td>Up to 400:20:8</td><td colspan="2">Up to 384:24:6</td><td colspan="4">Up to 512:32:8</td><td colspan="2">Up to 704:44:16<a class="footnote-ref" id="fnref:30" href="#fn:30"><sup>30</sup></a></td><td colspan="2">Up to 512:32:8</td><td>768:48:8</td><td>128:8:4</td><td></td><td>80:8:4</td><td colspan="3">128:8:4</td><td>Up to 192:12:8</td><td>Up to 192:12:4</td><td>192:12:4</td><td>Up to 512:?:?</td><td>128:?:?</td></tr><tr><td colspan="3">IOMMUv1</td><td colspan="11"><a href="/facts/Heterogeneous_Memory_Management/uwayMPnT">IOMMUv2</a></td><td colspan="2">IOMMUv1</td><td colspan="2">?</td><td colspan="5">IOMMUv2</td></tr><tr><td colspan="3">Video decoder</td><td colspan="3"><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD 3.0</a></td><td colspan="2"><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD 4.2</a></td><td colspan="2"><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD 6.0</a></td><td rowspan="2" colspan="2"><a href="/facts/Video_Core_Next/I0GL8eMR">VCN</a> 1.0<a class="footnote-ref" id="fnref:31" href="#fn:31"><sup>31</sup></a></td><td rowspan="2">VCN 2.1<a class="footnote-ref" id="fnref:32" href="#fn:32"><sup>32</sup></a></td><td rowspan="2">VCN 2.2<a class="footnote-ref" id="fnref:33" href="#fn:33"><sup>33</sup></a></td><td colspan="2" rowspan="2">VCN 3.1</td><td rowspan="2">?</td><td><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD 3.0</a></td><td><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD 4.0</a></td><td colspan="2"><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD 4.2</a></td><td><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD 6.2</a></td><td rowspan="2" colspan="3"><a href="/facts/Video_Core_Next/I0GL8eMR">VCN 1.0</a></td><td rowspan="2">VCN 3.1</td></tr><tr><td colspan="3">Video encoder</td><td>—</td><td colspan="2"><a href="/facts/Video_Coding_Engine/4L5MLb6K">VCE 1.0</a></td><td colspan="2"><a href="/facts/Video_Coding_Engine/4L5MLb6K">VCE 2.0</a></td><td colspan="2"><a href="/facts/Video_Coding_Engine/4L5MLb6K">VCE 3.1</a></td><td>—</td><td colspan="3"><a href="/facts/Video_Coding_Engine/4L5MLb6K">VCE 2.0</a></td><td><a href="/facts/Video_Coding_Engine/4L5MLb6K">VCE 3.4</a></td></tr><tr><td colspan="3">AMD Fluid Motion</td><td colspan="3"></td><td colspan="4"></td><td colspan="7"></td><td colspan="2"></td><td colspan="3"></td><td colspan="4"></td></tr><tr><td colspan="3">GPU power saving</td><td><a href="/facts/AMD_PowerPlay/By12rf5S">PowerPlay</a></td><td colspan="13"><a href="/facts/AMD_PowerTune/NMNAqExx">PowerTune</a></td><td><a href="/facts/AMD_PowerPlay/By12rf5S">PowerPlay</a></td><td colspan="8"><a href="/facts/AMD_PowerTune/NMNAqExx">PowerTune</a><a class="footnote-ref" id="fnref:34" href="#fn:34"><sup>34</sup></a></td></tr><tr><td colspan="3"><a href="/facts/AMD_TrueAudio/085nbPwY">TrueAudio</a></td><td colspan="3" rowspan="2">—</td><td colspan="7"><a class="footnote-ref" id="fnref:35" href="#fn:35"><sup>35</sup></a></td><td colspan="4">?</td><td rowspan="2">—</td><td colspan="8"></td></tr><tr><td colspan="3"><a href="/facts/FreeSync/UzEbg48y">FreeSync</a></td><td colspan="11">12</td><td colspan="88">12</td></tr><tr><td colspan="3"><a href="/facts/HDCP/zYhpvdCz">HDCP</a><a class="footnote-ref" id="fnref:36" href="#fn:36"><sup>36</sup></a></td><td colspan="3">?</td><td colspan="4">1.4</td><td colspan="4">2.2</td><td colspan="3">2.3</td><td>?</td><td colspan="4">1.4</td><td colspan="3">2.2</td><td>2.3</td></tr><tr><td colspan="3"><a href="/facts/PlayReady/Cc0XStVx">PlayReady</a><a class="footnote-ref" id="fnref:37" href="#fn:37"><sup>37</sup></a></td><td colspan="7">—</td><td colspan="7">3.0 not yet</td><td colspan="5">—</td><td colspan="4">3.0 not yet</td></tr><tr><td colspan="3"><a href="/facts/AMD_Eyefinity/Rnw8Qk1v">Supported displays</a><a class="footnote-ref" id="fnref:38" href="#fn:38"><sup>38</sup></a></td><td>2–3</td><td colspan="4">2–4</td><td colspan="2">3</td><td colspan="2">3 (desktop)4 (mobile, embedded)</td><td colspan="5">4</td><td colspan="4">2</td><td>3</td><td>4</td><td></td><td colspan="2">4</td></tr><tr><td colspan="3">/drm/radeon<a class="footnote-ref" id="fnref:39" href="#fn:39"><sup>39</sup></a><a class="footnote-ref" id="fnref:40" href="#fn:40"><sup>40</sup></a><a class="footnote-ref" id="fnref:41" href="#fn:41"><sup>41</sup></a></td><td colspan="6"></td><td colspan="8">—</td><td colspan="4"></td><td colspan="5">—</td></tr><tr><td colspan="3">/drm/amdgpu<a class="footnote-ref" id="fnref:42" href="#fn:42"><sup>42</sup></a><a class="footnote-ref" id="fnref:43" href="#fn:43"><sup>43</sup></a></td><td colspan="3">—</td><td colspan="11"><a class="footnote-ref" id="fnref:44" href="#fn:44"><sup>44</sup></a></td><td>—</td><td colspan="8"><a class="footnote-ref" id="fnref:45" href="#fn:45"><sup>45</sup></a></td></tr></tbody></table> <h3>ARM</h3> <p>ARM's <a href="/facts/Bifrost_(microarchitecture)/hHeuRwXb">Bifrost</a> microarchitecture, as implemented in the Mali-G71,<a class="footnote-ref" id="fnref:46" href="#fn:46"><sup>46</sup></a> is fully compliant with the HSA 1.1 hardware specifications. As of June 2016<a href="https://en.wikipedia.org/w/index.php?title=Heterogeneous_System_Architecture&action=edit">[update]</a>, ARM has not announced software support that would use this hardware feature. </p> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/General-purpose_computing_on_graphics_processing_units/roBwsPY2">General-purpose computing on graphics processing units</a> (GPGPU)</li> <li><a href="/facts/Non-Uniform_Memory_Access/MpmN5mN0">Non-Uniform Memory Access</a> (NUMA)</li> <li><a href="/facts/OpenMP/69IpI80o">OpenMP</a></li> <li><a href="/facts/Shared_memory/zmpH7WuV">Shared memory</a></li> <li><a href="/facts/Zero-copy/cc13RBxU">Zero-copy</a></li></ul> <h2 id="external-links">External links</h2> Wikimedia Commons has media related to Heterogeneous System Architecture. <ul><li><a href="https://www.youtube.com/watch?v=ln8JpfaLvbM">HSA Heterogeneous System Architecture Overview</a> on <a href="/facts/YouTube_video_(identifier)/db276jst">YouTube</a> by Vinod Tipparaju at <a href="/facts/ACM/IEEE_Supercomputing_Conference/vtBfdQHj">SC13</a> in November 2013</li> <li><a href="https://web.archive.org/web/20160514070602/http://www.mpsoc-forum.org/previous/2013/slides/8-Hegde.pdf">HSA and the software ecosystem</a></li> <li><a href="http://www-conf.slac.stanford.edu/xldb2012/talks/xldb2012_wed_1400_MichaelHouston.pdf">2012 – HSA by Michael Houston</a> <a href="https://web.archive.org/web/20160305141652/http://www-conf.slac.stanford.edu/xldb2012/talks/xldb2012_wed_1400_MichaelHouston.pdf">Archived</a> 5 March 2016 at the <a href="/facts/Wayback_Machine/nmQ3a6JC">Wayback Machine</a></li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>Tarun Iyer (30 April 2013). "AMD Unveils its Heterogeneous Uniform Memory Access (hUMA) Technology". Tom's Hardware. <a href="http://www.tomshardware.com/news/AMD-HSA-hUMA-APU,22324.html" target="_blank">http://www.tomshardware.com/news/AMD-HSA-hUMA-APU,22324.html</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>George Kyriazis (30 August 2012). Heterogeneous System Architecture: A Technical Review (PDF) (Report). AMD. Archived from the original (PDF) on 28 March 2014. Retrieved 26 May 2014. <a href="https://web.archive.org/web/20140328140823/http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2012/10/hsa10.pdf" target="_blank">https://web.archive.org/web/20140328140823/http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2012/10/hsa10.pdf</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>"What is Heterogeneous System Architecture (HSA)?". AMD. Archived from the original on 21 June 2014. Retrieved 23 May 2014. <a href="https://web.archive.org/web/20140621213832/http://developer.amd.com/resources/heterogeneous-computing/what-is-heterogeneous-system-architecture-hsa/" target="_blank">https://web.archive.org/web/20140621213832/http://developer.amd.com/resources/heterogeneous-computing/what-is-heterogeneous-system-architecture-hsa/</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>Joel Hruska (26 August 2013). "Setting HSAIL: AMD explains the future of CPU/GPU cooperation". ExtremeTech. Ziff Davis. <a href="http://www.extremetech.com/gaming/164817-setting-hsail-amd-cpu-gpu-cooperation" target="_blank">http://www.extremetech.com/gaming/164817-setting-hsail-amd-cpu-gpu-cooperation</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>Linaro (21 March 2014). "LCE13: Heterogeneous System Architecture (HSA) on ARM". slideshare.net. <a href="https://www.slideshare.net/mobile/linaroorg/hsa-linaro-updatejuly102013" target="_blank">https://www.slideshare.net/mobile/linaroorg/hsa-linaro-updatejuly102013</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>"Heterogeneous System Architecture: Purpose and Outlook". gpuscience.com. 9 November 2012. Archived from the original on 1 February 2014. Retrieved 24 May 2014. <a href="https://web.archive.org/web/20140201183411/http://gpuscience.com/cs/heterogeneous-system-architecture-purpose-and-outlook/" target="_blank">https://web.archive.org/web/20140201183411/http://gpuscience.com/cs/heterogeneous-system-architecture-purpose-and-outlook/</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>"Heterogeneous system architecture: Multicore image processing using a mix of CPU and GPU elements". Embedded Computing Design. Retrieved 23 May 2014. <a href="http://embedded-computing.com/articles/heterogeneous-processing-using-mix-cpu-gpu-elements/" target="_blank">http://embedded-computing.com/articles/heterogeneous-processing-using-mix-cpu-gpu-elements/</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> <li id="fn:8"><p>George Kyriazis (30 August 2012). Heterogeneous System Architecture: A Technical Review (PDF) (Report). AMD. Archived from the original (PDF) on 28 March 2014. Retrieved 26 May 2014. <a href="https://web.archive.org/web/20140328140823/http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2012/10/hsa10.pdf" target="_blank">https://web.archive.org/web/20140328140823/http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2012/10/hsa10.pdf</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></p></li> <li id="fn:9"><p>"Heterogeneous System Architecture: Purpose and Outlook". gpuscience.com. 9 November 2012. Archived from the original on 1 February 2014. Retrieved 24 May 2014. <a href="https://web.archive.org/web/20140201183411/http://gpuscience.com/cs/heterogeneous-system-architecture-purpose-and-outlook/" target="_blank">https://web.archive.org/web/20140201183411/http://gpuscience.com/cs/heterogeneous-system-architecture-purpose-and-outlook/</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></p></li> <li id="fn:10"><p>"Linux kernel 3.19, Section 1.3. HSA driver for AMD GPU devices". kernelnewbies.org. 8 February 2015. Retrieved 12 February 2015. <a href="http://kernelnewbies.org/Linux_3.19#head-ae54e026ef7588f4431f7e94178d27d5cd830bbf" target="_blank">http://kernelnewbies.org/Linux_3.19#head-ae54e026ef7588f4431f7e94178d27d5cd830bbf</a> <a href="#fnref:10" class="footnote-back-ref">↩</a></p></li> <li id="fn:11"><p>"HSA-Runtime-Reference-Source/README.md at master". github.com. 14 November 2014. Retrieved 12 February 2015. <a href="https://github.com/HSAFoundation/HSA-Runtime-Reference-Source/blob/master/README.md" target="_blank">https://github.com/HSAFoundation/HSA-Runtime-Reference-Source/blob/master/README.md</a> <a href="#fnref:11" class="footnote-back-ref">↩</a></p></li> <li id="fn:12"><p>"Linux Kernel 4.14 Announced with Secure Memory Encryption and More". 13 November 2017. Archived from the original on 13 November 2017. <a href="https://web.archive.org/web/20171113231202/https://www.xda-developers.com/linux-kernel-414/" target="_blank">https://web.archive.org/web/20171113231202/https://www.xda-developers.com/linux-kernel-414/</a> <a href="#fnref:12" class="footnote-back-ref">↩</a></p></li> <li id="fn:13"><p>Alex Woodie (26 August 2013). "HSA Foundation Aims to Boost Java's GPU Prowess". HPCwire. <a href="http://www.hpcwire.com/2013/08/26/hsa_foundation_aims_to_boost_javas_gpu_prowess/" target="_blank">http://www.hpcwire.com/2013/08/26/hsa_foundation_aims_to_boost_javas_gpu_prowess/</a> <a href="#fnref:13" class="footnote-back-ref">↩</a></p></li> <li id="fn:14"><p>"Bolt on github". GitHub. 11 January 2022. <a href="https://github.com/HSA-Libraries/Bolt" target="_blank">https://github.com/HSA-Libraries/Bolt</a> <a href="#fnref:14" class="footnote-back-ref">↩</a></p></li> <li id="fn:15"><p>AMD GPUOpen (19 April 2016). "CodeXL 2.0 includes HSA profiler". Archived from the original on 27 June 2018. Retrieved 21 April 2016. <a href="https://web.archive.org/web/20180627034628/https://gpuopen.com/codexl-2-0-is-here-and-open-source/" target="_blank">https://web.archive.org/web/20180627034628/https://gpuopen.com/codexl-2-0-is-here-and-open-source/</a> <a href="#fnref:15" class="footnote-back-ref">↩</a></p></li> <li id="fn:16"><p>"AMD Announces the 7th Generation APU: Excavator mk2 in Bristol Ridge and Stoney Ridge for Notebooks". 31 May 2016. Retrieved 3 January 2020. <a href="https://www.anandtech.com/show/10362/amd-7th-generation-apu-bristol-ridge-stoney-ridge-for-notebooks" target="_blank">https://www.anandtech.com/show/10362/amd-7th-generation-apu-bristol-ridge-stoney-ridge-for-notebooks</a> <a href="#fnref:16" class="footnote-back-ref">↩</a></p></li> <li id="fn:17"><p>"AMD Mobile "Carrizo" Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015" (Press release). 20 November 2014. Retrieved 16 February 2015. <a href="https://www.amd.com/en-us/press-releases/Pages/amd-mobile-carrizo-2014nov20.aspx" target="_blank">https://www.amd.com/en-us/press-releases/Pages/amd-mobile-carrizo-2014nov20.aspx</a> <a href="#fnref:17" class="footnote-back-ref">↩</a></p></li> <li id="fn:18"><p>For FM2+ Excavator models: A8-7680, A6-7480 & Athlon X4 845. <a href="#fnref:18" class="footnote-back-ref">↩</a></p></li> <li id="fn:19"><p>"The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List". TechARP.com. Retrieved 13 December 2017. <a href="https://www.techarp.com/guides/mobile-cpu-comparison-guide/5/" target="_blank">https://www.techarp.com/guides/mobile-cpu-comparison-guide/5/</a> <a href="#fnref:19" class="footnote-back-ref">↩</a></p></li> <li id="fn:20"><p>A PC would be one node. <a href="#fnref:20" class="footnote-back-ref">↩</a></p></li> <li id="fn:21"><p>An APU combines a CPU and a GPU. Both have cores. <a href="#fnref:21" class="footnote-back-ref">↩</a></p></li> <li id="fn:22"><p>Requires firmware support. <a href="#fnref:22" class="footnote-back-ref">↩</a></p></li> <li id="fn:23"><p>Requires firmware support. <a href="#fnref:23" class="footnote-back-ref">↩</a></p></li> <li id="fn:24"><p>Requires firmware support. <a href="#fnref:24" class="footnote-back-ref">↩</a></p></li> <li id="fn:25"><p>No SSE4. No SSSE3. <a href="#fnref:25" class="footnote-back-ref">↩</a></p></li> <li id="fn:26"><p>"AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver". VideoCardz.com. Retrieved 6 June 2017. <a href="http://videocardz.com/62250/amd-vega10-and-vega11-gpus-spotted-in-opencl-driver/" target="_blank">http://videocardz.com/62250/amd-vega10-and-vega11-gpus-spotted-in-opencl-driver/</a> <a href="#fnref:26" class="footnote-back-ref">↩</a></p></li> <li id="fn:27"><p>"AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver". VideoCardz.com. Retrieved 6 June 2017. <a href="http://videocardz.com/62250/amd-vega10-and-vega11-gpus-spotted-in-opencl-driver/" target="_blank">http://videocardz.com/62250/amd-vega10-and-vega11-gpus-spotted-in-opencl-driver/</a> <a href="#fnref:27" class="footnote-back-ref">↩</a></p></li> <li id="fn:28"><p>Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation. <a href="/wiki/Single-precision_floating-point_format" target="_blank">/wiki/Single-precision_floating-point_format</a> <a href="#fnref:28" class="footnote-back-ref">↩</a></p></li> <li id="fn:29"><p>Unified shaders : texture mapping units : render output units <a href="/wiki/Unified_shader_model" target="_blank">/wiki/Unified_shader_model</a> <a href="#fnref:29" class="footnote-back-ref">↩</a></p></li> <li id="fn:30"><p>Cutress, Ian (1 February 2018). "Zen Cores and Vega: Ryzen APUs for AM4 – AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm". Anandtech. Retrieved 7 February 2018. <a href="https://www.anandtech.com/show/12233/amd-tech-day-at-ces-2018-roadmap-revealed-with-ryzen-apus-zen-on-12nm-vega-on-7nm/3" target="_blank">https://www.anandtech.com/show/12233/amd-tech-day-at-ces-2018-roadmap-revealed-with-ryzen-apus-zen-on-12nm-vega-on-7nm/3</a> <a href="#fnref:30" class="footnote-back-ref">↩</a></p></li> <li id="fn:31"><p>Larabel, Michael (17 November 2017). "Radeon VCN Encode Support Lands in Mesa 17.4 Git". Phoronix. Retrieved 20 November 2017. <a href="https://www.phoronix.com/scan.php?page=news_item&px=Radeon-VCN-Encode-Lands" target="_blank">https://www.phoronix.com/scan.php?page=news_item&px=Radeon-VCN-Encode-Lands</a> <a href="#fnref:31" class="footnote-back-ref">↩</a></p></li> <li id="fn:32"><p>"AMD Ryzen 5000G 'Cezanne' APU Gets First High-Res Die Shots, 10.7 Billion Transistors In A 180mm2 Package". wccftech. 12 August 2021. Retrieved 25 August 2021. <a href="https://wccftech.com/amd-ryzen-5000g-cezanne-apu-first-high-res-die-shots-10-7-billion-transistors/" target="_blank">https://wccftech.com/amd-ryzen-5000g-cezanne-apu-first-high-res-die-shots-10-7-billion-transistors/</a> <a href="#fnref:32" class="footnote-back-ref">↩</a></p></li> <li id="fn:33"><p>"AMD Ryzen 5000G 'Cezanne' APU Gets First High-Res Die Shots, 10.7 Billion Transistors In A 180mm2 Package". wccftech. 12 August 2021. Retrieved 25 August 2021. <a href="https://wccftech.com/amd-ryzen-5000g-cezanne-apu-first-high-res-die-shots-10-7-billion-transistors/" target="_blank">https://wccftech.com/amd-ryzen-5000g-cezanne-apu-first-high-res-die-shots-10-7-billion-transistors/</a> <a href="#fnref:33" class="footnote-back-ref">↩</a></p></li> <li id="fn:34"><p>Tony Chen; Jason Greaves, "AMD's Graphics Core Next (GCN) Architecture" (PDF), AMD, retrieved 13 August 2016 <a href="http://meseec.ce.rit.edu/551-projects/fall2014/3-4.pdf" target="_blank">http://meseec.ce.rit.edu/551-projects/fall2014/3-4.pdf</a> <a href="#fnref:34" class="footnote-back-ref">↩</a></p></li> <li id="fn:35"><p>"A technical look at AMD's Kaveri architecture". Semi Accurate. Retrieved 6 July 2014. <a href="http://semiaccurate.com/2014/01/15/technical-look-amds-kaveri-architecture/" target="_blank">http://semiaccurate.com/2014/01/15/technical-look-amds-kaveri-architecture/</a> <a href="#fnref:35" class="footnote-back-ref">↩</a></p></li> <li id="fn:36"><p>To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup. <a href="#fnref:36" class="footnote-back-ref">↩</a></p></li> <li id="fn:37"><p>To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup. <a href="#fnref:37" class="footnote-back-ref">↩</a></p></li> <li id="fn:38"><p>To feed more than two displays, the additional panels must have native DisplayPort support.[25] Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed. <a href="/wiki/DisplayPort" target="_blank">/wiki/DisplayPort</a> <a href="#fnref:38" class="footnote-back-ref">↩</a></p></li> <li id="fn:39"><p>DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version. <a href="/wiki/Direct_Rendering_Manager" target="_blank">/wiki/Direct_Rendering_Manager</a> <a href="#fnref:39" class="footnote-back-ref">↩</a></p></li> <li id="fn:40"><p>Airlie, David (26 November 2009). "DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33". Retrieved 16 January 2016. <a href="http://airlied.livejournal.com/68805.html" target="_blank">http://airlied.livejournal.com/68805.html</a> <a href="#fnref:40" class="footnote-back-ref">↩</a></p></li> <li id="fn:41"><p>"Radeon feature matrix". freedesktop.org. Retrieved 10 January 2016. <a href="http://xorg.freedesktop.org/wiki/RadeonFeature/" target="_blank">http://xorg.freedesktop.org/wiki/RadeonFeature/</a> <a href="#fnref:41" class="footnote-back-ref">↩</a></p></li> <li id="fn:42"><p>DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version. <a href="/wiki/Direct_Rendering_Manager" target="_blank">/wiki/Direct_Rendering_Manager</a> <a href="#fnref:42" class="footnote-back-ref">↩</a></p></li> <li id="fn:43"><p>Deucher, Alexander (16 September 2015). "XDC2015: AMDGPU" (PDF). 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"[ANNOUNCE] xf86-video-amdgpu 1.2.0". lists.x.org. <a href="https://lists.x.org/archives/xorg-announce/2016-November/002741.html" target="_blank">https://lists.x.org/archives/xorg-announce/2016-November/002741.html</a> <a href="#fnref:45" class="footnote-back-ref">↩</a></p></li> <li id="fn:46"><p>"ARM Bifrost GPU Architecture". 30 May 2016. <a href="http://www.anandtech.com/show/10375/arm-unveils-bifrost-and-mali-g71/5" target="_blank">http://www.anandtech.com/show/10375/arm-unveils-bifrost-and-mali-g71/5</a> <a href="#fnref:46" class="footnote-back-ref">↩</a></p></li> </ol>