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List of semiconductor scale examples
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Listed are many semiconductor scale examples for various metal–oxide–semiconductor field-effect transistor (MOSFET, or MOS transistor) semiconductor manufacturing process nodes.

Timeline of MOSFET demonstrations

See also: MOSFET, Semiconductor device fabrication, and Transistor density

PMOS and NMOS

MOSFET (PMOS and NMOS) demonstrations
DateChannel lengthOxide thickness1MOSFET logicResearcher(s)OrganizationRef
June 196020,000 nm100 nmPMOSMohamed M. Atalla, Dawon KahngBell Telephone Laboratories23
NMOS
10,000 nm100 nmPMOSMohamed M. Atalla, Dawon KahngBell Telephone Laboratories4
NMOS
May 19658,000 nm150 nmNMOSChih-Tang Sah, Otto Leistiko, A.S. GroveFairchild Semiconductor5
5,000 nm170 nmPMOS
December 19721,000 nm?PMOSRobert H. Dennard, Fritz H. Gaensslen, Hwa-Nien YuIBM T.J. Watson Research Center678
19737,500 nm?NMOSSohichi SuzukiNEC910
6,000 nm?PMOS?Toshiba1112
October 19741,000 nm35 nmNMOSRobert H. Dennard, Fritz H. Gaensslen, Hwa-Nien YuIBM T.J. Watson Research Center13
500 nm
September 19751,500 nm20 nmNMOSRyoichi Hori, Hiroo Masuda, Osamu MinatoHitachi1415
March 19763,000 nm?NMOS?Intel16
April 19791,000 nm25 nmNMOSWilliam R. Hunter, L. M. Ephrath, Alice CramerIBM T.J. Watson Research Center17
December 1984100 nm5 nmNMOSToshio Kobayashi, Seiji Horiguchi, K. KiuchiNippon Telegraph and Telephone18
December 1985150 nm2.5 nmNMOSToshio Kobayashi, Seiji Horiguchi, M. Miyake, M. OdaNippon Telegraph and Telephone19
75 nm?NMOSStephen Y. Chou, Henry I. Smith, Dimitri A. AntoniadisMIT20
January 198660 nm?NMOSStephen Y. Chou, Henry I. Smith, Dimitri A. AntoniadisMIT21
June 1987200 nm3.5 nmPMOSToshio Kobayashi, M. Miyake, K. DeguchiNippon Telegraph and Telephone22
December 199340 nm?NMOSMizuki Ono, Masanobu Saito, Takashi YoshitomiToshiba23
September 199616 nm?PMOSHisao Kawaura, Toshitsugu Sakamoto, Toshio BabaNEC24
June 199850 nm1.3 nmNMOSKhaled Z. Ahmed, Effiong E. Ibok, Miryeong SongAdvanced Micro Devices (AMD)2526
December 20026 nm?PMOSBruce Doris, Omer Dokumaci, Meikei IeongIBM272829
December 20033 nm?PMOSHitoshi Wakabayashi, Shigeharu YamagamiNEC3031
?NMOS

CMOS (single-gate)

Complementary MOSFET (CMOS) demonstrations (single-gate)
DateChannel lengthOxide thickness32Researcher(s)OrganizationRef
February 1963??Chih-Tang Sah, Frank WanlassFairchild Semiconductor3334
196820,000 nm100 nm?RCA Laboratories35
197010,000 nm100 nm?RCA Laboratories36
December 19762,000 nm?A. Aitken, R.G. Poulsen, A.T.P. MacArthur, J.J. WhiteMitel Semiconductor37
February 19783,000 nm?Toshiaki Masuhara, Osamu Minato, Toshio Sasaki, Yoshio SakaiHitachi Central Research Laboratory383940
February 19831,200 nm25 nmR.J.C. Chwang, M. Choi, D. Creek, S. Stern, P.H. PelleyIntel4142
900 nm15 nmTsuneo Mano, J. Yamada, Junichi Inoue, S. NakajimaNippon Telegraph and Telephone (NTT)4344
December 19831,000 nm22.5 nmG.J. Hu, Yuan Taur, Robert H. Dennard, Chung-Yu TingIBM T.J. Watson Research Center45
February 1987800 nm17 nmT. Sumi, Tsuneo Taniguchi, Mikio Kishimoto, Hiroshige HiranoMatsushita4647
700 nm12 nmTsuneo Mano, J. Yamada, Junichi Inoue, S. NakajimaNippon Telegraph and Telephone (NTT)4849
September 1987500 nm12.5 nmHussein I. Hanafi, Robert H. Dennard, Yuan Taur, Nadim F. HaddadIBM T.J. Watson Research Center50
December 1987250 nm?Naoki Kasai, Nobuhiro Endo, Hiroshi KitajimaNEC51
February 1988400 nm10 nmM. Inoue, H. Kotani, T. Yamada, Hiroyuki YamauchiMatsushita5253
December 1990100 nm?Ghavam G. Shahidi, Bijan Davari, Yuan Taur, James D. WarnockIBM T.J. Watson Research Center54
1993350 nm??Sony55
1996150 nm??Mitsubishi Electric
1998180 nm??TSMC56
December 20035 nm?Hitoshi Wakabayashi, Shigeharu Yamagami, Nobuyuki IkezawaNEC5758

Multi-gate MOSFET (MuGFET)

Multi-gateMOSFET (MuGFET) demonstrations
DateChannel lengthMuGFET typeResearcher(s)OrganizationRef
August 1984?DGMOSToshihiro Sekigawa, Yutaka HayashiElectrotechnical Laboratory (ETL)59
19872,000 nmDGMOSToshihiro SekigawaElectrotechnical Laboratory (ETL)60
December 1988250 nmDGMOSBijan Davari, Wen-Hsing Chang, Matthew R. Wordeman, C.S. OhIBM T.J. Watson Research Center6162
180 nm
?GAAFETFujio Masuoka, Hiroshi Takato, Kazumasa Sunouchi, N. OkabeToshiba636465
December 1989200 nmFinFETDigh Hisamoto, Toru Kaga, Yoshifumi Kawamoto, Eiji TakedaHitachi Central Research Laboratory666768
December 199817 nmFinFETDigh Hisamoto, Chenming Hu, Tsu-Jae King Liu, Jeffrey BokorUniversity of California (Berkeley)6970
200115 nmFinFETChenming Hu, Yang-Kyu Choi, Nick Lindert, Tsu-Jae King LiuUniversity of California (Berkeley)7172
December 200210 nmFinFETShibly Ahmed, Scott Bell, Cyrus Tabery, Jeffrey BokorUniversity of California (Berkeley)7374
June 20063 nmGAAFETHyunjin Lee, Yang-kyu Choi, Lee-Eun Yu, Seong-Wan RyuKAIST7576

Other types of MOSFET

MOSFET demonstrations (other types)
DateChannellength(nm)Oxidethickness(nm)77MOSFETtypeResearcher(s)OrganizationRef
October 1962??TFTPaul K. WeimerRCA Laboratories7879
1965??GaAsH. Becke, R. Hall, J. WhiteRCA Laboratories80
October 1966100,000100TFTT.P. Brody, H.E. KunigWestinghouse Electric8182
August 1967??FGMOSDawon Kahng, Simon Min SzeBell Telephone Laboratories83
October 1967??MNOSH.A. Richard Wegener, A.J. Lincoln, H.C. PaoSperry Corporation84
July 1968??BiMOSHung-Chang Lin, Ramachandra R. IyerWestinghouse Electric8586
October 1968??BiCMOSHung-Chang Lin, Ramachandra R. Iyer, C.T. HoWestinghouse Electric8788
1969??VMOS?Hitachi8990
September 1969??DMOSY. Tarui, Y. Hayashi, Toshihiro SekigawaElectrotechnical Laboratory (ETL)9192
October 1970??ISFETPiet BergveldUniversity of Twente9394
October 19701000?DMOSY. Tarui, Y. Hayashi, Toshihiro SekigawaElectrotechnical Laboratory (ETL)95
1977??VDMOSJohn Louis MollHP Labs96
??LDMOS?Hitachi97
July 1979??IGBTBantval Jayant Baliga, Margaret LazeriGeneral Electric98
December 19842000?BiCMOSH. Higuchi, Goro Kitsukawa, Takahide Ikeda, Y. NishioHitachi99
May 1985300??K. Deguchi, Kazuhiko Komatsu, M. Miyake, H. NamatsuNippon Telegraph and Telephone100
February 19851000?BiCMOSH. Momose, Hideki Shibata, S. Saitoh, Jun-ichi MiyamotoToshiba101
November 1986908.3?Han-Sheng Lee, L.C. PuzioGeneral Motors102
December 198660??Ghavam G. Shahidi, Dimitri A. Antoniadis, Henry I. SmithMIT103104
May 1987?10?Bijan Davari, Chung-Yu Ting, Kie Y. Ahn, S. BasavaiahIBM T.J. Watson Research Center105
December 1987800?BiCMOSRobert H. Havemann, R. E. Eklund, Hiep V. TranTexas Instruments106
June 199730?EJ-MOSFETHisao Kawaura, Toshitsugu Sakamoto, Toshio BabaNEC107
199832???NEC108
19998???
April 20008?EJ-MOSFETHisao Kawaura, Toshitsugu Sakamoto, Toshio BabaNEC109

Commercial products using micro-scale MOSFETs

Products featuring 20 μm manufacturing process

Products featuring 10 μm manufacturing process

Main article: 10 μm process

Products featuring 8 μm manufacturing process

Products featuring 6 μm manufacturing process

Main article: 6 μm process

Products featuring 3 μm manufacturing process

Main article: 3 μm process

Products featuring 1.5 μm manufacturing process

Main article: 1.5 μm process

Products featuring 1 μm manufacturing process

Main article: 1 μm process

  • NTT's DRAM memory chips, including its 64 kb chip in 1979 and 256 kb chip in 1980.122
  • NEC's 1 Mb DRAM memory chip in 1984.123
  • Intel 80386 CPU launched in 1985.

Products featuring 800 nm manufacturing process

Main article: 800 nm process

Products featuring 600 nm manufacturing process

Main article: 600 nm process

Products featuring 350 nm manufacturing process

Main article: 350 nm process

Products featuring 250 nm manufacturing process

Main article: 250 nm process

Processors using 180 nm manufacturing technology

Main article: 180 nm process

Processors using 130 nm manufacturing technology

Main article: 130 nm process

Commercial products using nano-scale MOSFETs

See also: Nanoelectronics and Nanocircuitry

Chips using 90 nm manufacturing technology

Main article: 90 nm process

Processors using 65 nm manufacturing technology

Main article: 65 nm process

Processors using 45 nm technology

Main article: 45 nm process

Chips using 32 nm technology

Main article: 32 nm process

  • Toshiba produced commercial 32 Gb NAND flash memory chips with the 32 nm process in 2009.145
  • Intel Core i3 and i5 processors, released in January 2010146
  • Intel 6-core processor, codenamed Gulftown147
  • Intel i7-970, was released in late July 2010, priced at approximately US$900
  • AMD FX Series processors, codenamed Zambezi and based on AMD's Bulldozer architecture, were released in October 2011. The technology used a 32 nm SOI process, two CPU cores per module, and up to four modules, ranging from a quad-core design costing approximately US$130 to a $280 eight-core design.
  • Ambarella Inc. announced the availability of the A7L system-on-a-chip circuit for digital still cameras, providing 1080p60 high-definition video capabilities in September 2011148

Chips using 24–28 nm technology

  • SK Hynix announced that it could produce a 26 nm flash chip with 64 Gb capacity; Intel Corp. and Micron Technology had by then already developed the technology themselves. Announced in 2010.149
  • Toshiba announced that it was shipping 24 nm flash memory NAND devices on August 31, 2010.150
  • In 2016 MCST's 28 nm processor Elbrus-8S went for serial production.151152

Chips using 22 nm technology

Main article: 22 nm process

  • Intel Core i7 and Intel Core i5 processors based on Intel's Ivy Bridge 22 nm technology for series 7 chip-sets went on sale worldwide on April 23, 2012.153

Chips using 20 nm technology

Chips using 16 nm technology

Chips using 14 nm technology

Main article: 14 nm process

  • Intel Core i7 and Intel Core i5 processors based on Intel's Broadwell 14 nm technology was launched in January 2015.156
  • AMD Ryzen processors based on AMD's Zen or Zen+ architectures and which uses 14 nm FinFET technology.157

Chips using 10 nm technology

Main article: 10 nm process

Chips using 7 nm technology

Main article: 7 nm process

  • TSMC began risk production of 256 Mbit SRAM memory chips using a 7 nm process in April 2017.163
  • Samsung and TSMC began mass production of 7 nm devices in 2018.164
  • Apple A12 and Huawei Kirin 980 mobile processors, both released in 2018, use 7 nm chips manufactured by TSMC.165
  • AMD began using TSMC 7 nm starting with the Vega 20 GPU in November 2018,166 with Zen 2-based CPUs and APUs from July 2019,167 and for both PlayStation 5 168 and Xbox Series X/S 169 consoles' APUs, released both in November 2020.

Chips using 5 nm technology

Main article: 5 nm process

  • Samsung began production of 5 nm chips (5LPE) in late 2018.170
  • TSMC began production of 5 nm chips (CLN5FF) in April 2019.171

Chips using 3 nm technology

Main article: 3 nm process

See also

References

  1. "Angstrom". Collins English Dictionary. Retrieved 2019-03-02. https://www.collinsdictionary.com/dictionary/english/angstrom

  2. Sze, Simon M. (2002). Semiconductor Devices: Physics and Technology (PDF) (2nd ed.). Wiley. p. 4. ISBN 0-471-33372-7. 0-471-33372-7

  3. Atalla, Mohamed M.; Kahng, Dawon (June 1960). "Silicon–silicon dioxide field induced surface devices". IRE-AIEE Solid State Device Research Conference. Carnegie Mellon University Press. /wiki/Mohamed_M._Atalla

  4. Voinigescu, Sorin (2013). High-Frequency Integrated Circuits. Cambridge University Press. p. 164. ISBN 9780521873024. 9780521873024

  5. Sah, Chih-Tang; Leistiko, Otto; Grove, A. S. (May 1965). "Electron and hole mobilities in inversion layers on thermally oxidized silicon surfaces". IEEE Transactions on Electron Devices. 12 (5): 248–254. Bibcode:1965ITED...12..248L. doi:10.1109/T-ED.1965.15489. Archived from the original on 2021-04-14. Retrieved 2019-09-26. /wiki/Chih-Tang_Sah

  6. Dennard, Robert H.; Gaensslen, Fritz H.; Yu, Hwa-Nien; Kuhn, L. (December 1972). "Design of micron MOS switching devices". 1972 International Electron Devices Meeting. 1972 International Electron Devices Meeting. pp. 168–170. doi:10.1109/IEDM.1972.249198. /wiki/Robert_H._Dennard

  7. Hori, Ryoichi; Masuda, Hiroo; Minato, Osamu; Nishimatsu, Shigeru; Sato, Kikuji; Kubo, Masaharu (September 1975). "Short Channel MOS-IC Based on Accurate Two Dimensional Device Design". Japanese Journal of Applied Physics. 15 (S1): 193. doi:10.7567/JJAPS.15S1.193. ISSN 1347-4065. https://doi.org/10.7567%2FJJAPS.15S1.193

  8. Critchlow, D. L. (2007). "Recollections on MOSFET Scaling". IEEE Solid-State Circuits Society Newsletter. 12 (1): 19–22. doi:10.1109/N-SSC.2007.4785536. https://doi.org/10.1109%2FN-SSC.2007.4785536

  9. "1970s: Development and evolution of microprocessors" (PDF). Semiconductor History Museum of Japan. Retrieved 27 June 2019. http://www.shmj.or.jp/english/pdf/ic/exhibi748E.pdf

  10. "NEC 751 (uCOM-4)". The Antique Chip Collector's Page. Archived from the original on 2011-05-25. Retrieved 2010-06-11. https://web.archive.org/web/20110525202756/http://www.antiquetech.com/chips/NEC751.htm

  11. "1973: 12-bit engine-control microprocessor (Toshiba)" (PDF). Semiconductor History Museum of Japan. Retrieved 27 June 2019. http://www.shmj.or.jp/english/pdf/ic/exhibi739E.pdf

  12. Belzer, Jack; Holzman, Albert G.; Kent, Allen (1978). Encyclopedia of Computer Science and Technology: Volume 10 – Linear and Matrix Algebra to Microorganisms: Computer-Assisted Identification. CRC Press. p. 402. ISBN 9780824722609.Corder, Mike (Spring 1999). "Big Things in Small Packages". Pioneers' Progress with picoJava Technology. Sun Microelectronics. Archived from the original on 2006-03-12. Retrieved April 23, 2012. The first 6502 was fabricated with 8 micron technology, ran at one megahertz and had a maximum memory of 64k. 9780824722609

  13. Dennard, Robert H.; Gaensslen, F. H.; Yu, Hwa-Nien; Rideout, V. L.; Bassous, E.; LeBlanc, A. R. (October 1974). "Design of ion-implanted MOSFET's with very small physical dimensions" (PDF). IEEE Journal of Solid-State Circuits. 9 (5): 256–268. Bibcode:1974IJSSC...9..256D. CiteSeerX 10.1.1.334.2417. doi:10.1109/JSSC.1974.1050511. S2CID 283984. /wiki/Robert_H._Dennard

  14. Hori, Ryoichi; Masuda, Hiroo; Minato, Osamu; Nishimatsu, Shigeru; Sato, Kikuji; Kubo, Masaharu (September 1975). "Short Channel MOS-IC Based on Accurate Two Dimensional Device Design". Japanese Journal of Applied Physics. 15 (S1): 193. doi:10.7567/JJAPS.15S1.193. ISSN 1347-4065. https://doi.org/10.7567%2FJJAPS.15S1.193

  15. Kubo, Masaharu; Hori, Ryoichi; Minato, Osamu; Sato, Kikuji (February 1976). "A threshold voltage controlling circuit for short channel MOS integrated circuits". 1976 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. 1976 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. Vol. XIX. pp. 54–55. doi:10.1109/ISSCC.1976.1155515. S2CID 21048622."History of the Intel Microprocessor - Listoid". Archived from the original on 2015-04-27. Retrieved 2019-07-02. /wiki/Doi_(identifier)

  16. "Intel Microprocessor Quick Reference Guide". Intel. Retrieved 27 June 2019."Design case history: the Commodore 64" (PDF). IEEE Spectrum. Archived from the original (PDF) on May 13, 2012. Retrieved 1 September 2019. https://www.intel.com/pressroom/kits/quickrefyr.htm

  17. Hunter, William R.; Ephrath, L. M.; Cramer, Alice; Grobman, W. D.; Osburn, C. M.; Crowder, B. L.; Luhn, H. E. (April 1979). "1 /spl mu/m MOSFET VLSI technology. V. A single-level polysilicon technology using electron-beam lithography". IEEE Journal of Solid-State Circuits. 14 (2): 275–281. doi:10.1109/JSSC.1979.1051174. S2CID 26389509."Emotion Engine and Graphics Synthesizer Used in the Core of PlayStation Become One Chip" (PDF) (Press release). Sony. 21 April 2003. Retrieved 26 June 2019. /wiki/IEEE_Journal_of_Solid-State_Circuits

  18. Kobayashi, Toshio; Horiguchi, Seiji; Kiuchi, K. (December 1984). "Deep-submicron MOSFET characteristics with 5 nm gate oxide". 1984 International Electron Devices Meeting. pp. 414–417. doi:10.1109/IEDM.1984.190738. S2CID 46729489."Toshiba Makes Major Advances in NAND Flash Memory with 3-bit-per-cell 32nm generation and with 4-bit-per-cell 43nm technology". Toshiba. 11 February 2009. Retrieved 21 June 2019. /wiki/Doi_(identifier)

  19. Kobayashi, Toshio; Horiguchi, Seiji; Miyake, M.; Oda, M.; Kiuchi, K. (December 1985). "Extremely high transconductance (Above 500 mS/Mm) MOSFET with 2.5 nm gate oxide". 1985 International Electron Devices Meeting. pp. 761–763. doi:10.1109/IEDM.1985.191088. S2CID 22309664. /wiki/Doi_(identifier)

  20. Chou, Stephen Y.; Antoniadis, Dimitri A.; Smith, Henry I. (December 1985). "Observation of electron velocity overshoot in sub-100-nm-channel MOSFET's in Silicon". IEEE Electron Device Letters. 6 (12): 665–667. Bibcode:1985IEDL....6..665C. doi:10.1109/EDL.1985.26267. S2CID 28493431."16/12nm Technology". TSMC. Retrieved 30 June 2019. /wiki/IEEE_Electron_Device_Letters

  21. Chou, Stephen Y.; Smith, Henry I.; Antoniadis, Dimitri A. (January 1986). "Sub-100-nm channel-length transistors fabricated using x-ray lithography". Journal of Vacuum Science & Technology B: Microelectronics Processing and Phenomena. 4 (1): 253–255. Bibcode:1986JVSTB...4..253C. doi:10.1116/1.583451. ISSN 0734-211X. /wiki/Bibcode_(identifier)

  22. Kobayashi, Toshio; Miyake, M.; Deguchi, K.; Kimizuka, M.; Horiguchi, Seiji; Kiuchi, K. (1987). "Subhalf-micrometer p-channel MOSFET's with 3.5-nm gate Oxide fabricated using X-ray lithography". IEEE Electron Device Letters. 8 (6): 266–268. Bibcode:1987IEDL....8..266M. doi:10.1109/EDL.1987.26625. S2CID 38828156. /wiki/IEEE_Electron_Device_Letters

  23. Ono, Mizuki; Saito, Masanobu; Yoshitomi, Takashi; Fiegna, Claudio; Ohguro, Tatsuya; Iwai, Hiroshi (December 1993). "Sub-50 nm gate length n-MOSFETs with 10 nm phosphorus source and drain junctions". Proceedings of IEEE International Electron Devices Meeting. pp. 119–122. doi:10.1109/IEDM.1993.347385. ISBN 0-7803-1450-6. S2CID 114633315. 0-7803-1450-6

  24. Kawaura, Hisao; Sakamoto, Toshitsugu; Baba, Toshio; Ochiai, Yukinori; Fujita, Jun'ichi; Matsui, Shinji; Sone, Jun'ichi (1997). "Proposal of Pseudo Source and Drain MOSFETs for Evaluating 10-nm Gate MOSFETs". Japanese Journal of Applied Physics. 36 (3S): 1569. Bibcode:1997JaJAP..36.1569K. doi:10.1143/JJAP.36.1569. ISSN 1347-4065. S2CID 250846435. /wiki/Japanese_Journal_of_Applied_Physics

  25. Ahmed, Khaled Z.; Ibok, Effiong E.; Song, Miryeong; Yeap, Geoffrey; Xiang, Qi; Bang, David S.; Lin, Ming-Ren (1998). "Performance and reliability of sub-100 nm MOSFETs with ultra thin direct tunneling gate oxides". 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No. 98CH36216). pp. 160–161. doi:10.1109/VLSIT.1998.689240. ISBN 0-7803-4770-6. S2CID 109823217. 0-7803-4770-6

  26. Ahmed, Khaled Z.; Ibok, Effiong E.; Song, Miryeong; Yeap, Geoffrey; Xiang, Qi; Bang, David S.; Lin, Ming-Ren (1998). "Sub-100 nm nMOSFETs with direct tunneling thermal, nitrous and nitric oxides". 56th Annual Device Research Conference Digest (Cat. No. 98TH8373). pp. 10–11. doi:10.1109/DRC.1998.731099. ISBN 0-7803-4995-4. S2CID 1849364. 0-7803-4995-4

  27. Doris, Bruce B.; Dokumaci, Omer H.; Ieong, Meikei K.; Mocuta, Anda; Zhang, Ying; Kanarsky, Thomas S.; Roy, R. A. (December 2002). "Extreme scaling with ultra-thin Si channel MOSFETs". Digest. International Electron Devices Meeting. pp. 267–270. doi:10.1109/IEDM.2002.1175829. ISBN 0-7803-7462-2. S2CID 10151651. 0-7803-7462-2

  28. Schwierz, Frank; Wong, Hei; Liou, Juin J. (2010). Nanometer CMOS. Pan Stanford Publishing. p. 17. ISBN 9789814241083. 9789814241083

  29. "IBM claims world's smallest silicon transistor – TheINQUIRER". Theinquirer.net. 2002-12-09. Archived from the original on May 31, 2011. Retrieved 7 December 2017. https://web.archive.org/web/20110531040504/http://www.theinquirer.net/inquirer/news/1034321/ibm-claims-worlds-smallest-silicon-transistor

  30. Wakabayashi, Hitoshi; Yamagami, Shigeharu; Ikezawa, Nobuyuki; Ogura, Atsushi; Narihiro, Mitsuru; Arai, K.; Ochiai, Y.; Takeuchi, K.; Yamamoto, T.; Mogami, T. (December 2003). "Sub-10-nm planar-bulk-CMOS devices using lateral junction control". IEEE International Electron Devices Meeting 2003. pp. 20.7.1–20.7.3. doi:10.1109/IEDM.2003.1269446. ISBN 0-7803-7872-5. S2CID 2100267. 0-7803-7872-5

  31. Schwierz, Frank; Wong, Hei; Liou, Juin J. (2010). Nanometer CMOS. Pan Stanford Publishing. p. 17. ISBN 9789814241083. 9789814241083

  32. "Angstrom". Collins English Dictionary. Retrieved 2019-03-02. https://www.collinsdictionary.com/dictionary/english/angstrom

  33. "1963: Complementary MOS Circuit Configuration is Invented". Computer History Museum. Retrieved 6 July 2019. https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/

  34. Sah, Chih-Tang; Wanlass, Frank (February 1963). Nanowatt logic using field-effect metal–oxide semiconductor triodes. 1963 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. Vol. VI. pp. 32–33. doi:10.1109/ISSCC.1963.1157450. /wiki/Chih-Tang_Sah

  35. Lojek, Bo (2007). History of Semiconductor Engineering. Springer Science & Business Media. p. 330. ISBN 9783540342588. 9783540342588

  36. Lojek, Bo (2007). History of Semiconductor Engineering. Springer Science & Business Media. p. 330. ISBN 9783540342588. 9783540342588

  37. Aitken, A.; Poulsen, R. G.; MacArthur, A. T. P.; White, J. J. (December 1976). "A fully plasma etched-ion implanted CMOS process". 1976 International Electron Devices Meeting. 1976 International Electron Devices Meeting. pp. 209–213. doi:10.1109/IEDM.1976.189021. S2CID 24526762. /wiki/Doi_(identifier)

  38. "1978: Double-well fast CMOS SRAM (Hitachi)" (PDF). Semiconductor History Museum of Japan. Retrieved 5 July 2019. http://www.shmj.or.jp/english/pdf/ic/exhibi727E.pdf

  39. Masuhara, Toshiaki; Minato, Osamu; Sasaki, Toshio; Sakai, Yoshio; Kubo, Masaharu; Yasui, Tokumasa (February 1978). "A high-speed, low-power Hi-CMOS 4K static RAM". 1978 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. 1978 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. Vol. XXI. pp. 110–111. doi:10.1109/ISSCC.1978.1155749. S2CID 30753823. /wiki/Doi_(identifier)

  40. Masuhara, Toshiaki; Minato, Osamu; Sakai, Yoshi; Sasaki, Toshio; Kubo, Masaharu; Yasui, Tokumasa (September 1978). "Short Channel Hi-CMOS Device and Circuits". ESSCIRC 78: 4th European Solid State Circuits Conference – Digest of Technical Papers: 131–132. https://ieeexplore.ieee.org/document/5469023

  41. Gealow, Jeffrey Carl (10 August 1990). "Impact of Processing Technology on DRAM Sense Amplifier Design" (PDF). Massachusetts Institute of Technology. pp. 149–166. Retrieved 25 June 2019 – via CORE. https://core.ac.uk/download/pdf/4426308.pdf

  42. Chwang, R. J. C.; Choi, M.; Creek, D.; Stern, S.; Pelley, P. H.; Schutz, Joseph D.; Bohr, M. T.; Warkentin, P. A.; Yu, K. (February 1983). "A 70ns high density CMOS DRAM". 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. Vol. XXVI. pp. 56–57. doi:10.1109/ISSCC.1983.1156456. S2CID 29882862. /wiki/Doi_(identifier)

  43. Gealow, Jeffrey Carl (10 August 1990). "Impact of Processing Technology on DRAM Sense Amplifier Design" (PDF). Massachusetts Institute of Technology. pp. 149–166. Retrieved 25 June 2019 – via CORE. https://core.ac.uk/download/pdf/4426308.pdf

  44. Mano, Tsuneo; Yamada, J.; Inoue, Junichi; Nakajima, S. (February 1983). "Submicron VLSI memory circuits". 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. Vol. XXVI. pp. 234–235. doi:10.1109/ISSCC.1983.1156549. S2CID 42018248. /wiki/Doi_(identifier)

  45. Hu, G. J.; Taur, Yuan; Dennard, Robert H.; Terman, L. M.; Ting, Chung-Yu (December 1983). "A self-aligned 1-μm CMOS technology for VLSI". 1983 International Electron Devices Meeting. pp. 739–741. doi:10.1109/IEDM.1983.190615. S2CID 20070619. /wiki/Robert_H._Dennard

  46. Gealow, Jeffrey Carl (10 August 1990). "Impact of Processing Technology on DRAM Sense Amplifier Design" (PDF). Massachusetts Institute of Technology. pp. 149–166. Retrieved 25 June 2019 – via CORE. https://core.ac.uk/download/pdf/4426308.pdf

  47. Sumi, T.; Taniguchi, Tsuneo; Kishimoto, Mikio; Hirano, Hiroshige; Kuriyama, H.; Nishimoto, T.; Oishi, H.; Tetakawa, S. (1987). "A 60ns 4Mb DRAM in a 300mil DIP". 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. Vol. XXX. pp. 282–283. doi:10.1109/ISSCC.1987.1157106. S2CID 60783996. /wiki/Doi_(identifier)

  48. Gealow, Jeffrey Carl (10 August 1990). "Impact of Processing Technology on DRAM Sense Amplifier Design" (PDF). Massachusetts Institute of Technology. pp. 149–166. Retrieved 25 June 2019 – via CORE. https://core.ac.uk/download/pdf/4426308.pdf

  49. Mano, Tsuneo; Yamada, J.; Inoue, Junichi; Nakajima, S.; Matsumura, Toshiro; Minegishi, K.; Miura, K.; Matsuda, T.; Hashimoto, C.; Namatsu, H. (1987). "Circuit technologies for 16Mb DRAMs". 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. Vol. XXX. pp. 22–23. doi:10.1109/ISSCC.1987.1157158. S2CID 60984466. /wiki/Doi_(identifier)

  50. Hanafi, Hussein I.; Dennard, Robert H.; Taur, Yuan; Haddad, Nadim F.; Sun, J. Y. C.; Rodriguez, M. D. (September 1987). "0.5 μm CMOS Device Design and Characterization". ESSDERC '87: 17th European Solid State Device Research Conference: 91–94. /wiki/Robert_H._Dennard

  51. Kasai, Naoki; Endo, Nobuhiro; Kitajima, Hiroshi (December 1987). "0.25 μm CMOS technology using P+polysilicon gate PMOSFET". 1987 International Electron Devices Meeting. pp. 367–370. doi:10.1109/IEDM.1987.191433. S2CID 9203005. /wiki/Doi_(identifier)

  52. Gealow, Jeffrey Carl (10 August 1990). "Impact of Processing Technology on DRAM Sense Amplifier Design" (PDF). Massachusetts Institute of Technology. pp. 149–166. Retrieved 25 June 2019 – via CORE. https://core.ac.uk/download/pdf/4426308.pdf

  53. Inoue, M.; Kotani, H.; Yamada, T.; Yamauchi, Hiroyuki; Fujiwara, A.; Matsushima, J.; Akamatsu, Hironori; Fukumoto, M.; Kubota, M.; Nakao, I.; Aoi (1988). "A 16mb Dram with an Open Bit-Line Architecture". 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers. pp. 246–. doi:10.1109/ISSCC.1988.663712. S2CID 62034618. /wiki/Doi_(identifier)

  54. Shahidi, Ghavam G.; Davari, Bijan; Taur, Yuan; Warnock, James D.; Wordeman, Matthew R.; McFarland, P. A.; Mader, S. R.; Rodriguez, M. D. (December 1990). "Fabrication of CMOS on ultrathin SOI obtained by epitaxial lateral overgrowth and chemical-mechanical polishing". International Technical Digest on Electron Devices: 587–590. doi:10.1109/IEDM.1990.237130. S2CID 114249312. /wiki/Ghavam_Shahidi

  55. "Memory". STOL (Semiconductor Technology Online). Archived from the original on 2 November 2023. Retrieved 25 June 2019. https://web.archive.org/web/20231102131915/http://maltiel-consulting.com/Semiconductor_technology_memory.html

  56. "0.18-micron Technology". TSMC. Retrieved 30 June 2019. https://www.tsmc.com/english/dedicatedFoundry/technology/0.18um.htm

  57. Wakabayashi, Hitoshi; Yamagami, Shigeharu; Ikezawa, Nobuyuki; Ogura, Atsushi; Narihiro, Mitsuru; Arai, K.; Ochiai, Y.; Takeuchi, K.; Yamamoto, T.; Mogami, T. (December 2003). "Sub-10-nm planar-bulk-CMOS devices using lateral junction control". IEEE International Electron Devices Meeting 2003. pp. 20.7.1–20.7.3. doi:10.1109/IEDM.2003.1269446. ISBN 0-7803-7872-5. S2CID 2100267. 0-7803-7872-5

  58. "NEC test-produces world's smallest transistor". Thefreelibrary.com. Retrieved 7 December 2017. http://www.thefreelibrary.com/NEC+test-produces+world's+smallest+transistor.-a0111295563

  59. Sekigawa, Toshihiro; Hayashi, Yutaka (August 1984). "Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate". Solid-State Electronics. 27 (8): 827–828. Bibcode:1984SSEle..27..827S. doi:10.1016/0038-1101(84)90036-4. ISSN 0038-1101. /wiki/Bibcode_(identifier)

  60. Koike, Hanpei; Nakagawa, Tadashi; Sekigawa, Toshiro; Suzuki, E.; Tsutsumi, Toshiyuki (23 February 2003). "Primary Consideration on Compact Modeling of DG MOSFETs with Four-terminal Operation Mode" (PDF). TechConnect Briefs. 2 (2003): 330–333. S2CID 189033174. Archived from the original (PDF) on 26 September 2019. https://web.archive.org/web/20190926013047/https://pdfs.semanticscholar.org/1a31/399021f62ae3d00dd6dd42d2bc7483598d26.pdf

  61. Davari, Bijan; Chang, Wen-Hsing; Wordeman, Matthew R.; Oh, C. S.; Taur, Yuan; Petrillo, Karen E.; Rodriguez, M. D. (December 1988). "A high performance 0.25 mu m CMOS technology". Technical Digest., International Electron Devices Meeting. pp. 56–59. doi:10.1109/IEDM.1988.32749. S2CID 114078857. /wiki/Bijan_Davari

  62. Davari, Bijan; Wong, C. Y.; Sun, Jack Yuan-Chen; Taur, Yuan (December 1988). "Doping of n/Sup +/ And p/Sup +/ Polysilicon in a dual-gate CMOS process". Technical Digest., International Electron Devices Meeting. pp. 238–241. doi:10.1109/IEDM.1988.32800. S2CID 113918637. /wiki/Bijan_Davari

  63. Masuoka, Fujio; Takato, Hiroshi; Sunouchi, Kazumasa; Okabe, N.; Nitayama, Akihiro; Hieda, K.; Horiguchi, Fumio (December 1988). "High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs". Technical Digest., International Electron Devices Meeting. pp. 222–225. doi:10.1109/IEDM.1988.32796. S2CID 114148274. /wiki/Fujio_Masuoka

  64. Brozek, Tomasz (2017). Micro- and Nanoelectronics: Emerging Device Challenges and Solutions. CRC Press. p. 117. ISBN 9781351831345. 9781351831345

  65. Ishikawa, Fumitaro; Buyanova, Irina (2017). Novel Compound Semiconductor Nanowires: Materials, Devices, and Applications. CRC Press. p. 457. ISBN 9781315340722. 9781315340722

  66. Colinge, J.P. (2008). FinFETs and Other Multi-Gate Transistors. Springer Science & Business Media. p. 11. ISBN 9780387717517. 9780387717517

  67. Hisamoto, Digh; Kaga, Toru; Kawamoto, Yoshifumi; Takeda, Eiji (December 1989). "A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET". International Technical Digest on Electron Devices Meeting. pp. 833–836. doi:10.1109/IEDM.1989.74182. S2CID 114072236. /wiki/Doi_(identifier)

  68. "IEEE Andrew S. Grove Award Recipients". IEEE Andrew S. Grove Award. Institute of Electrical and Electronics Engineers. Archived from the original on September 9, 2018. Retrieved 4 July 2019. https://web.archive.org/web/20180909112404/https://www.ieee.org/about/awards/bios/grove-recipients.html

  69. Tsu-Jae King, Liu (June 11, 2012). "FinFET: History, Fundamentals and Future". University of California, Berkeley. Symposium on VLSI Technology Short Course. Archived from the original on 28 May 2016. Retrieved 9 July 2019. /wiki/Tsu-Jae_King_Liu

  70. Hisamoto, Digh; Hu, Chenming; Liu, Tsu-Jae King; Bokor, Jeffrey; Lee, Wen-Chin; Kedzierski, Jakub; Anderson, Erik; Takeuchi, Hideki; Asano, Kazuya (December 1998). "A folded-channel MOSFET for deep-sub-tenth micron era". International Electron Devices Meeting 1998. Technical Digest (Cat. No. 98CH36217). pp. 1032–1034. doi:10.1109/IEDM.1998.746531. ISBN 0-7803-4774-9. S2CID 37774589. 0-7803-4774-9

  71. Tsu-Jae King, Liu (June 11, 2012). "FinFET: History, Fundamentals and Future". University of California, Berkeley. Symposium on VLSI Technology Short Course. Archived from the original on 28 May 2016. Retrieved 9 July 2019. /wiki/Tsu-Jae_King_Liu

  72. Hu, Chenming; Choi, Yang-Kyu; Lindert, N.; Xuan, P.; Tang, S.; Ha, D.; Anderson, E.; Bokor, J.; Tsu-Jae King, Liu (December 2001). "Sub-20 nm CMOS FinFET technologies". International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224). pp. 19.1.1–19.1.4. doi:10.1109/IEDM.2001.979526. ISBN 0-7803-7050-3. S2CID 8908553. 0-7803-7050-3

  73. Tsu-Jae King, Liu (June 11, 2012). "FinFET: History, Fundamentals and Future". University of California, Berkeley. Symposium on VLSI Technology Short Course. Archived from the original on 28 May 2016. Retrieved 9 July 2019. /wiki/Tsu-Jae_King_Liu

  74. Ahmed, Shibly; Bell, Scott; Tabery, Cyrus; Bokor, Jeffrey; Kyser, David; Hu, Chenming; Liu, Tsu-Jae King; Yu, Bin; Chang, Leland (December 2002). "FinFET scaling to 10 nm gate length" (PDF). Digest. International Electron Devices Meeting. pp. 251–254. CiteSeerX 10.1.1.136.3757. doi:10.1109/IEDM.2002.1175825. ISBN 0-7803-7462-2. S2CID 7106946. Archived from the original (PDF) on 2020-05-27. Retrieved 2019-10-11. 0-7803-7462-2

  75. Lee, Hyunjin; Choi, Yang-Kyu; Yu, Lee-Eun; Ryu, Seong-Wan; Han, Jin-Woo; Jeon, K.; Jang, D.Y.; Kim, Kuk-Hwan; Lee, Ju-Hyun; et al. (June 2006). "Sub-5nm All-Around Gate FinFET for Ultimate Scaling". 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers. pp. 58–59. doi:10.1109/VLSIT.2006.1705215. hdl:10203/698. ISBN 978-1-4244-0005-8. S2CID 26482358. 978-1-4244-0005-8

  76. "Still Room at the Bottom (nanometer transistor developed by Yang-kyu Choi from the Korea Advanced Institute of Science and Technology )", Nanoparticle News, 1 April 2006, archived from the original on 6 November 2012 https://web.archive.org/web/20121106011401/http://www.highbeam.com/doc/1G1-145838158.html

  77. "Angstrom". Collins English Dictionary. Retrieved 2019-03-02. https://www.collinsdictionary.com/dictionary/english/angstrom

  78. Weimer, Paul K. (June 1962). "The TFT A New Thin-Film Transistor". Proceedings of the IRE. 50 (6): 1462–1469. doi:10.1109/JRPROC.1962.288190. ISSN 0096-8390. S2CID 51650159. /wiki/Paul_K._Weimer

  79. Kuo, Yue (1 January 2013). "Thin Film Transistor Technology—Past, Present, and Future" (PDF). The Electrochemical Society Interface. 22 (1): 55–61. Bibcode:2013ECSIn..22a..55K. doi:10.1149/2.F06131if. ISSN 1064-8208. https://www.electrochem.org/dl/interface/spr/spr13/spr13_p055_061.pdf

  80. Ye, Peide D.; Xuan, Yi; Wu, Yanqing; Xu, Min (2010). "Atomic-Layer Deposited High-k/III-V Metal-Oxide-Semiconductor Devices and Correlated Empirical Model". In Oktyabrsky, Serge; Ye, Peide (eds.). Fundamentals of III-V Semiconductor MOSFETs. Springer Science & Business Media. pp. 173–194. doi:10.1007/978-1-4419-1547-4_7. ISBN 978-1-4419-1547-4. 978-1-4419-1547-4

  81. Brody, T. P.; Kunig, H. E. (October 1966). "A HIGH-GAIN InAs THIN-FILM TRANSISTOR". Applied Physics Letters. 9 (7): 259–260. Bibcode:1966ApPhL...9..259B. doi:10.1063/1.1754740. ISSN 0003-6951. https://doi.org/10.1063%2F1.1754740

  82. Woodall, Jerry M. (2010). Fundamentals of III-V Semiconductor MOSFETs. Springer Science & Business Media. pp. 2–3. ISBN 9781441915474. 9781441915474

  83. Kahng, Dawon; Sze, Simon Min (July–August 1967). "A floating gate and its application to memory devices". The Bell System Technical Journal. 46 (6): 1288–1295. Bibcode:1967ITED...14Q.629K. doi:10.1002/j.1538-7305.1967.tb01738.x. /wiki/Dawon_Kahng

  84. Wegener, H. A. R.; Lincoln, A. J.; Pao, H. C.; O'Connell, M. R.; Oleksiak, R. E.; Lawrence, H. (October 1967). "The variable threshold transistor, a new electrically-alterable, non-destructive read-only storage device". 1967 International Electron Devices Meeting. Vol. 13. p. 70. doi:10.1109/IEDM.1967.187833. /wiki/Doi_(identifier)

  85. Lin, Hung Chang; Iyer, Ramachandra R. (July 1968). "A Monolithic Mos-Bipolar Audio Amplifier". IEEE Transactions on Broadcast and Television Receivers. 14 (2): 80–86. doi:10.1109/TBTR1.1968.4320132. /wiki/Hung-Chang_Lin

  86. Alvarez, Antonio R. (1990). "Introduction to BiCMOS". BiCMOS Technology and Applications. Springer Science & Business Media. pp. 1–20 (2). doi:10.1007/978-1-4757-2029-7_1. ISBN 9780792393849. 9780792393849

  87. Lin, Hung Chang; Iyer, Ramachandra R.; Ho, C. T. (October 1968). "Complementary MOS-bipolar structure". 1968 International Electron Devices Meeting. 1968 International Electron Devices Meeting. pp. 22–24. doi:10.1109/IEDM.1968.187949. /wiki/Hung-Chang_Lin

  88. Alvarez, Antonio R. (1990). "Introduction to BiCMOS". BiCMOS Technology and Applications. Springer Science & Business Media. pp. 1–20 (2). doi:10.1007/978-1-4757-2029-7_1. ISBN 9780792393849. 9780792393849

  89. "Advances in Discrete Semiconductors March On". Power Electronics Technology. Informa: 52–6. September 2005. Archived (PDF) from the original on 22 March 2006. Retrieved 31 July 2019. https://www.powerelectronics.com/content/advances-discrete-semiconductors-march

  90. Oxner, E. S. (1988). Fet Technology and Application. CRC Press. p. 18. ISBN 9780824780500. 9780824780500

  91. Tarui, Y.; Hayashi, Y.; Sekigawa, Toshihiro (September 1969). "Diffusion Selfaligned MOST; A New Approach for High Speed Device". Extended Abstracts of the 1969 Conference on Solid State Devices. doi:10.7567/SSDM.1969.4-1. S2CID 184290914. {{cite book}}: |journal= ignored (help) /wiki/Doi_(identifier)

  92. McLintock, G. A.; Thomas, R. E. (December 1972). "Modelling of the double-diffused MOST's with self-aligned gates". 1972 International Electron Devices Meeting. 1972 International Electron Devices Meeting. pp. 24–26. doi:10.1109/IEDM.1972.249241. /wiki/Doi_(identifier)

  93. Bergveld, P. (January 1970). "Development of an Ion-Sensitive Solid-State Device for Neurophysiological Measurements". IEEE Transactions on Biomedical Engineering. BME-17 (1): 70–71. doi:10.1109/TBME.1970.4502688. PMID 5441220. /wiki/IEEE_Transactions_on_Biomedical_Engineering

  94. Chris Toumazou; Pantelis Georgiou (December 2011). "40 years of ISFET technology: From neuronal sensing to DNA sequencing". Electronics Letters. doi:10.1049/el.2011.3231. Retrieved 13 May 2016. https://www.researchgate.net/publication/260616066

  95. Tarui, Y.; Hayashi, Y.; Sekigawa, Toshihiro (October 1970). DSA enhancement – Depletion MOS IC. 1970 International Electron Devices Meeting. p. 110. doi:10.1109/IEDM.1970.188299. /wiki/Doi_(identifier)

  96. "Advances in Discrete Semiconductors March On". Power Electronics Technology. Informa: 52–6. September 2005. Archived (PDF) from the original on 22 March 2006. Retrieved 31 July 2019. https://www.powerelectronics.com/content/advances-discrete-semiconductors-march

  97. Duncan, Ben (1996). High Performance Audio Power Amplifiers. Elsevier. pp. 177–8, 406. ISBN 9780080508047. 9780080508047

  98. Baliga, B. Jayant (2015). The IGBT Device: Physics, Design and Applications of the Insulated Gate Bipolar Transistor. William Andrew. pp. xxviii, 5–12. ISBN 9781455731534. 9781455731534

  99. Higuchi, H.; Kitsukawa, Goro; Ikeda, Takahide; Nishio, Y.; Sasaki, N.; Ogiue, Katsumi (December 1984). "Performance and structures of scaled-down bipolar devices merged with CMOSFETs". 1984 International Electron Devices Meeting. pp. 694–697. doi:10.1109/IEDM.1984.190818. S2CID 41295752. /wiki/Doi_(identifier)

  100. Deguchi, K.; Komatsu, Kazuhiko; Miyake, M.; Namatsu, H.; Sekimoto, M.; Hirata, K. (1985). "Step-and-Repeat X-ray/Photo Hybrid Lithography for 0.3 μm Mos Devices". 1985 Symposium on VLSI Technology. Digest of Technical Papers: 74–75. https://ieeexplore.ieee.org/document/4480310

  101. Momose, H.; Shibata, Hideki; Saitoh, S.; Miyamoto, Jun-ichi; Kanzaki, K.; Kohyama, Susumu (1985). "1.0-/spl mu/m n-Well CMOS/Bipolar Technology". IEEE Journal of Solid-State Circuits. 20 (1): 137–143. Bibcode:1985IJSSC..20..137M. doi:10.1109/JSSC.1985.1052286. S2CID 37353920. /wiki/IEEE_Journal_of_Solid-State_Circuits

  102. Lee, Han-Sheng; Puzio, L.C. (November 1986). "The electrical properties of subquarter-micrometer gate-length MOSFET's". IEEE Electron Device Letters. 7 (11): 612–614. Bibcode:1986IEDL....7..612H. doi:10.1109/EDL.1986.26492. S2CID 35142126. /wiki/IEEE_Electron_Device_Letters

  103. Shahidi, Ghavam G.; Antoniadis, Dimitri A.; Smith, Henry I. (December 1986). "Electron velocity overshoot at 300 K and 77 K in silicon MOSFETs with submicron channel lengths". 1986 International Electron Devices Meeting. pp. 824–825. doi:10.1109/IEDM.1986.191325. S2CID 27558025. /wiki/Ghavam_Shahidi

  104. Chou, Stephen Y.; Smith, Henry I.; Antoniadis, Dimitri A. (January 1986). "Sub-100-nm channel-length transistors fabricated using x-ray lithography". Journal of Vacuum Science & Technology B: Microelectronics Processing and Phenomena. 4 (1): 253–255. Bibcode:1986JVSTB...4..253C. doi:10.1116/1.583451. ISSN 0734-211X. /wiki/Bibcode_(identifier)

  105. Davari, Bijan; Ting, Chung-Yu; Ahn, Kie Y.; Basavaiah, S.; Hu, Chao-Kun; Taur, Yuan; Wordeman, Matthew R.; Aboelfotoh, O. (May 1987). "Submicron Tungsten Gate MOSFET with 10 nm Gate Oxide". 1987 Symposium on VLSI Technology. Digest of Technical Papers: 61–62. /wiki/Bijan_Davari

  106. Havemann, Robert H.; Eklund, R. E.; Tran, Hiep V.; Haken, R. A.; Scott, D. B.; Fung, P. K.; Ham, T. E.; Favreau, D. P.; Virkus, R. L. (December 1987). "An 0.8 μm 256K BiCMOS SRAM technology". 1987 International Electron Devices Meeting. pp. 841–843. doi:10.1109/IEDM.1987.191564. S2CID 40375699. /wiki/Doi_(identifier)

  107. Kawaura, Hisao; Sakamoto, Toshitsugu; Baba, Toshio; Ochiai, Yukinori; Fujita, Jun-ichi; Matsui, Shinji; Sone, J. (1997). "Transistor operations in 30-nm-gate-length EJ-MOSFETs". 1997 55th Annual Device Research Conference Digest. pp. 14–15. doi:10.1109/DRC.1997.612456. ISBN 0-7803-3911-8. S2CID 38105606. 0-7803-3911-8

  108. Schwierz, Frank; Wong, Hei; Liou, Juin J. (2010). Nanometer CMOS. Pan Stanford Publishing. p. 17. ISBN 9789814241083. 9789814241083

  109. Kawaura, Hisao; Sakamoto, Toshitsugu; Baba, Toshio (12 June 2000). "Observation of source-to-drain direct tunneling current in 8 nm gate electrically variable shallow junction metal–oxide–semiconductor field-effect transistors". Applied Physics Letters. 76 (25): 3810–3812. Bibcode:2000ApPhL..76.3810K. doi:10.1063/1.126789. ISSN 0003-6951. /wiki/Applied_Physics_Letters

  110. Lojek, Bo (2007). History of Semiconductor Engineering. Springer Science & Business Media. p. 330. ISBN 9783540342588. 9783540342588

  111. Lojek, Bo (2007). History of Semiconductor Engineering. Springer Science & Business Media. pp. 362–363. ISBN 9783540342588. The i1103 was manufactured on a 6-mask silicon-gate P-MOS process with 8 μm minimum features. The resulting product had a 2,400 μm, 2 memory cell size, a die size just under 10 mm2, and sold for around $21. 9783540342588

  112. Belzer, Jack; Holzman, Albert G.; Kent, Allen (1978). Encyclopedia of Computer Science and Technology: Volume 10 – Linear and Matrix Algebra to Microorganisms: Computer-Assisted Identification. CRC Press. p. 402. ISBN 9780824722609.Corder, Mike (Spring 1999). "Big Things in Small Packages". Pioneers' Progress with picoJava Technology. Sun Microelectronics. Archived from the original on 2006-03-12. Retrieved April 23, 2012. The first 6502 was fabricated with 8 micron technology, ran at one megahertz and had a maximum memory of 64k. 9780824722609

  113. "1973: 12-bit engine-control microprocessor (Toshiba)" (PDF). Semiconductor History Museum of Japan. Retrieved 27 June 2019. http://www.shmj.or.jp/english/pdf/ic/exhibi739E.pdf

  114. Kubo, Masaharu; Hori, Ryoichi; Minato, Osamu; Sato, Kikuji (February 1976). "A threshold voltage controlling circuit for short channel MOS integrated circuits". 1976 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. 1976 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. Vol. XIX. pp. 54–55. doi:10.1109/ISSCC.1976.1155515. S2CID 21048622."History of the Intel Microprocessor - Listoid". Archived from the original on 2015-04-27. Retrieved 2019-07-02. /wiki/Doi_(identifier)

  115. "Intel Microprocessor Quick Reference Guide". Intel. Retrieved 27 June 2019."Design case history: the Commodore 64" (PDF). IEEE Spectrum. Archived from the original (PDF) on May 13, 2012. Retrieved 1 September 2019. https://www.intel.com/pressroom/kits/quickrefyr.htm

  116. "Intel Microprocessor Quick Reference Guide". Intel. Retrieved 27 June 2019."Design case history: the Commodore 64" (PDF). IEEE Spectrum. Archived from the original (PDF) on May 13, 2012. Retrieved 1 September 2019. https://www.intel.com/pressroom/kits/quickrefyr.htm

  117. "Intel Microprocessor Quick Reference Guide". Intel. Retrieved 27 June 2019."Design case history: the Commodore 64" (PDF). IEEE Spectrum. Archived from the original (PDF) on May 13, 2012. Retrieved 1 September 2019. https://www.intel.com/pressroom/kits/quickrefyr.htm

  118. Mueller, S (2006-07-21). "Microprocessors from 1971 to the Present". informIT. Retrieved 2012-05-11. http://www.informit.com/articles/article.aspx?p=482324&seqNum=2

  119. Kubo, Masaharu; Hori, Ryoichi; Minato, Osamu; Sato, Kikuji (February 1976). "A threshold voltage controlling circuit for short channel MOS integrated circuits". 1976 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. 1976 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. Vol. XIX. pp. 54–55. doi:10.1109/ISSCC.1976.1155515. S2CID 21048622."History of the Intel Microprocessor - Listoid". Archived from the original on 2015-04-27. Retrieved 2019-07-02. /wiki/Doi_(identifier)

  120. "Memory". STOL (Semiconductor Technology Online). Archived from the original on 2 November 2023. Retrieved 25 June 2019. https://web.archive.org/web/20231102131915/http://maltiel-consulting.com/Semiconductor_technology_memory.html

  121. "Amiga Manual: Amiga 3000+ System Specification 1991". 17 July 1991. https://archive.org/stream/Amiga_3000_System_Specification_The_1991-07-17_Commodore/Amiga_3000_System_Specification_The_1991-07-17_Commodore_djvu.txt

  122. Gealow, Jeffrey Carl (10 August 1990). "Impact of Processing Technology on DRAM Sense Amplifier Design" (PDF). Massachusetts Institute of Technology. pp. 149–166. Retrieved 25 June 2019 – via CORE. https://core.ac.uk/download/pdf/4426308.pdf

  123. "Memory". STOL (Semiconductor Technology Online). Archived from the original on 2 November 2023. Retrieved 25 June 2019. https://web.archive.org/web/20231102131915/http://maltiel-consulting.com/Semiconductor_technology_memory.html

  124. Gealow, Jeffrey Carl (10 August 1990). "Impact of Processing Technology on DRAM Sense Amplifier Design" (PDF). Massachusetts Institute of Technology. pp. 149–166. Retrieved 25 June 2019 – via CORE. https://core.ac.uk/download/pdf/4426308.pdf

  125. "Memory". STOL (Semiconductor Technology Online). Archived from the original on 2 November 2023. Retrieved 25 June 2019. https://web.archive.org/web/20231102131915/http://maltiel-consulting.com/Semiconductor_technology_memory.html

  126. Gealow, Jeffrey Carl (10 August 1990). "Impact of Processing Technology on DRAM Sense Amplifier Design" (PDF). Massachusetts Institute of Technology. pp. 149–166. Retrieved 25 June 2019 – via CORE. https://core.ac.uk/download/pdf/4426308.pdf

  127. "Memory". STOL (Semiconductor Technology Online). Archived from the original on 2 November 2023. Retrieved 25 June 2019. https://web.archive.org/web/20231102131915/http://maltiel-consulting.com/Semiconductor_technology_memory.html

  128. "Memory". STOL (Semiconductor Technology Online). Archived from the original on 2 November 2023. Retrieved 25 June 2019. https://web.archive.org/web/20231102131915/http://maltiel-consulting.com/Semiconductor_technology_memory.html

  129. "Memory". STOL (Semiconductor Technology Online). Archived from the original on 2 November 2023. Retrieved 25 June 2019. https://web.archive.org/web/20231102131915/http://maltiel-consulting.com/Semiconductor_technology_memory.html

  130. "Memory". STOL (Semiconductor Technology Online). Archived from the original on 2 November 2023. Retrieved 25 June 2019. https://web.archive.org/web/20231102131915/http://maltiel-consulting.com/Semiconductor_technology_memory.html

  131. "Memory". STOL (Semiconductor Technology Online). Archived from the original on 2 November 2023. Retrieved 25 June 2019. https://web.archive.org/web/20231102131915/http://maltiel-consulting.com/Semiconductor_technology_memory.html

  132. "Memory". STOL (Semiconductor Technology Online). Archived from the original on 2 November 2023. Retrieved 25 June 2019. https://web.archive.org/web/20231102131915/http://maltiel-consulting.com/Semiconductor_technology_memory.html

  133. "Propeller I semiconductor process technology? Is it 350nm or 180nm?". Archived from the original on 2012-07-10. Retrieved 2012-09-10. https://archive.today/20120710222806/http://forums.parallax.com/showthread.php?130327-Propeller-I-semiconductor-process-technology-Is-it-350nm-or-180nm

  134. "Memory". STOL (Semiconductor Technology Online). Archived from the original on 2 November 2023. Retrieved 25 June 2019. https://web.archive.org/web/20231102131915/http://maltiel-consulting.com/Semiconductor_technology_memory.html

  135. "Memory". STOL (Semiconductor Technology Online). Archived from the original on 2 November 2023. Retrieved 25 June 2019. https://web.archive.org/web/20231102131915/http://maltiel-consulting.com/Semiconductor_technology_memory.html

  136. "Memory". STOL (Semiconductor Technology Online). Archived from the original on 2 November 2023. Retrieved 25 June 2019. https://web.archive.org/web/20231102131915/http://maltiel-consulting.com/Semiconductor_technology_memory.html

  137. "Memory". STOL (Semiconductor Technology Online). Archived from the original on 2 November 2023. Retrieved 25 June 2019. https://web.archive.org/web/20231102131915/http://maltiel-consulting.com/Semiconductor_technology_memory.html

  138. Hunter, William R.; Ephrath, L. M.; Cramer, Alice; Grobman, W. D.; Osburn, C. M.; Crowder, B. L.; Luhn, H. E. (April 1979). "1 /spl mu/m MOSFET VLSI technology. V. A single-level polysilicon technology using electron-beam lithography". IEEE Journal of Solid-State Circuits. 14 (2): 275–281. doi:10.1109/JSSC.1979.1051174. S2CID 26389509."Emotion Engine and Graphics Synthesizer Used in the Core of PlayStation Become One Chip" (PDF) (Press release). Sony. 21 April 2003. Retrieved 26 June 2019. /wiki/IEEE_Journal_of_Solid-State_Circuits

  139. Krewell, Kevin (21 October 2002). "Fujitsu's SPARC64 V Is Real Deal". Microprocessor Report. http://www.eecg.toronto.edu/~moshovos/ACA07/lecturenotes/ultrasparc5%2520(mpr).pdf

  140. Hunter, William R.; Ephrath, L. M.; Cramer, Alice; Grobman, W. D.; Osburn, C. M.; Crowder, B. L.; Luhn, H. E. (April 1979). "1 /spl mu/m MOSFET VLSI technology. V. A single-level polysilicon technology using electron-beam lithography". IEEE Journal of Solid-State Circuits. 14 (2): 275–281. doi:10.1109/JSSC.1979.1051174. S2CID 26389509."Emotion Engine and Graphics Synthesizer Used in the Core of PlayStation Become One Chip" (PDF) (Press release). Sony. 21 April 2003. Retrieved 26 June 2019. /wiki/IEEE_Journal_of_Solid-State_Circuits

  141. "ソニー、65nm対応の半導体設備を導入。3年間で2,000億円の投資". pc.watch.impress.co.jp. Archived from the original on 2016-08-13. https://pc.watch.impress.co.jp/docs/2003/0421/sony1.htm

  142. TG Daily – AMD preps 65 nm Turion X2 processors Archived 2007-09-13 at the Wayback Machine http://www.tgdaily.com/content/view/31877/135/

  143. http://focus.ti.com/pdfs/wtbu/ti_omap3family.pdf [bare URL PDF] http://focus.ti.com/pdfs/wtbu/ti_omap3family.pdf

  144. "Panasonic starts to sell a New-generation UniPhier System LSI". Panasonic. October 10, 2007. Retrieved 2 July 2019. http://panasonic.co.jp/corp/news/official.data/data.dir/en071010-3/en071010-3.html

  145. Kobayashi, Toshio; Horiguchi, Seiji; Kiuchi, K. (December 1984). "Deep-submicron MOSFET characteristics with 5 nm gate oxide". 1984 International Electron Devices Meeting. pp. 414–417. doi:10.1109/IEDM.1984.190738. S2CID 46729489."Toshiba Makes Major Advances in NAND Flash Memory with 3-bit-per-cell 32nm generation and with 4-bit-per-cell 43nm technology". Toshiba. 11 February 2009. Retrieved 21 June 2019. /wiki/Doi_(identifier)

  146. "Intel Debuts 32-NM Westmere Desktop Processors". InformationWeek, 7 January 2010. Retrieved 2011-12-17. http://www.informationweek.com/news/security/management/showArticle.jhtml?articleID=222200708

  147. Cangeloso, Sal (February 4, 2010). "Intel's 6-core 32nm processors arriving soon". Geek.com. Archived from the original on March 30, 2012. Retrieved November 11, 2011. https://web.archive.org/web/20120330104041/http://www.geek.com/articles/chips/intels-6-core-32nm-processors-arriving-soon-2010024/

  148. "Ambarella A7L Enables the Next Generation of Digital Still Cameras with 1080p60 Fluid Motion Video". News release. September 26, 2011. Archived from the original on November 10, 2011. Retrieved November 11, 2011. https://web.archive.org/web/20111110054035/http://www.ambarella.com/news/26/74/Ambarella-A7L-Enables-the-Next-Generation-of-Digital-Still-Cameras-with-1080p60-Fluid-Motion-Video.html

  149. Article reporting Hynix 26 nm technology announcement http://www.eetimes.com/electronics-news/4087542/Hynix-Samsung-push-NAND-flash-below-30-nm

  150. Toshiba launches 24nm process NAND flash memory http://www.toshiba.co.jp/about/press/2010_08/pr3101.htm?from=RSS_PRESS&uid=20100831-1112e

  151. "The Russian 28-nm processor "Elbrus-8C" will go into production in 2016". Retrieved 7 September 2020. https://www.cnews.ru/news/top/rossijskij_28nm_protsessor_elbrus8s

  152. "Another domestic data storage system on "Elbrus" has been created". 25 August 2020. Retrieved 7 September 2020. https://rossaprimavera.ru/news/d7e86147

  153. Intel launches Ivy Bridge... http://semiaccurate.com/2012/04/23/intel-launches-ivy-bridge-amid-crushing-marketing-buzzwords/

  154. "History". Samsung Electronics. Samsung. Retrieved 19 June 2019. https://www.samsung.com/us/aboutsamsung/company/history/

  155. Chou, Stephen Y.; Antoniadis, Dimitri A.; Smith, Henry I. (December 1985). "Observation of electron velocity overshoot in sub-100-nm-channel MOSFET's in Silicon". IEEE Electron Device Letters. 6 (12): 665–667. Bibcode:1985IEDL....6..665C. doi:10.1109/EDL.1985.26267. S2CID 28493431."16/12nm Technology". TSMC. Retrieved 30 June 2019. /wiki/IEEE_Electron_Device_Letters

  156. EETimes Intel Rolls 14nm Broadwell in Vegas http://www.eetimes.com/document.asp?doc_id=1325057

  157. "AMD Zen Architecture Overview". Tech4Gizmos. 2015-12-04. Retrieved 2019-05-01. http://tech4gizmos.com/amd-zen-architecture/

  158. "Samsung Mass Producing 128Gb 3-bit MLC NAND Flash". Tom's Hardware. 11 April 2013. Archived from the original on 21 June 2019. Retrieved 21 June 2019. https://web.archive.org/web/20190621175628/https://www.tomshardware.co.uk/NAND-128Gb-Mass-Production-3-bit-MLC,news-43458.html

  159. Samsung Starts Industry's First Mass Production of System-on-Chip with 10-Nanometer FinFET Technology, Oct 2016 https://news.samsung.com/global/samsung-starts-industrys-first-mass-production-of-system-on-chip-with-10-nanometer-finfet-technology

  160. "10nm Technology". TSMC. Retrieved 30 June 2019. https://www.tsmc.com/english/dedicatedFoundry/technology/10nm.htm

  161. "Latest Samsung Galaxy Smartphones | Mobile Phones". http://www.samsung.com/us/explore/galaxy-s8/buy/

  162. techinsights.com. "10nm Rollout Marching Right Along". www.techinsights.com. Archived from the original on 2017-08-03. Retrieved 2017-06-30. https://web.archive.org/web/20170803141307/http://www.techinsights.com/about-techinsights/overview/blog/10nm-rollout-marching-right-along/

  163. "7nm Technology". TSMC. Retrieved 30 June 2019. https://www.tsmc.com/english/dedicatedFoundry/technology/7nm.htm

  164. TSMC ramping up 7nm chip production Monica Chen, Hsinchu; Jessie Shen, DIGITIMES Friday 22 June 2018 https://www.digitimes.com/news/a20180622PD204.html

  165. "Apple's A12 Bionic is the first 7-nanometer smartphone chip". Engadget. Retrieved 2018-09-20. https://www.engadget.com/2018/09/12/apple-a12-bionic-7-nanometer-chip/

  166. Smith, Ryan. "AMD Announces Radeon Instinct MI60 & MI50 Accelerators: Powered By 7nm Vega". www.anandtech.com. Retrieved 2021-01-09. https://www.anandtech.com/show/13562/amd-announces-radeon-instinct-mi60-mi50-accelerators-powered-by-7nm-vega

  167. Cutress, Ian. "AMD Ryzen 3000 Announced: Five CPUs, 12 Cores for $499, Up to 4.6 GHz, PCIe 4.0, Coming 7/7". www.anandtech.com. Retrieved 2021-01-09. https://www.anandtech.com/show/14407/amd-ryzen-3000-announced-five-cpus-12-cores-for-499-up-to-46-ghz-pcie-40-coming-77

  168. Smith, Ryan. "Sony Teases Next-Gen PlayStation: Custom AMD Chip with Zen 2 CPU & Navi GPU, SSD Too". www.anandtech.com. Retrieved 2021-01-09. https://www.anandtech.com/show/14224/sony-teases-nextgen-playstation-custom-amd-chip-with-zen-2-cpu-navi-gpu-ssd-too

  169. Howse, Brett. "Xbox at E3 2019: Xbox Project Scarlett Console Launching Holiday 2020". www.anandtech.com. Retrieved 2021-01-09. https://www.anandtech.com/show/14519/xbox-at-e3-xbox-project-scarlet-console-launching-holiday-2020

  170. Shilov, Anton. "Samsung Completes Development of 5nm EUV Process Technology". www.anandtech.com. Retrieved 2019-05-31. https://www.anandtech.com/show/14231/samsung-completes-development-of-5-nm-euv-process-technology

  171. TSMC and OIP Ecosystem Partners Deliver Industry's First Complete Design Infrastructure for 5nm Process Technology (press release), TSMC, 3 April 2019 https://www.tsmc.com/tsmcdotcom/PRListingNewsAction.do?action=detail&language=E&newsid=THPGWQTHTH

  172. "TSMC Plans New Fab for 3nm". EE Times. 12 December 2016. Retrieved 26 September 2019. https://www.eetimes.com/document.asp?doc_id=1330971

  173. Armasu, Lucian (11 January 2019), "Samsung Plans Mass Production of 3nm GAAFET Chips in 2021", Tom's Hardware https://www.tomshardware.com/news/samsung-3nm-gaafet-production-2021,38426.html

  174. Smith, Ryan. "Samsung Starts 3nm Production: The Gate-All-Around (GAAFET) Era Begins". www.anandtech.com. Retrieved 2022-11-08. https://www.anandtech.com/show/17474/samsung-starts-3nm-production-the-gaafet-era-begins