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AMD Eyefinity
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<h2 id="overview">Overview</h2> <p>AMD Eyefinity is implemented by multiple on-<a href="/facts/Die_(integrated_circuit)/XWvdlltE">die</a> <a href="/facts/Display_controller/ISm9E6Nc">display controllers</a>. The HD 5000-series designs host two internal clocks and one external clock. Displays connected over <a href="/facts/VGA_connector/FI7TpsL6">VGA</a>, <a href="/facts/Digital_Visual_Interface/Dpnu9JmB">DVI</a>, or <a href="/facts/High-Definition_Multimedia_Interface/HuNwzm04">HDMI</a> each require their own internal clock. But all displays connected over <a href="/facts/DisplayPort/rJSvGhBN">DisplayPort</a> can be driven from only one external clock. This external clock is what allows Eyefinity to fuel up to six monitors from a single card. </p><p>The entire HD 5000 series of products have Eyefinity capabilities supporting three outputs. The <i>Radeon HD 5870 Eyefinity Edition</i>, however, supports six <a href="/facts/Mini_DisplayPort/6xH3MDvx">mini DisplayPort</a> outputs, all of which can be simultaneously active.<a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a> </p><p>The display controller has two <a href="/facts/RAMDAC/P82pNINa">RAMDACs</a> that drive the <a href="/facts/Video_Graphics_Array/8GGsGTSc">VGA</a> or <a href="/facts/Digital_Visual_Interface/Dpnu9JmB">DVI</a> ports in analog mode. For example, when a DVI-to-VGA converter is attached to a DVI port). It also has a maximum of six digital transmitters that can output either a <a href="/facts/DisplayPort/rJSvGhBN">DisplayPort</a> signal or a <a href="/facts/Transition_Minimized_Differential_Signaling/kRqz8N2I">TMDS</a> signal for either DVI or <a href="/facts/HDMI/HuNwzm04">HDMI</a>, and two <a href="/facts/Clock_signal/9UfTzGHx">clock signal</a> generators to drive the digital outputs in <a href="/facts/Transition-minimized_differential_signaling/kRqz8N2I">TMDS</a> mode. <a href="/facts/Dual-link_DVI/Dpnu9JmB">Dual-link DVI</a> displays use two of the TMDS/DisplayPort transmitters and one clock signal each. Single-link DVI displays and HDMI displays use one TMDS/DisplayPort transmitter and one clock signal each. DisplayPort displays use one TMDS/DisplayPort transmitter and no clock signal. </p><p>An active DisplayPort adapter can convert a DisplayPort signal to another type of signal—like VGA, single-link DVI, or dual-link DVI; or HDMI if more than two non-DisplayPort displays must be connected to a Radeon HD 5000 series graphics card.<a class="footnote-ref" id="fnref:8" href="#fn:8"><sup>8</sup></a> </p><p>DisplayPort 1.2 added the possibility to drive multiple displays on single DisplayPort connector, called <a href="/facts/Multi-Stream_Transport/rJSvGhBN">Multi-Stream Transport</a> (MST). AMD graphics solutions equipped with DisplayPort 1.2 outputs can run multiple monitors from a single port. </p><p>At High-Performance Graphics 2010 Mark Fowler presented the Evergreen and stated that e.g. 5870 (Cypress), 5770 (Juniper) and 5670 (Redwood) support max resolution of the 6 times 2560×1600 pixels, while the 5470 (Cedar) supports 4 times 2560×1600 pixels.<a class="footnote-ref" id="fnref:9" href="#fn:9"><sup>9</sup></a> </p> <h2 id="availability">Availability</h2> <h3>Feature overview for AMD graphics cards</h3> <p class="note">Main article: <a href="/facts/List_of_AMD_graphics_processing_units/jaVxfufu">List of Radeon graphics cards</a></p> <p>All AMD GPUs starting with the Evergreen series support a maximum of 2 <i>non</i>-<a href="/facts/DisplayPort/rJSvGhBN">DisplayPort</a> displays and a maximum of 6 DisplayPort displays per graphics card.<a class="footnote-ref" id="fnref:10" href="#fn:10"><sup>10</sup></a> </p><p>The following table shows features of <a href="/facts/Advanced_Micro_Devices/CB1G7QTb">AMD</a>/<a href="/facts/ATI_Technologies/7hPl9Cqx">ATI</a>'s <a href="/facts/Graphics_processing_unit/PTK1RQVp">GPUs</a> (see also: <a href="/facts/List_of_AMD_graphics_processing_units/jaVxfufu">List of AMD graphics processing units</a>). </p> [ <a href="https://en.wikipedia.org/w/index.php?title=Template:AMD_GPU_features&veaction=edit">VisualEditor</a> ] <ul><li>view</li><li>talk</li><li>edit</li></ul> <table><tbody><tr><th>Name of <a href="/facts/Graphics_processing_unit/PTK1RQVp">GPU</a> series</th><th><a href="/facts/List_of_AMD_graphics_processing_units/jaVxfufu">Wonder</a></th><th><a href="/facts/List_of_AMD_graphics_processing_units/jaVxfufu">Mach</a></th><th><a href="/facts/List_of_AMD_graphics_processing_units/jaVxfufu">3D Rage</a></th><th><a href="/facts/List_of_AMD_graphics_processing_units/jaVxfufu">Rage Pro</a></th><th><a href="/facts/List_of_AMD_graphics_processing_units/jaVxfufu">Rage 128</a></th><th><a href="/facts/Radeon_R100_series/Qgqk8EFj">R100</a></th><th><a href="/facts/Radeon_R200_series/pAA96fYU">R200</a></th><th><a href="/facts/Radeon_R300_series/XlbYkgGA">R300</a></th><th><a href="/facts/Radeon_R400_series/gT3bKhe5">R400</a></th><th><a href="/facts/Radeon_X1000_series/x8PysrFS">R500</a></th><th><a href="/facts/Radeon_HD_2000_series/QwlY2oKq">R600</a></th><th><a href="/facts/Radeon_HD_3000_series/mjnLsqHh">RV670</a></th><th><a href="/facts/Radeon_HD_4000_series/kWppqQVY">R700</a></th><th><a href="/facts/Radeon_HD_5000_series/RvyDSDdz">Evergreen</a></th><th colspan="2"><a href="/facts/Radeon_HD_6000_series/oFFj55YU">NorthernIslands</a></th><th><a href="/facts/Radeon_HD_7000_series/2jTX6dtY">SouthernIslands</a></th><th><a href="/facts/Radeon_200_series/9KsuUb43">SeaIslands</a></th><th><a href="/facts/Radeon_300_series/k8rYwyzT">VolcanicIslands</a></th><th><a href="/facts/Radeon_400_series/mxk11VqW">ArcticIslands</a>/<a href="/facts/Radeon_500_series/1XgrvSjM">Polaris</a></th><th><a href="/facts/Radeon_RX_Vega_series/j13wIHR5">Vega</a></th><th><a href="/facts/Radeon_RX_5000_series/pTtU0PYl">Navi 1x</a></th><th><a href="/facts/Radeon_RX_6000_series/G6Enmfs3">Navi 2x</a></th><th><a href="/facts/Radeon_RX_7000_series/MF4QXbUv">Navi 3x</a></th><th><a href="/facts/Radeon_RX_9000_series/25YlbYY4">Navi 4x</a></th></tr><tr><th>Released</th><td>1986</td><td>1991</td><td>Apr1996</td><td>Mar1997</td><td>Aug1998</td><td>Apr2000</td><td>Aug2001</td><td>Sep2002</td><td>May2004</td><td>Oct2005</td><td>May2007</td><td>Nov2007</td><td>Jun2008</td><td>Sep2009</td><td>Oct2010</td><td>Dec2010</td><td>Jan2012</td><td>Sep2013</td><td>Jun2015</td><td>Jun 2016, Apr 2017, Aug 2019</td><td>Jun 2017, Feb 2019</td><td>Jul2019</td><td>Nov2020</td><td>Dec2022</td><td>Feb2025</td></tr><tr><th><a href="/facts/List_of_AMD_graphics_processing_units/jaVxfufu">Marketing Name</a></th><td>Wonder</td><td>Mach</td><td>3DRage</td><td>RagePro</td><td>Rage128</td><td>Radeon7000</td><td>Radeon8000</td><td>Radeon9000</td><td>RadeonX700/X800</td><td>RadeonX1000</td><td>RadeonHD 2000</td><td>RadeonHD 3000</td><td>RadeonHD 4000</td><td>RadeonHD 5000</td><td colspan="2">RadeonHD 6000</td><td>RadeonHD 7000</td><td>Radeon200</td><td>Radeon300</td><td>Radeon400/500/600</td><td>RadeonRX Vega, Radeon VII</td><td>RadeonRX 5000</td><td>RadeonRX 6000</td><td>RadeonRX 7000</td><td>RadeonRX 9000</td></tr><tr><th>AMD support</th><td colspan="19"></td><td colspan="8"></td></tr><tr><th>Kind</th><td colspan="2">2D</td><td colspan="23">3D</td></tr><tr><th><a href="/facts/Instruction_set_architecture/8p8vwUeE">Instruction set architecture</a></th><td colspan="10">Not publicly known</td><td colspan="6"><a href="/facts/TeraScale_(microarchitecture)/Yt6jwq9b">TeraScale</a> instruction set</td><td colspan="5"><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN instruction set</a></td><td colspan="4"><a href="/facts/RDNA_(microarchitecture)/tplgu8A1">RDNA instruction set</a></td></tr><tr><th><a href="/facts/Microarchitecture/NFRd4NUL">Microarchitecture</a></th><td colspan="5">Not publicly known</td><td colspan="2">GFX1</td><td colspan="3">GFX2</td><td colspan="3"><a href="/facts/TeraScale_(microarchitecture)/Yt6jwq9b">TeraScale 1(VLIW5)</a>(GFX3)</td><td><a href="/facts/TeraScale_(microarchitecture)/Yt6jwq9b">TeraScale 2(VLIW5)</a>(GFX4)</td><td><a href="/facts/TeraScale_(microarchitecture)/Yt6jwq9b">TeraScale 2(VLIW5)</a> up to 68xx(GFX4)</td><td><a href="/facts/TeraScale_(microarchitecture)/Yt6jwq9b">TeraScale 3(VLIW4)</a> in 69xx <a class="footnote-ref" id="fnref:11" href="#fn:11"><sup>11</sup></a><a class="footnote-ref" id="fnref:12" href="#fn:12"><sup>12</sup></a>(GFX5)</td><td><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN 1stgen</a>(GFX6)</td><td><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN 2ndgen</a>(GFX7)</td><td><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN 3rdgen</a>(GFX8)</td><td><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN 4thgen</a>(GFX8)</td><td><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN 5thgen</a>(GFX9)</td><td><a href="/facts/RDNA_(microarchitecture)/tplgu8A1">RDNA</a>(GFX10.1)</td><td><a href="/facts/RDNA_2/tplgu8A1">RDNA 2</a>(GFX10.3)</td><td><a href="/facts/RDNA_3/tCrEHPQu">RDNA 3</a>(GFX11)</td><td><a href="/facts/RDNA_4/sm5tywSH">RDNA 4</a>(GFX12)</td></tr><tr><th>Type</th><td colspan="6">Fixed pipeline<a class="footnote-ref" id="fnref:13" href="#fn:13"><sup>13</sup></a></td><td colspan="4">Programmable pixel & vertex pipelines</td><td colspan="15"><a href="/facts/Unified_shader_model/f436C5Vw">Unified shader model</a></td></tr><tr><th><a href="/facts/Direct3D/WHJ6DTcv">Direct3D</a></th><td colspan="2">—</td><td>5.0</td><td colspan="2">6.0</td><td>7.0</td><td>8.1</td><td>9.011 (<a href="/facts/Feature_levels_in_Direct3D/MUsSPfsz">9_2</a>)</td><td>9.0b11 (<a href="/facts/Feature_levels_in_Direct3D/MUsSPfsz">9_2</a>)</td><td>9.0c11 (<a href="/facts/Feature_levels_in_Direct3D/MUsSPfsz">9_3</a>)</td><td>10.011 (<a href="/facts/Feature_levels_in_Direct3D/MUsSPfsz">10_0</a>)</td><td colspan="2">10.111 (<a href="/facts/Feature_levels_in_Direct3D/MUsSPfsz">10_1</a>)</td><td colspan="3">11 (<a href="/facts/Feature_levels_in_Direct3D/MUsSPfsz">11_0</a>)</td><td>11 (<a href="/facts/Feature_levels_in_Direct3D/MUsSPfsz">11_1</a>)12 (<a href="/facts/Feature_levels_in_Direct3D/MUsSPfsz">11_1</a>)</td><td colspan="3">11 (<a href="/facts/Feature_levels_in_Direct3D/MUsSPfsz">12_0</a>)12 (<a href="/facts/Feature_levels_in_Direct3D/MUsSPfsz">12_0</a>)</td><td colspan="2">11 (<a href="/facts/Feature_levels_in_Direct3D/MUsSPfsz">12_1</a>)12 (<a href="/facts/Feature_levels_in_Direct3D/MUsSPfsz">12_1</a>)</td><td colspan="3">11 (<a href="/facts/Feature_levels_in_Direct3D/MUsSPfsz">12_1</a>)12 (<a href="/facts/Feature_levels_in_Direct3D/MUsSPfsz">12_2</a>)</td></tr><tr><th><a href="/facts/High-Level_Shader_Language/UdEsuct2">Shader model</a></th><td colspan="6">—</td><td>1.4</td><td>2.0+</td><td>2.0b</td><td>3.0</td><td>4.0</td><td colspan="2">4.1</td><td colspan="3">5.0</td><td>5.1</td><td colspan="3">5.16.5</td><td colspan="4">6.7</td><td>6.8</td></tr><tr><th><a href="/facts/OpenGL/xQoMWePr">OpenGL</a></th><td colspan="3">—</td><td>1.1</td><td>1.2</td><td colspan="2">1.3</td><td colspan="3">2.1<a class="footnote-ref" id="fnref:14" href="#fn:14"><sup>14</sup></a><a class="footnote-ref" id="fnref:15" href="#fn:15"><sup>15</sup></a></td><td colspan="3">3.3</td><td colspan="3">4.5<a class="footnote-ref" id="fnref:16" href="#fn:16"><sup>16</sup></a><a class="footnote-ref" id="fnref:17" href="#fn:17"><sup>17</sup></a><a class="footnote-ref" id="fnref:18" href="#fn:18"><sup>18</sup></a><a class="footnote-ref" id="fnref:19" href="#fn:19"><sup>19</sup></a></td><td colspan="9">4.6</td></tr><tr><th><a href="/facts/Vulkan/e188Vdpc">Vulkan</a></th><td colspan="15">—</td><td>1.1<a class="footnote-ref" id="fnref:20" href="#fn:20"><sup>20</sup></a><a class="footnote-ref" id="fnref:21" href="#fn:21"><sup>21</sup></a></td><td colspan="2">1.3<a class="footnote-ref" id="fnref:22" href="#fn:22"><sup>22</sup></a></td><td colspan="7">1.4<a class="footnote-ref" id="fnref:23" href="#fn:23"><sup>23</sup></a></td></tr><tr><th><a href="/facts/OpenCL/ns8y6np7">OpenCL</a></th><td colspan="10">—</td><td colspan="2"><a href="/facts/Close_to_Metal/csw137dk">Close to Metal</a></td><td>1.1 (not supported by <a href="/facts/Mesa_(computer_graphics)/oxcVI6bd">Mesa</a>)</td><td colspan="4">1.2+ (on <a href="/facts/Linux/9FvCKSTq">Linux</a>: 1.1+ (no Image support on clover, with by rustiCL) with Mesa, 1.2+ on GCN 1.Gen)</td><td colspan="4">2.0+ (Adrenalin driver on <a href="/facts/Windows_7/tldLdbnX">Win7+</a>)(on <a href="/facts/Linux/9FvCKSTq">Linux</a> ROCM, Mesa 1.2+ (no Image support in clover, but in rustiCL with Mesa, 2.0+ and 3.0 with AMD drivers or AMD ROCm), 5th gen: 2.2 win 10+ and Linux RocM 5.0+</td><td colspan="4">2.2+ and 3.0 windows 8.1+ and Linux ROCM 5.0+ (Mesa rustiCL 1.2+ and 3.0 (2.1+ and 2.2+ wip))<a class="footnote-ref" id="fnref:24" href="#fn:24"><sup>24</sup></a><a class="footnote-ref" id="fnref:25" href="#fn:25"><sup>25</sup></a><a class="footnote-ref" id="fnref:26" href="#fn:26"><sup>26</sup></a></td></tr><tr><th><a href="/facts/Heterogeneous_System_Architecture/uwayMPnT">HSA</a> / <a href="/facts/ROCm/MX8uasuY">ROCm</a></th><td colspan="16">—</td><td colspan="5"></td><td colspan="4">?</td></tr><tr><th>Video decoding <a href="/facts/Application-specific_integrated_circuit/YGUXpX50">ASIC</a></th><td colspan="10">—</td><td><a href="/facts/ATI_Avivo/mL6GsCWG">Avivo</a>/<a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD</a></td><td><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD+</a></td><td><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD 2</a></td><td><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD 2.2</a></td><td colspan="2"><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD 3</a></td><td><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD 4</a></td><td><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD 4.2</a></td><td><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD 5.0</a> or <a href="/facts/Unified_Video_Decoder/aQrrwg54">6.0</a></td><td><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD 6.3</a></td><td><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD 7</a> <a class="footnote-ref" id="fnref:27" href="#fn:27"><sup>27</sup></a><a class="footnote-ref" id="fnref:28" href="#fn:28"><sup>28</sup></a></td><td rowspan="2"><a href="/facts/Video_Core_Next/I0GL8eMR">VCN 2.0</a> <a class="footnote-ref" id="fnref:29" href="#fn:29"><sup>29</sup></a><a class="footnote-ref" id="fnref:30" href="#fn:30"><sup>30</sup></a></td><td rowspan="2"><a href="/facts/Video_Core_Next/I0GL8eMR">VCN 3.0</a> <a class="footnote-ref" id="fnref:31" href="#fn:31"><sup>31</sup></a></td><td rowspan="2"><a href="/facts/Video_Core_Next/I0GL8eMR">VCN 4.0</a></td><td rowspan="2"><a href="/facts/Video_Core_Next/I0GL8eMR">VCN 5.0</a></td></tr><tr><th>Video encoding <a href="/facts/Application-specific_integrated_circuit/YGUXpX50">ASIC</a></th><td colspan="16">—</td><td><a href="/facts/Video_Coding_Engine/4L5MLb6K">VCE 1.0</a></td><td><a href="/facts/Video_Coding_Engine/4L5MLb6K">VCE 2.0</a></td><td><a href="/facts/Video_Coding_Engine/4L5MLb6K">VCE 3.0 or 3.1</a></td><td><a href="/facts/Video_Coding_Engine/4L5MLb6K">VCE 3.4</a></td><td><a href="/facts/Video_Coding_Engine/4L5MLb6K">VCE 4.0</a> <a class="footnote-ref" id="fnref:32" href="#fn:32"><sup>32</sup></a><a class="footnote-ref" id="fnref:33" href="#fn:33"><sup>33</sup></a></td></tr><tr><th>Fluid Motion <a class="footnote-ref" id="fnref:34" href="#fn:34"><sup>34</sup></a></th><td colspan="17"></td><td colspan="4"></td><td colspan="2"></td><td colspan="2">?</td></tr><tr><th>Power saving</th><td colspan="10">?</td><td colspan="4"><a href="/facts/AMD_PowerPlay/By12rf5S">PowerPlay</a></td><td colspan='2"'><a href="/facts/AMD_PowerTune/NMNAqExx">PowerTune</a></td><td colspan="5"><a href="/facts/AMD_PowerTune/NMNAqExx">PowerTune</a> & <a href="/facts/Graphics_Core_Next/WYNvhDUP">ZeroCore Power</a></td><td colspan="4">?</td></tr><tr><th><a href="/facts/AMD_TrueAudio/085nbPwY">TrueAudio</a></th><td colspan="17">—</td><td colspan="2">Via dedicated <a href="/facts/Digital_signal_processing/PEG7azr8">DSP</a></td><td colspan="6">Via shaders</td></tr><tr><th><a href="/facts/FreeSync/UzEbg48y">FreeSync</a></th><td colspan="17">—</td><td colspan="8">12</td></tr><tr><th><a href="/facts/High-bandwidth_Digital_Content_Protection/zYhpvdCz">HDCP</a><a class="footnote-ref" id="fnref:35" href="#fn:35"><sup>35</sup></a></th><td colspan="10">—</td><td colspan="7">?</td><td colspan="2">1.4</td><td colspan="2">2.2</td><td colspan="4">2.3 <a class="footnote-ref" id="fnref:36" href="#fn:36"><sup>36</sup></a></td></tr><tr><th><a href="/facts/PlayReady/Cc0XStVx">PlayReady</a><a class="footnote-ref" id="fnref:37" href="#fn:37"><sup>37</sup></a></th><td colspan="19">—</td><td>3.0</td><td></td><td colspan="4">3.0</td></tr><tr><th>Supported displays<a class="footnote-ref" id="fnref:38" href="#fn:38"><sup>38</sup></a></th><td></td><td></td><td></td><td></td><td></td><td>1–2</td><td colspan="7">2</td><td colspan="8">2–6</td><td colspan="3">?</td><td>4</td></tr><tr><th>Max. <a href="/facts/Display_resolution/8LQTWvl3">resolution</a></th><td colspan="13">?</td><td colspan="3">2–6 ×2560×1600</td><td colspan="3">2–6 ×4096×2160 @ 30 Hz</td><td>2–6 ×5120×2880 @ 60 Hz</td><td>3 ×7680×4320 @ 60 Hz <a class="footnote-ref" id="fnref:39" href="#fn:39"><sup>39</sup></a></td><td colspan="2">7680×4320 @ 60 Hz <a href="https://www.powercolor.com/product?id=1623918640#spe">PowerColor</a></td><td>7680x4320<p>@165 Hz</p></td><td>7680x4320</td></tr><tr><th>/drm/radeon<a class="footnote-ref" id="fnref:40" href="#fn:40"><sup>40</sup></a></th><td></td><td></td><td></td><td></td><td></td><td colspan="13"></td><td colspan="7">—</td></tr><tr><th>/drm/amdgpu<a class="footnote-ref" id="fnref:41" href="#fn:41"><sup>41</sup></a></th><td colspan="17">—</td><td colspan="1">Optional <a class="footnote-ref" id="fnref:42" href="#fn:42"><sup>42</sup></a></td><td colspan="7"></td></tr></tbody></table> <h3>Feature overview for AMD APUs</h3> <p class="note">Main article: <a href="/facts/List_of_AMD_Accelerated_Processing_Unit_microprocessors/62q8zqca">List of AMD APUs</a></p> <p>AMD Eyefinity is also available in AMD's APU branded product line. The A10-7850K is said to support up to four displays. </p><p>The following table shows features of <a href="/facts/AMD/CB1G7QTb">AMD</a>'s processors with 3D graphics, including <a href="/facts/AMD_APU/hdApEUQw">APUs</a> (see also: <a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">List of AMD processors with 3D graphics</a>). </p> [ <a href="https://en.wikipedia.org/w/index.php?title=Template:Features_of_AMD_Processors_with_3D_Graphics&veaction=edit">VisualEditor</a> ] <ul><li>view</li><li>talk</li><li>edit</li></ul> <table><tbody><tr><th colspan="3">Platform</th><th colspan="14">High, standard and low power</th><th colspan="9">Low and ultra-low power</th></tr><tr><th rowspan="11">Codename</th><th rowspan="2">Server</th><th>Basic</th><th colspan="5"></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Toronto</a></th><th colspan="8"></th><th colspan="9"></th></tr><tr><th>Micro</th><th colspan="14"></th><th></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Kyoto</a></th><th colspan="7"></th></tr><tr><th rowspan="4">Desktop</th><th>Performance</th><th colspan="12"></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Raphael</a></th><th rowspan="3"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Phoenix</a></th><th colspan="9" rowspan="3"></th></tr><tr><th>Mainstream</th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Llano</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Trinity</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Richland</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Kaveri</a></th><th rowspan="2"><a href="/facts/Steamroller_(microarchitecture)/SxtLaauz">Kaveri Refresh (Godavari)</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Carrizo</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Bristol Ridge</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Raven Ridge</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Picasso</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Renoir</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Cezanne</a></th><th></th></tr><tr><th>Entry</th><th colspan="2"></th></tr><tr><th>Basic</th><th colspan="14"></th><th></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Kabini</a></th><th colspan="3"></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Dalí</a></th><th colspan="3"></th></tr><tr><th rowspan="4">Mobile</th><th>Performance</th><th colspan="9"></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Renoir</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Cezanne</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Rembrandt</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Dragon Range</a></th><th></th><th rowspan="2" colspan="9"></th></tr><tr><th>Mainstream</th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Llano</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Trinity</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Richland</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Kaveri</a></th><th rowspan="2"></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Carrizo</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Bristol Ridge</a></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Raven Ridge</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Picasso</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Renoir</a><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Lucienne</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Cezanne</a><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Barceló</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Phoenix</a></th></tr><tr><th>Entry</th><th colspan="6"></th><th colspan="5"></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Dalí</a></th><th colspan="2"></th><th rowspan="2"><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Mendocino</a></th></tr><tr><th>Basic</th><th colspan="14"></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Desna, Ontario, Zacate</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Kabini, Temash</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Beema, Mullins</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Carrizo-L</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Stoney Ridge</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Pollock</a></th><th></th></tr><tr><th colspan="2">Embedded</th><th></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Trinity</a></th><th></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Bald Eagle</a></th><th></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Merlin Falcon</a>,<a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Brown Falcon</a></th><th></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Great Horned Owl</a></th><th></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Grey Hawk</a></th><th colspan="4"></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Ontario, Zacate</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Kabini</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Steppe Eagle</a>, <a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Crowned Eagle</a>, <a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">LX-Family</a></th><th></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Prairie Falcon</a></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">Banded Kestrel</a></th><th></th><th><a href="/facts/List_of_AMD_processors_with_3D_graphics/62q8zqca">River Hawk</a></th><th></th></tr><tr><td colspan="3">Released</td><td>Aug 2011</td><td>Oct 2012</td><td>Jun 2013</td><td>Jan 2014</td><td>2015</td><td>Jun 2015</td><td>Jun 2016</td><td>Oct 2017</td><td>Jan 2019</td><td>Mar 2020</td><td>Jan 2021</td><td>Jan 2022</td><td>Sep 2022</td><td>Jan 2023</td><td>Jan 2011</td><td>May 2013</td><td>Apr 2014</td><td>May 2015</td><td>Feb 2016</td><td>Apr 2019</td><td>Jul 2020</td><td>Jun 2022</td><td>Nov 2022</td></tr><tr><td colspan="3">CPU <a href="/facts/Microarchitecture/NFRd4NUL">microarchitecture</a></td><td><a href="/facts/AMD_10h/2hQAazep">K10</a></td><td colspan="2"><a href="/facts/Piledriver_(microarchitecture)/Fhxly06H">Piledriver</a></td><td colspan="2"><a href="/facts/Steamroller_(microarchitecture)/SxtLaauz">Steamroller</a></td><td><a href="/facts/Excavator_(microarchitecture)/Bzj9WKGV">Excavator</a></td><td>"<a href="/facts/Excavator_(microarchitecture)/Bzj9WKGV">Excavator+</a>"<a class="footnote-ref" id="fnref:43" href="#fn:43"><sup>43</sup></a></td><td><a href="/facts/Zen_(first_generation)/oChXIp3y">Zen</a></td><td><a href="/facts/Zen%252B/1bJfQtRR">Zen+</a></td><td><a href="/facts/Zen_2/pdL7I80c">Zen 2</a></td><td><a href="/facts/Zen_3/szGTAfyB">Zen 3</a></td><td><a href="/facts/Zen_3%252B/szGTAfyB">Zen 3+</a></td><td colspan="2"><a href="/facts/Zen_4/UJXLYNuq">Zen 4</a></td><td><a href="/facts/Bobcat_(microarchitecture)/EweFKE9J">Bobcat</a></td><td><a href="/facts/Jaguar_(microarchitecture)/PkCbNj9a">Jaguar</a></td><td><a href="/facts/Puma_(microarchitecture)/ujJ1MBg1">Puma</a></td><td><a href="/facts/Puma_(microarchitecture)/ujJ1MBg1">Puma+</a><a class="footnote-ref" id="fnref:44" href="#fn:44"><sup>44</sup></a></td><td>"<a href="/facts/Excavator_(microarchitecture)/Bzj9WKGV">Excavator+</a>"</td><td colspan="2"><a href="/facts/Zen_(first_generation)/oChXIp3y">Zen</a></td><td><a href="/facts/Zen%252B/1bJfQtRR">Zen+</a></td><td>"<a href="/facts/Zen_2/pdL7I80c">Zen 2+</a>"</td></tr><tr><td colspan="3"><a href="/facts/Instruction_set_architecture/8p8vwUeE">ISA</a></td><td><a href="/facts/X86-64/cyWvUFlP">x86-64</a> v1</td><td colspan="4"><a href="/facts/X86-64/cyWvUFlP">x86-64</a> v2</td><td colspan="7"><a href="/facts/X86-64/cyWvUFlP">x86-64</a> v3</td><td colspan="2"><a href="/facts/X86-64/cyWvUFlP">x86-64</a> v4</td><td><a href="/facts/X86-64/cyWvUFlP">x86-64</a> v1</td><td colspan="3"><a href="/facts/X86-64/cyWvUFlP">x86-64</a> v2</td><td colspan="5"><a href="/facts/X86-64/cyWvUFlP">x86-64</a> v3</td></tr><tr><td rowspan="5">Socket</td><td rowspan="4">Desktop</td><td>Performance</td><td colspan="12">—</td><td rowspan="2"><a href="/facts/Socket_AM5/x4zuI5Ck">AM5</a></td><td>—</td><td rowspan="3" colspan="9">—</td></tr><tr><td>Mainstream</td><td colspan="5">—</td><td colspan="6"><a href="/facts/Socket_AM4/MuNKCgeF">AM4</a></td><td>—</td><th>—</th></tr><tr><td>Entry</td><td><a href="/facts/Socket_FM1/vrA6VVSD">FM1</a></td><td colspan="2"><a href="/facts/Socket_FM2/olCXfpAL">FM2</a></td><td colspan="2"><a href="/facts/Socket_FM2%252B/GQlcTMJW">FM2+</a></td><td><a href="/facts/Socket_FM2%252B/GQlcTMJW">FM2+</a><a class="footnote-ref" id="fnref:45" href="#fn:45"><sup>45</sup></a>, <a href="/facts/Socket_AM4/MuNKCgeF">AM4</a></td><td colspan="5"><a href="/facts/Socket_AM4/MuNKCgeF">AM4</a></td><td colspan="3">—</td></tr><tr><td>Basic</td><td colspan="14">—</td><td>—</td><td><a href="/facts/Socket_AM1/43Q9guVD">AM1</a></td><td colspan="3">—</td><td>FP5</td><td colspan="3">—</td></tr><tr><td colspan="2">Other</td><td><a href="/facts/Socket_FS1/GGxHBYCC">FS1</a></td><td colspan="2"><a href="/facts/Socket_FS1r2/GGxHBYCC">FS1+</a>, <a href="/facts/Socket_FP2/c8WeE1u8">FP2</a></td><td colspan="2"><a href="/facts/Socket_FP3/7vDcpQfR">FP3</a></td><td colspan="2">FP4</td><td colspan="2">FP5</td><td colspan="2">FP6</td><td>FP7</td><td>FL1</td><td>FP7 FP7r2 FP8</td><td><a href="/facts/Socket_FT1/IuvuQVPW">FT1</a></td><td><a href="/facts/Socket_FT3/PC1tK41m">FT3</a></td><td colspan="2"><a href="/facts/Socket_FT3b/PC1tK41m">FT3b</a></td><td>FP4</td><td>FP5</td><td>FT5</td><td>FP5</td><td>FT6</td></tr><tr><td colspan="3"><a href="/facts/PCI_Express/ADhsLCUK">PCI Express</a> version</td><td colspan="3">2.0</td><td colspan="8">3.0</td><td>4.0</td><td>5.0</td><td>4.0</td><td colspan="4">2.0</td><td colspan="5">3.0</td></tr><tr><td colspan="3"><a href="/facts/Compute_Express_Link/YSJGcCMx">CXL</a></td><td colspan="14">—</td><td colspan="9">—</td></tr><tr><td colspan="3"><a href="/facts/Semiconductor_device_fabrication/Jd23Mu1z">Fab.</a> (<a href="/facts/Nanometre/a98sjHyu">nm</a>)</td><td colspan="3"><a href="/facts/GlobalFoundries/lFTS5fbT">GF</a> <a href="/facts/32_nm_process/CsdohJVh">32SHP</a>(<a href="/facts/HKMG/4E8qtXmp">HKMG</a> <a href="/facts/Silicon_on_insulator/fxSkXYmw">SOI</a>)</td><td colspan="4">GF <a href="/facts/32_nm_process/CsdohJVh">28SHP</a>(HKMG bulk)</td><td>GF <a href="/facts/14_nm_process/lQYsD92n">14LPP</a>(<a href="/facts/FinFET/xox63kP7">FinFET</a> bulk)</td><td>GF <a href="/facts/14_nm_process/lQYsD92n">12LP</a>(FinFET bulk)</td><td colspan="2"><a href="/facts/TSMC/B4BdojRk">TSMC</a> <a href="/facts/7_nm_process/7UatqvR9">N7</a>(FinFET bulk)</td><td>TSMC <a href="/facts/7_nm_process/7UatqvR9">N6</a> (FinFET bulk)</td><td>CCD: TSMC <a href="/facts/5_nm_process/5NndITJ3">N5</a> (FinFET bulk)cIOD: TSMC <a href="/facts/7_nm_process/7UatqvR9">N6</a>(FinFET bulk)</td><td>TSMC <a href="/facts/5_nm_process/5NndITJ3">4nm</a> (FinFET bulk)</td><td>TSMC <a href="/facts/45_nm_process/hlbmxAme">N40</a>(bulk)</td><td>TSMC <a href="/facts/32_nm_process/CsdohJVh">N28</a>(HKMG bulk)</td><td colspan="3">GF 28SHP(HKMG bulk)</td><td colspan="2">GF <a href="/facts/14_nm_process/lQYsD92n">14LPP</a>(<a href="/facts/FinFET/xox63kP7">FinFET</a> bulk)</td><td>GF <a href="/facts/14_nm_process/lQYsD92n">12LP</a>(FinFET bulk)</td><td>TSMC <a href="/facts/7_nm_process/7UatqvR9">N6</a> (FinFET bulk)</td></tr><tr><td colspan="3"><a href="/facts/Die_(integrated_circuit)/XWvdlltE">Die</a> area (mm2)</td><td>228</td><td colspan="2">246</td><td colspan="2">245</td><td>245</td><td>250</td><td colspan="2">210<a class="footnote-ref" id="fnref:46" href="#fn:46"><sup>46</sup></a></td><td>156</td><td>180</td><td>210</td><td>CCD: (2x) 70cIOD: 122</td><td>178</td><td>75 (+ 28 <a href="/facts/List_of_AMD_chipsets/AesBnfxQ">FCH</a>)</td><td colspan="2">107</td><td>?</td><td>125</td><td>149</td><td></td><td></td><td>~100</td></tr><tr><td colspan="3">Min <a href="/facts/Thermal_Design_Power/Idcy26tM">TDP</a> (W)</td><td>35</td><td colspan="4">17</td><td colspan="4">12</td><td colspan="2">10</td><td>15</td><td>65</td><td>35</td><td>4.5</td><td>4</td><td>3.95</td><td>10</td><td colspan="3">6</td><td>12</td><td>8</td></tr><tr><td colspan="3">Max APU <a href="/facts/Thermal_Design_Power/Idcy26tM">TDP</a> (W)</td><td colspan="3">100</td><td colspan="2">95</td><td colspan="6">65</td><td>45</td><td>170</td><td>54</td><td>18</td><td colspan="5">25</td><td>6</td><td>54</td><td>15</td></tr><tr><td colspan="3">Max stock APU base clock (GHz)</td><td>3</td><td>3.8</td><td>4.1</td><td colspan="2">4.1</td><td>3.7</td><td>3.8</td><td>3.6</td><td>3.7</td><td>3.8</td><td>4.0</td><td>3.3</td><td>4.7</td><td>4.3</td><td>1.75</td><td>2.2</td><td>2</td><td>2.2</td><td>3.2</td><td>2.6</td><td>1.2</td><td>3.35</td><td>2.8</td></tr><tr><td colspan="3">Max APUs per node<a class="footnote-ref" id="fnref:47" href="#fn:47"><sup>47</sup></a></td><td colspan="14">1</td><td colspan="9">1</td></tr><tr><td colspan="3">Max core dies per CPU</td><td colspan="12">1</td><td>2</td><td>1</td><td colspan="9">1</td></tr><tr><td colspan="3">Max CCX per core die</td><td colspan="9">1</td><td>2</td><td colspan="4">1</td><td colspan="9">1</td></tr><tr><td colspan="3">Max cores per CCX</td><td colspan="10">4</td><td colspan="4">8</td><td>2</td><td colspan="3">4</td><td colspan="3">2</td><td colspan="2">4</td></tr><tr><td colspan="3">Max <a href="/facts/Central_processing_unit/Jxp1bqMV">CPU</a><a class="footnote-ref" id="fnref:48" href="#fn:48"><sup>48</sup></a> <a href="/facts/Multi-core_processor/ABNb65hQ">cores</a> per APU</td><td colspan="9">4</td><td colspan="3">8</td><td>16</td><td>8</td><td>2</td><td colspan="3">4</td><td colspan="3">2</td><td colspan="2">4</td></tr><tr><td colspan="3">Max <a href="/facts/Thread_(computing)/hh8WHyPd">threads</a> per CPU core</td><td colspan="7">1</td><td colspan="7">2</td><td colspan="5">1</td><td colspan="4">2</td></tr><tr><td colspan="3">Integer pipeline structure</td><td>3+3</td><td colspan="6">2+2</td><td colspan="2">4+2</td><td>4+2+1</td><td colspan="4">1+3+3+1+2</td><td colspan="4">1+1+1+1</td><td>2+2</td><td colspan="3">4+2</td><td>4+2+1</td></tr><tr><td colspan="3">i386, i486, i586, CMOV, NOPL, i686, <a href="/facts/Physical_Address_Extension/aEr4tj4x">PAE</a>, <a href="/facts/NX_bit/MnBB93BK">NX bit</a>, CMPXCHG16B, <a href="/facts/AMD-V/utQwmdY3">AMD-V</a>, <a href="/facts/Second_Level_Address_Translation/WY0j2dRv">RVI</a>, <a href="/facts/Bit_Manipulation_Instruction_Sets/LJAm1LWC">ABM</a>, and 64-bit LAHF/SAHF</td><td colspan="14"></td><td colspan="9"></td></tr><tr><td colspan="3"><a href="/facts/IOMMU/lvVkzUyw">IOMMU</a><a class="footnote-ref" id="fnref:49" href="#fn:49"><sup>49</sup></a></td><td rowspan="2">—</td><td colspan="13">v2</td><td colspan="2">v1</td><td colspan="7">v2</td></tr><tr><td colspan="3"><a href="/facts/Bit_Manipulation_Instruction_Sets/LJAm1LWC">BMI1</a>, <a href="/facts/AES_instruction_set/NomFEB4w">AES-NI</a>, <a href="/facts/CLMUL/UzzxBF65">CLMUL</a>, and <a href="/facts/F16C/v6G70oa7">F16C</a></td><td colspan="13"></td><td rowspan="2">—</td><td colspan="9" rowspan="2"></td></tr><tr><td colspan="3">MOVBE</td><td colspan="5" rowspan="2">—</td><td rowspan="2" colspan="9"></td></tr><tr><td colspan="3"><a href="/facts/X86_virtualization/utQwmdY3">AVIC</a>, <a href="/facts/Bit_Manipulation_Instruction_Sets/LJAm1LWC">BMI2</a>, <a href="/facts/RDRAND/IdeN4y36">RDRAND</a>, and MWAITX/MONITORX</td><td colspan="4">—</td><td colspan="5"></td></tr><tr><td colspan="3">SME<a class="footnote-ref" id="fnref:50" href="#fn:50"><sup>50</sup></a>, TSME<a class="footnote-ref" id="fnref:51" href="#fn:51"><sup>51</sup></a>, <a href="/facts/Intel_ADX/7I3KDzYA">ADX</a>, <a href="/facts/Intel_SHA_extensions/qDzy2N70">SHA</a>, <a href="/facts/RDSEED/IdeN4y36">RDSEED</a>, <a href="/facts/Supervisor_Mode_Access_Prevention/H8RSCNy2">SMAP</a>, <a href="/facts/Control_register/9VGRHh3f">SMEP</a>, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing</td><td colspan="7">—</td><td colspan="7"></td><td colspan="5">—</td><td colspan="4"></td></tr><tr><td colspan="3"><a href="/facts/Second_Level_Address_Translation/WY0j2dRv">GMET</a>, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT</td><td colspan="9">—</td><td colspan="5"></td><td colspan="8">—</td><td></td></tr><tr><td colspan="3"><a href="/facts/Memory_protection/3zDwN2SG">MPK</a>, VAES</td><td colspan="10">—</td><td colspan="4"></td><td colspan="9">—</td></tr><tr><td colspan="3"><a href="/facts/Software_Guard_Extensions/HcgbyB5P">SGX</a></td><td colspan="14">—</td><td colspan="9">—</td></tr><tr><td colspan="3"><a href="/facts/Floating-point_unit/XWTW2AbF">FPUs</a> per <a href="/facts/Multi-core_processor/ABNb65hQ">core</a></td><td>1</td><td colspan="6">0.5</td><td colspan="7">1</td><td colspan="4">1</td><td>0.5</td><td colspan="4">1</td></tr><tr><td colspan="3">Pipes per FPU</td><td colspan="14">2</td><td colspan="9">2</td></tr><tr><td colspan="3">FPU pipe width</td><td colspan="9">128-bit</td><td colspan="5">256-bit</td><td>80-bit</td><td colspan="7">128-bit</td><td>256-bit</td></tr><tr><td colspan="3">CPU <a href="/facts/Instruction_set/8p8vwUeE">instruction set</a> <a href="/facts/Single_instruction%2c_multiple_data/gQHWQSpo">SIMD</a> level</td><td><a href="/facts/SSE4a/Tnxrl7Ph">SSE4a</a><a class="footnote-ref" id="fnref:52" href="#fn:52"><sup>52</sup></a></td><td colspan="4"><a href="/facts/Advanced_Vector_Extensions/znDpc6Vt">AVX</a></td><td colspan="7"><a href="/facts/Advanced_Vector_Extensions/znDpc6Vt">AVX2</a></td><td colspan="2"><a href="/facts/AVX-512/2KpGqI8t">AVX-512</a></td><td><a href="/facts/SSSE3/xlRTcz4I">SSSE3</a></td><td colspan="3"><a href="/facts/Advanced_Vector_Extensions/znDpc6Vt">AVX</a></td><td colspan="5"><a href="/facts/Advanced_Vector_Extensions/znDpc6Vt">AVX2</a></td></tr><tr><td colspan="3"><a href="/facts/3DNow!/QYJL2HBt">3DNow!</a></td><td><a href="/facts/3DNow!/QYJL2HBt">3DNow!+</a></td><td colspan="13">—</td><td colspan="9">—</td></tr><tr><td colspan="3"><a href="/facts/PREFETCHW/QYJL2HBt">PREFETCH/PREFETCHW</a></td><td colspan="14"></td><td colspan="9"></td></tr><tr><td colspan="3">GFNI</td><td colspan="12">—</td><td colspan="2"></td><td rowspan="2" colspan="9">—</td></tr><tr><td colspan="3"><a href="/facts/Advanced_Matrix_Extensions/qkDBQbBE">AMX</a></td><td colspan="14">—</td></tr><tr><td colspan="3"><a href="/facts/FMA4/mqglSHqk">FMA4</a>, LWP, <a href="/facts/Bit_Manipulation_Instruction_Sets/LJAm1LWC">TBM</a>, and <a href="/facts/XOP_instruction_set/Xey2cAGM">XOP</a></td><td rowspan="2">—</td><td colspan="6"></td><td colspan="7">—</td><td rowspan="2" colspan="4">—</td><td></td><td colspan="4">—</td></tr><tr><td colspan="3"><a href="/facts/FMA3/mqglSHqk">FMA3</a></td><td colspan="13"></td><td colspan="5"></td></tr><tr><td colspan="3"><a href="/facts/AMD_XDNA/Yafyvy2F">AMD XDNA</a></td><td colspan="13">—</td><td></td><td colspan="9">—</td></tr><tr><td colspan="3"><a href="/facts/L1_cache/x8BYFcdv">L1</a> data cache per core (KiB)</td><td>64</td><td colspan="4">16</td><td colspan="9">32</td><td colspan="9">32</td></tr><tr><td colspan="3">L1 data cache <a href="/facts/Cache_placement_policies/MuBjrreM">associativity</a> (ways)</td><td>2</td><td colspan="4">4</td><td colspan="9">8</td><td colspan="9">8</td></tr><tr><td colspan="3">L1 instruction caches per <a href="/facts/Multi-core_processor/ABNb65hQ">core</a></td><td>1</td><td colspan="6">0.5</td><td colspan="7">1</td><td colspan="4">1</td><td>0.5</td><td colspan="4">1</td></tr><tr><td colspan="3">Max APU total L1 instruction cache (KiB)</td><td>256</td><td colspan="2">128</td><td colspan="4">192</td><td colspan="5">256</td><td>512</td><td>256</td><td colspan="2">64</td><td colspan="2">128</td><td>96</td><td colspan="4">128</td></tr><tr><td colspan="3">L1 instruction cache <a href="/facts/Cache_placement_policies/MuBjrreM">associativity</a> (ways)</td><td colspan="3">2</td><td colspan="4">3</td><td colspan="2">4</td><td colspan="5">8</td><td colspan="4">2</td><td>3</td><td colspan="3">4</td><td>8</td></tr><tr><td colspan="3"><a href="/facts/L2_cache/x8BYFcdv">L2 caches</a> per <a href="/facts/Multi-core_processor/ABNb65hQ">core</a></td><td>1</td><td colspan="6">0.5</td><td colspan="7">1</td><td colspan="4">1</td><td>0.5</td><td colspan="4">1</td></tr><tr><td colspan="3">Max APU total L2 cache (MiB)</td><td colspan="5">4</td><td colspan="4">2</td><td colspan="3">4</td><td>16</td><td></td><td>1</td><td colspan="3">2</td><td colspan="3">1</td><td colspan="2">2</td></tr><tr><td colspan="3">L2 cache <a href="/facts/Cache_placement_policies/MuBjrreM">associativity</a> (ways)</td><td colspan="7">16</td><td colspan="7">8</td><td colspan="5">16</td><td colspan="4">8</td></tr><tr><td colspan="3">Max on-die <a href="/facts/L3_cache/x8BYFcdv">L3 cache</a> per CCX (MiB)</td><td colspan="7" rowspan="8">—</td><td colspan="3">4</td><td colspan="2">16</td><td>32</td><td></td><td colspan="6" rowspan="8">—</td><td colspan="4">4</td></tr><tr><td colspan="3">Max 3D V-Cache per CCD (MiB)</td><td colspan="5">—</td><td>64</td><td>—</td><td colspan="4">—</td></tr><tr><td colspan="3">Max total in-CCD <a href="/facts/L3_cache/x8BYFcdv">L3 cache</a> per APU (MiB)</td><td colspan="2">4</td><td>8</td><td colspan="2">16</td><td>64</td><td></td><td colspan="4">4</td></tr><tr><td colspan="3">Max. total 3D V-Cache per APU (MiB)</td><td colspan="5">—</td><td>64</td><td>—</td><td colspan="4">—</td></tr><tr><td colspan="3">Max. board <a href="/facts/L3_cache/x8BYFcdv">L3 cache</a> per APU (MiB)</td><td colspan="7">—</td><td colspan="4">—</td></tr><tr><td colspan="3">Max total <a href="/facts/L3_cache/x8BYFcdv">L3 cache</a> per APU (MiB)</td><td colspan="2">4</td><td>8</td><td colspan="2">16</td><td>128</td><td></td><td colspan="4">4</td></tr><tr><td colspan="3">APU L3 cache <a href="/facts/Cache_placement_policies/MuBjrreM">associativity</a> (ways)</td><td colspan="7">16</td><td colspan="4">16</td></tr><tr><td colspan="3">L3 cache scheme</td><td colspan="7"><a href="/facts/Victim_cache/7efuQ3PY">Victim</a></td><td colspan="4"><a href="/facts/Victim_cache/7efuQ3PY">Victim</a></td></tr><tr><td colspan="3">Max. <a href="/facts/L4_cache/x8BYFcdv">L4 cache</a></td><td colspan="14">—</td><td colspan="9">—</td></tr><tr><td colspan="3">Max stock <a href="/facts/Dynamic_random-access_memory/koI9FGo5">DRAM</a> support</td><td colspan="2"><a href="/facts/DDR3_SDRAM/1R1CTNv3">DDR3</a>-1866</td><td colspan="3">DDR3-2133</td><td>DDR3-2133, <a href="/facts/DDR4_SDRAM/70r37baX">DDR4</a>-2400</td><td>DDR4-2400</td><td colspan="2">DDR4-2933</td><td colspan="2">DDR4-3200, <a href="/facts/LPDDR/2XdLrg47">LPDDR4</a>-4266</td><td><a href="/facts/DDR5_SDRAM/N3XSGE40">DDR5</a>-4800, <a href="/facts/LPDDR/2XdLrg47">LPDDR5</a>-6400</td><td><a href="/facts/DDR5_SDRAM/N3XSGE40">DDR5</a>-5200</td><td><a href="/facts/DDR5_SDRAM/N3XSGE40">DDR5</a>-5600, <a href="/facts/LPDDR/2XdLrg47">LPDDR5x</a>-7500</td><td><a href="/facts/DDR3L/1R1CTNv3">DDR3L</a>-1333</td><td>DDR3L-1600</td><td colspan="2">DDR3L-1866</td><td>DDR3-1866, <a href="/facts/DDR4_SDRAM/70r37baX">DDR4</a>-2400</td><td>DDR4-2400</td><td>DDR4-1600</td><td>DDR4-3200</td><td>LPDDR5-5500</td></tr><tr><td colspan="3">Max <a href="/facts/Dynamic_random-access_memory/koI9FGo5">DRAM</a> channels per APU</td><td colspan="14">2</td><td colspan="5">1</td><td>2</td><td>1</td><td colspan="2">2</td></tr><tr><td colspan="3">Max stock <a href="/facts/Dynamic_random-access_memory/koI9FGo5">DRAM</a> <a href="/facts/Bandwidth_(computing)/lY6Tb4gX">bandwidth</a> (GB/s) per APU</td><td colspan="2">29.866</td><td colspan="3">34.132</td><td colspan="2">38.400</td><td colspan="2">46.932</td><td colspan="2">68.256</td><td>102.400</td><td>83.200</td><td>120.000</td><td>10.666</td><td>12.800</td><td colspan="2">14.933</td><td>19.200</td><td>38.400</td><td>12.800</td><td>51.200</td><td>88.000</td></tr><tr><td colspan="3">GPU <a href="/facts/Microarchitecture/NFRd4NUL">microarchitecture</a></td><td><a href="/facts/TeraScale_(microarchitecture)/Yt6jwq9b">TeraScale 2 (VLIW5)</a></td><td colspan="2"><a href="/facts/TeraScale_(microarchitecture)/Yt6jwq9b">TeraScale 3 (VLIW4)</a></td><td colspan="2"><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN 2nd gen</a></td><td colspan="2"><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN 3rd gen</a></td><td colspan="4"><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN 5th gen</a><a class="footnote-ref" id="fnref:53" href="#fn:53"><sup>53</sup></a></td><td colspan="2"><a href="/facts/RDNA_2/tplgu8A1">RDNA 2</a></td><td><a href="/facts/RDNA_3/tCrEHPQu">RDNA 3</a></td><td><a href="/facts/TeraScale_(microarchitecture)/Yt6jwq9b">TeraScale 2 (VLIW5)</a></td><td colspan="3"><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN 2nd gen</a></td><td><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN 3rd gen</a><a class="footnote-ref" id="fnref:54" href="#fn:54"><sup>54</sup></a></td><td colspan="3"><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN 5th gen</a></td><td><a href="/facts/RDNA_2/tplgu8A1">RDNA 2</a></td></tr><tr><td colspan="3">GPU <a href="/facts/Instruction_set/8p8vwUeE">instruction set</a></td><td colspan="3"><a href="/facts/TeraScale_(microarchitecture)/Yt6jwq9b">TeraScale</a> instruction set</td><td colspan="8"><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN instruction set</a></td><td colspan="3"><a href="/facts/RDNA_(microarchitecture)/tplgu8A1">RDNA instruction set</a></td><td><a href="/facts/TeraScale_(microarchitecture)/Yt6jwq9b">TeraScale</a> instruction set</td><td colspan="7"><a href="/facts/Graphics_Core_Next/WYNvhDUP">GCN instruction set</a></td><td><a href="/facts/RDNA_(microarchitecture)/tplgu8A1">RDNA instruction set</a></td></tr><tr><td colspan="3">Max stock GPU base clock (MHz)</td><td>600</td><td>800</td><td>844</td><td colspan="2">866</td><td colspan="2">1108</td><td>1250</td><td>1400</td><td colspan="2">2100</td><td>2400</td><td>400</td><td></td><td>538</td><td>600</td><td>?</td><td>847</td><td>900</td><td>1200</td><td>600</td><td>1300</td><td>1900</td></tr><tr><td colspan="3">Max stock GPU base <a href="/facts/GFLOPS/6zYlH68F">GFLOPS</a><a class="footnote-ref" id="fnref:55" href="#fn:55"><sup>55</sup></a></td><td>480</td><td>614.4</td><td>648.1</td><td colspan="2">886.7</td><td colspan="2">1134.5</td><td>1760</td><td>1971.2</td><td colspan="2">2150.4</td><td>3686.4</td><td>102.4</td><td></td><td>86</td><td>?</td><td>?</td><td>?</td><td>345.6</td><td>460.8</td><td>230.4</td><td>1331.2</td><td>486.4</td></tr><tr><td rowspan="2" colspan="3">3D engine<a class="footnote-ref" id="fnref:56" href="#fn:56"><sup>56</sup></a></td><td>Up to 400:20:8</td><td colspan="2">Up to 384:24:6</td><td colspan="4">Up to 512:32:8</td><td colspan="2">Up to 704:44:16<a class="footnote-ref" id="fnref:57" href="#fn:57"><sup>57</sup></a></td><td colspan="2">Up to 512:32:8</td><td>768:48:8</td><td>128:8:4</td><td></td><td>80:8:4</td><td colspan="3">128:8:4</td><td>Up to 192:12:8</td><td>Up to 192:12:4</td><td>192:12:4</td><td>Up to 512:?:?</td><td>128:?:?</td></tr><tr><td colspan="3">IOMMUv1</td><td colspan="11"><a href="/facts/Heterogeneous_Memory_Management/uwayMPnT">IOMMUv2</a></td><td colspan="2">IOMMUv1</td><td colspan="2">?</td><td colspan="5">IOMMUv2</td></tr><tr><td colspan="3">Video decoder</td><td colspan="3"><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD 3.0</a></td><td colspan="2"><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD 4.2</a></td><td colspan="2"><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD 6.0</a></td><td rowspan="2" colspan="2"><a href="/facts/Video_Core_Next/I0GL8eMR">VCN</a> 1.0<a class="footnote-ref" id="fnref:58" href="#fn:58"><sup>58</sup></a></td><td rowspan="2">VCN 2.1<a class="footnote-ref" id="fnref:59" href="#fn:59"><sup>59</sup></a></td><td rowspan="2">VCN 2.2<a class="footnote-ref" id="fnref:60" href="#fn:60"><sup>60</sup></a></td><td colspan="2" rowspan="2">VCN 3.1</td><td rowspan="2">?</td><td><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD 3.0</a></td><td><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD 4.0</a></td><td colspan="2"><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD 4.2</a></td><td><a href="/facts/Unified_Video_Decoder/aQrrwg54">UVD 6.2</a></td><td rowspan="2" colspan="3"><a href="/facts/Video_Core_Next/I0GL8eMR">VCN 1.0</a></td><td rowspan="2">VCN 3.1</td></tr><tr><td colspan="3">Video encoder</td><td>—</td><td colspan="2"><a href="/facts/Video_Coding_Engine/4L5MLb6K">VCE 1.0</a></td><td colspan="2"><a href="/facts/Video_Coding_Engine/4L5MLb6K">VCE 2.0</a></td><td colspan="2"><a href="/facts/Video_Coding_Engine/4L5MLb6K">VCE 3.1</a></td><td>—</td><td colspan="3"><a href="/facts/Video_Coding_Engine/4L5MLb6K">VCE 2.0</a></td><td><a href="/facts/Video_Coding_Engine/4L5MLb6K">VCE 3.4</a></td></tr><tr><td colspan="3">AMD Fluid Motion</td><td colspan="3"></td><td colspan="4"></td><td colspan="7"></td><td colspan="2"></td><td colspan="3"></td><td colspan="4"></td></tr><tr><td colspan="3">GPU power saving</td><td><a href="/facts/AMD_PowerPlay/By12rf5S">PowerPlay</a></td><td colspan="13"><a href="/facts/AMD_PowerTune/NMNAqExx">PowerTune</a></td><td><a href="/facts/AMD_PowerPlay/By12rf5S">PowerPlay</a></td><td colspan="8"><a href="/facts/AMD_PowerTune/NMNAqExx">PowerTune</a><a class="footnote-ref" id="fnref:61" href="#fn:61"><sup>61</sup></a></td></tr><tr><td colspan="3"><a href="/facts/AMD_TrueAudio/085nbPwY">TrueAudio</a></td><td colspan="3" rowspan="2">—</td><td colspan="7"><a class="footnote-ref" id="fnref:62" href="#fn:62"><sup>62</sup></a></td><td colspan="4">?</td><td rowspan="2">—</td><td colspan="8"></td></tr><tr><td colspan="3"><a href="/facts/FreeSync/UzEbg48y">FreeSync</a></td><td colspan="11">12</td><td colspan="88">12</td></tr><tr><td colspan="3"><a href="/facts/HDCP/zYhpvdCz">HDCP</a><a class="footnote-ref" id="fnref:63" href="#fn:63"><sup>63</sup></a></td><td colspan="3">?</td><td colspan="4">1.4</td><td colspan="4">2.2</td><td colspan="3">2.3</td><td>?</td><td colspan="4">1.4</td><td colspan="3">2.2</td><td>2.3</td></tr><tr><td colspan="3"><a href="/facts/PlayReady/Cc0XStVx">PlayReady</a><a class="footnote-ref" id="fnref:64" href="#fn:64"><sup>64</sup></a></td><td colspan="7">—</td><td colspan="7">3.0 not yet</td><td colspan="5">—</td><td colspan="4">3.0 not yet</td></tr><tr><td colspan="3">Supported displays<a class="footnote-ref" id="fnref:65" href="#fn:65"><sup>65</sup></a></td><td>2–3</td><td colspan="4">2–4</td><td colspan="2">3</td><td colspan="2">3 (desktop)4 (mobile, embedded)</td><td colspan="5">4</td><td colspan="4">2</td><td>3</td><td>4</td><td></td><td colspan="2">4</td></tr><tr><td colspan="3">/drm/radeon<a class="footnote-ref" id="fnref:66" href="#fn:66"><sup>66</sup></a><a class="footnote-ref" id="fnref:67" href="#fn:67"><sup>67</sup></a><a class="footnote-ref" id="fnref:68" href="#fn:68"><sup>68</sup></a></td><td colspan="6"></td><td colspan="8">—</td><td colspan="4"></td><td colspan="5">—</td></tr><tr><td colspan="3">/drm/amdgpu<a class="footnote-ref" id="fnref:69" href="#fn:69"><sup>69</sup></a><a class="footnote-ref" id="fnref:70" href="#fn:70"><sup>70</sup></a></td><td colspan="3">—</td><td colspan="11"><a class="footnote-ref" id="fnref:71" href="#fn:71"><sup>71</sup></a></td><td>—</td><td colspan="8"><a class="footnote-ref" id="fnref:72" href="#fn:72"><sup>72</sup></a></td></tr></tbody></table> <h2 id="software-support">Software support</h2> <p><a href="/facts/AMD_Catalyst/ntMxIHW0">AMD Catalyst</a> supports Eyefinity and enables the user to independently configure and run each attached displays. It facilitates the configuration of "cloned mode", i.e. to copy one desktop onto multiple screens or "extended mode", i.e. to span the workspace across multiple screens and combine the resolutions of all of those displays into one big resolution. AMD calls the extended modes Single Large Surface (SLS) and Catalyst support of certain range of display group configurations. For example, 5x1 landscape and 5x1 portrait are supported since AMD Catalyst version 11.10 from October 2011.<a class="footnote-ref" id="fnref:73" href="#fn:73"><sup>73</sup></a><a class="footnote-ref" id="fnref:74" href="#fn:74"><sup>74</sup></a> </p><p>Starting in Catalyst 14.6, AMD supports mixed resolution support, so a single Eyefinity display group can drive each monitor at a different resolution. This is provided through two new Eyefinity display modes, <i>Fit</i> and <i>Expand</i>, in addition to the existing <i>Fill</i> mode. In Fit or Expand mode, AMD compensates for mismatched resolutions by creating a virtual desktop of a different resolution than the monitors, and then either padding it out or cropping it as is necessary.<a class="footnote-ref" id="fnref:75" href="#fn:75"><sup>75</sup></a> </p><p>AMD Eyefinity works with games that support non-standard aspect ratios, which is required for panning across multiple displays. SLS ("Single Large Surface") mode requires an identical display resolution on all configured displays. AMD validated some video games to support Eyefinity. The short list includes titles such as <a href="/facts/Age_of_Conan/4DNLf8Iq">Age of Conan</a>, <a href="/facts/ARMA_2%3a_Operation_Arrowhead/lKp05ybA">ARMA 2: Operation Arrowhead</a>, <a href="/facts/S.T.A.L.K.E.R.%3a_Call_of_Pripyat/0JWL5nF9">S.T.A.L.K.E.R.: Call of Pripyat</a>, <a href="/facts/Serious_Sam_3%3a_BFE/n4Q3DP2M">Serious Sam 3: BFE</a>, <a href="/facts/Singularity_(video_game)/NK22eFXr">Singularity (video game)</a>, <a href="/facts/Sleeping_Dogs_(video_game)/9RK7YpUU">Sleeping Dogs</a>, <a href="/facts/Assassin%2527s_Creed_II/QMpKvJIv">Assassin's Creed II</a>, <a href="/facts/Sniper_Elite_V2/n9c6mKhk">Sniper Elite V2</a>, <a href="/facts/Soldier_of_Fortune_(video_game)/BbVew4Sr">Soldier of Fortune Online</a>, <a href="/facts/Tom_Clancy%2527s_Splinter_Cell%3a_Conviction/D6Y8v5cF">Tom Clancy's Splinter Cell: Conviction</a>, <a href="/facts/Star_Wars%3a_The_Force_Unleashed_2/FxUQnvLz">Star Wars: The Force Unleashed 2</a>, <a href="/facts/Marvel_Super_Hero_Squad_Online/STqssDzj">Marvel Super Hero Squad Online</a>, <a href="/facts/R.U.S.E./6msa79P4">R.U.S.E.</a>, <a href="/facts/Supreme_Commander_2/y9GCm0fq">Supreme Commander 2</a> among others.<a class="footnote-ref" id="fnref:76" href="#fn:76"><sup>76</sup></a> However, some games not on this short list seem to work as well, e.g. <a href="/facts/Dirt_3/IKA2CNdg">Dirt 3</a> and <a href="/facts/The_Elder_Scrolls_V%3a_Skyrim/ESFn4mVx">The Elder Scrolls V: Skyrim</a>. </p><p><a href="/facts/KMS_driver/AjCBBvrU">KMS driver</a> supports AMD Eyefinity.<a class="footnote-ref" id="fnref:77" href="#fn:77"><sup>77</sup></a> </p> <h2 id="see-also">See also</h2> Wikimedia Commons has media related to AMD Eyefinity. <ul><li><a href="/facts/AMD_FireMV/WRtMxIXV">AMD FireMV</a> – pre-Eyefinity products for multi-monitor set-ups</li> <li><a href="/facts/Multi-monitor/KnL7NhG0">Multi-monitor</a></li></ul> <h2 id="external-links">External links</h2> <ul><li><a href="https://www.youtube.com/watch?v=rxp2Y_FISoI">AMD Eyefinity 5x1 Portrait and 120Hz</a> on <a href="/facts/YouTube_video_(identifier)/db276jst">YouTube</a> playing <a href="/facts/The_Elder_Scrolls_V%3a_Skyrim/ESFn4mVx">The Elder Scrolls V: Skyrim</a></li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>"AMD's Radeon HD 5870 Eyefinity 6 Edition Reviewed". AnandTech. 2010-03-31. Retrieved 2014-07-02. <a href="http://www.anandtech.com/show/3621/amds-radeon-hd-5870-eyefinity-6-edition-reviewed" target="_blank">http://www.anandtech.com/show/3621/amds-radeon-hd-5870-eyefinity-6-edition-reviewed</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>"AMD Eyefinity: FAQ". AMD. 2011-05-17. Retrieved 2014-07-02. <a href="http://support.amd.com/en-us/kb-articles/Pages/AMDEyefinityFAQs.aspx" target="_blank">http://support.amd.com/en-us/kb-articles/Pages/AMDEyefinityFAQs.aspx</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>"How do I connect three or More Monitors to an AMD Radeon HD 5000, HD 6000, and HD 7000 Series Graphics Card?". AMD. Retrieved 2014-12-08. <a href="http://support.amd.com/en-us/search/faq/154" target="_blank">http://support.amd.com/en-us/search/faq/154</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>"Radeon feature matrix". freedesktop.org. Retrieved 10 January 2016. <a href="http://xorg.freedesktop.org/wiki/RadeonFeature/" target="_blank">http://xorg.freedesktop.org/wiki/RadeonFeature/</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>"Configuring and Running a Large Video Wall using ATI FirePro Graphics" (PDF). Retrieved 2014-07-04. <a href="https://www.amd.com/Documents/Configuring_and_Running_Large_Video_Wall_using_ATI_FirePros_v1-2.pdf" target="_blank">https://www.amd.com/Documents/Configuring_and_Running_Large_Video_Wall_using_ATI_FirePros_v1-2.pdf</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>"Carrizo introduces a new video playback pathways". <a href="http://www.anandtech.com/show/9319/amd-launches-carrizo-the-laptop-leap-of-efficiency-and-architecture-updates/6" target="_blank">http://www.anandtech.com/show/9319/amd-launches-carrizo-the-laptop-leap-of-efficiency-and-architecture-updates/6</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>"AMD Eyefinity on AMD Radeon HD 5870". Tom's Hardware. 2009-09-23. Retrieved 2014-07-02. <a href="http://www.tomshardware.com/reviews/radeon-hd-5870,2422-8.html" target="_blank">http://www.tomshardware.com/reviews/radeon-hd-5870,2422-8.html</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> <li id="fn:8"><p>"AMD Eyefinity on AMD Radeon HD 5870". Tom's Hardware. 2009-09-23. Retrieved 2014-07-02. <a href="http://www.tomshardware.com/reviews/radeon-hd-5870,2422-8.html" target="_blank">http://www.tomshardware.com/reviews/radeon-hd-5870,2422-8.html</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></p></li> <li id="fn:9"><p>"Presenting Radeon HD 5000" (PDF). <a href="http://highperformancegraphics.org/previous/www_2010/media/Hot3D/HPG2010_Hot3D_AMD.pdf" target="_blank">http://highperformancegraphics.org/previous/www_2010/media/Hot3D/HPG2010_Hot3D_AMD.pdf</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></p></li> <li id="fn:10"><p>"Radeon feature matrix". freedesktop.org. Retrieved 10 January 2016. <a href="http://xorg.freedesktop.org/wiki/RadeonFeature/" target="_blank">http://xorg.freedesktop.org/wiki/RadeonFeature/</a> <a href="#fnref:10" class="footnote-back-ref">↩</a></p></li> <li id="fn:11"><p>"AMD Radeon HD 6900 (AMD Cayman) series graphics cards". HWlab. hw-lab.com. December 19, 2010. Archived from the original on August 23, 2022. Retrieved August 23, 2022. New VLIW4 architecture of stream processors allowed to save area of each SIMD by 10%, while performing the same compared to previous VLIW5 architecture <a href="http://web.archive.org/web/20220823180458/https://hw-lab.com/amd-radeon-hd-6900-series-amd-cayman.html/4" target="_blank">http://web.archive.org/web/20220823180458/https://hw-lab.com/amd-radeon-hd-6900-series-amd-cayman.html/4</a> <a href="#fnref:11" class="footnote-back-ref">↩</a></p></li> <li id="fn:12"><p>"GPU Specs Database". TechPowerUp. Retrieved August 23, 2022. <a href="https://www.techpowerup.com/gpu-specs/?generation=Northern%20Islands&architecture=TeraScale%203&sort=generation" target="_blank">https://www.techpowerup.com/gpu-specs/?generation=Northern%20Islands&architecture=TeraScale%203&sort=generation</a> <a href="#fnref:12" class="footnote-back-ref">↩</a></p></li> <li id="fn:13"><p>The Radeon 100 Series has programmable pixel shaders, but do not fully comply with DirectX 8 or Pixel Shader 1.0. See article on R100's pixel shaders. <a href="/wiki/Radeon_R100_series#R100's_pixel_shaders" target="_blank">/wiki/Radeon_R100_series#R100's_pixel_shaders</a> <a href="#fnref:13" class="footnote-back-ref">↩</a></p></li> <li id="fn:14"><p>R300, R400 and R500 based cards do not fully comply with OpenGL 2+ as the hardware does not support all types of non-power of two (NPOT) textures. <a href="#fnref:14" class="footnote-back-ref">↩</a></p></li> <li id="fn:15"><p>"NPOT Texture (OpenGL Wiki)". Khronos Group. Retrieved February 10, 2021. <a href="https://www.khronos.org/opengl/wiki/NPOT_Texture" target="_blank">https://www.khronos.org/opengl/wiki/NPOT_Texture</a> <a href="#fnref:15" class="footnote-back-ref">↩</a></p></li> <li id="fn:16"><p>"AMD Radeon Software Crimson Edition Beta". AMD. Retrieved 2018-04-20. <a href="https://support.amd.com/en-us/kb-articles/pages/amd-radeon-software-crimson-edition-beta.aspx" target="_blank">https://support.amd.com/en-us/kb-articles/pages/amd-radeon-software-crimson-edition-beta.aspx</a> <a href="#fnref:16" class="footnote-back-ref">↩</a></p></li> <li id="fn:17"><p>"Mesamatrix". mesamatrix.net. Retrieved 2018-04-22. <a href="https://mesamatrix.net/" target="_blank">https://mesamatrix.net/</a> <a href="#fnref:17" class="footnote-back-ref">↩</a></p></li> <li id="fn:18"><p>"RadeonFeature". X.Org Foundation. Retrieved 2018-04-20. <a href="https://www.x.org/wiki/RadeonFeature/" target="_blank">https://www.x.org/wiki/RadeonFeature/</a> <a href="#fnref:18" class="footnote-back-ref">↩</a></p></li> <li id="fn:19"><p>OpenGL 4+ compliance requires supporting FP64 shaders and these are emulated on some TeraScale chips using 32-bit hardware. <a href="#fnref:19" class="footnote-back-ref">↩</a></p></li> <li id="fn:20"><p>OpenGL 4+ compliance requires supporting FP64 shaders and these are emulated on some TeraScale chips using 32-bit hardware. <a href="#fnref:20" class="footnote-back-ref">↩</a></p></li> <li id="fn:21"><p>Vulkan support is theoretically possible but has not been implemented in a stable driver. <a href="#fnref:21" class="footnote-back-ref">↩</a></p></li> <li id="fn:22"><p>"Conformant Products". Khronos Group. Retrieved 2024-12-02. <a href="https://www.khronos.org/conformance/adopters/conformant-products#submission_820" target="_blank">https://www.khronos.org/conformance/adopters/conformant-products#submission_820</a> <a href="#fnref:22" class="footnote-back-ref">↩</a></p></li> <li id="fn:23"><p>"radv: add Vulkan 1.4 support". Mesa. Retrieved 2024-12-02. <a href="https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32432" target="_blank">https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32432</a> <a href="#fnref:23" class="footnote-back-ref">↩</a></p></li> <li id="fn:24"><p>"AMD Radeon RX 6800 XT Specs". TechPowerUp. Retrieved January 1, 2021. <a href="https://www.techpowerup.com/gpu-specs/radeon-rx-6800-xt.c3694" target="_blank">https://www.techpowerup.com/gpu-specs/radeon-rx-6800-xt.c3694</a> <a href="#fnref:24" class="footnote-back-ref">↩</a></p></li> <li id="fn:25"><p>"AMD Launches The Radeon PRO W7500/W7600 RDNA3 GPUs". Phoronix. 3 August 2023. Retrieved 4 September 2023. <a href="https://www.phoronix.com/news/AMD-Radeon-PRO-W7500-W7600" target="_blank">https://www.phoronix.com/news/AMD-Radeon-PRO-W7500-W7600</a> <a href="#fnref:25" class="footnote-back-ref">↩</a></p></li> <li id="fn:26"><p>"AMD Radeon Pro 5600M Grafikkarte". TopCPU.net (in German). Retrieved 4 September 2023. <a href="https://www.topcpu.net/de/cpu/Radeon-Pro-5600M" target="_blank">https://www.topcpu.net/de/cpu/Radeon-Pro-5600M</a> <a href="#fnref:26" class="footnote-back-ref">↩</a></p></li> <li id="fn:27"><p>Killian, Zak (March 22, 2017). "AMD publishes patches for Vega support on Linux". Tech Report. Retrieved March 23, 2017. <a href="https://techreport.com/news/31627/amd-publishes-patches-for-vega-support-on-linux" target="_blank">https://techreport.com/news/31627/amd-publishes-patches-for-vega-support-on-linux</a> <a href="#fnref:27" class="footnote-back-ref">↩</a></p></li> <li id="fn:28"><p>The UVD and VCE were replaced by the Video Core Next (VCN) ASIC in the Raven Ridge APU implementation of Vega. <a href="/wiki/Ryzen#Raven_Ridge" target="_blank">/wiki/Ryzen#Raven_Ridge</a> <a href="#fnref:28" class="footnote-back-ref">↩</a></p></li> <li id="fn:29"><p>Killian, Zak (March 22, 2017). "AMD publishes patches for Vega support on Linux". Tech Report. Retrieved March 23, 2017. <a href="https://techreport.com/news/31627/amd-publishes-patches-for-vega-support-on-linux" target="_blank">https://techreport.com/news/31627/amd-publishes-patches-for-vega-support-on-linux</a> <a href="#fnref:29" class="footnote-back-ref">↩</a></p></li> <li id="fn:30"><p>The UVD and VCE were replaced by the Video Core Next (VCN) ASIC in the Raven Ridge APU implementation of Vega. <a href="/wiki/Ryzen#Raven_Ridge" target="_blank">/wiki/Ryzen#Raven_Ridge</a> <a href="#fnref:30" class="footnote-back-ref">↩</a></p></li> <li id="fn:31"><p>Larabel, Michael (September 15, 2020). "AMD Radeon Navi 2 / VCN 3.0 Supports AV1 Video Decoding". Phoronix. Retrieved January 1, 2021. <a href="https://www.phoronix.com/scan.php?page=news_item&px=AV1-Decode-For-AMD-VCN-3.0" target="_blank">https://www.phoronix.com/scan.php?page=news_item&px=AV1-Decode-For-AMD-VCN-3.0</a> <a href="#fnref:31" class="footnote-back-ref">↩</a></p></li> <li id="fn:32"><p>Killian, Zak (March 22, 2017). "AMD publishes patches for Vega support on Linux". Tech Report. Retrieved March 23, 2017. <a href="https://techreport.com/news/31627/amd-publishes-patches-for-vega-support-on-linux" target="_blank">https://techreport.com/news/31627/amd-publishes-patches-for-vega-support-on-linux</a> <a href="#fnref:32" class="footnote-back-ref">↩</a></p></li> <li id="fn:33"><p>The UVD and VCE were replaced by the Video Core Next (VCN) ASIC in the Raven Ridge APU implementation of Vega. <a href="/wiki/Ryzen#Raven_Ridge" target="_blank">/wiki/Ryzen#Raven_Ridge</a> <a href="#fnref:33" class="footnote-back-ref">↩</a></p></li> <li id="fn:34"><p>Video processing for video frame rate interpolation technique. In Windows it works as a DirectShow filter in your player. In Linux, there is no support on the part of drivers and / or community. <a href="#fnref:34" class="footnote-back-ref">↩</a></p></li> <li id="fn:35"><p>To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup. <a href="#fnref:35" class="footnote-back-ref">↩</a></p></li> <li id="fn:36"><p>Edmonds, Rich (February 4, 2022). "ASUS Dual RX 6600 GPU review: Rock-solid 1080p gaming with impressive thermals". Windows Central. Retrieved November 1, 2022. <a href="https://www.windowscentral.com/asus-dual-rx-6600-gpu-review" target="_blank">https://www.windowscentral.com/asus-dual-rx-6600-gpu-review</a> <a href="#fnref:36" class="footnote-back-ref">↩</a></p></li> <li id="fn:37"><p>To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup. <a href="#fnref:37" class="footnote-back-ref">↩</a></p></li> <li id="fn:38"><p>More displays may be supported with native DisplayPort connections, or splitting the maximum resolution between multiple monitors with active converters. <a href="/wiki/DisplayPort" target="_blank">/wiki/DisplayPort</a> <a href="#fnref:38" class="footnote-back-ref">↩</a></p></li> <li id="fn:39"><p>"Radeon's next-generation Vega architecture" (PDF). Radeon Technologies Group (AMD). Archived from the original (PDF) on September 6, 2018. Retrieved June 13, 2017. <a href="https://web.archive.org/web/20180906124605/http://radeon.com/_downloads/vega-whitepaper-11.6.17.pdf" target="_blank">https://web.archive.org/web/20180906124605/http://radeon.com/_downloads/vega-whitepaper-11.6.17.pdf</a> <a href="#fnref:39" class="footnote-back-ref">↩</a></p></li> <li id="fn:40"><p>DRM (Direct Rendering Manager) is a component of the Linux kernel. AMDgpu is the Linux kernel module. Support in this table refers to the most current version. <a href="/wiki/Direct_Rendering_Manager" target="_blank">/wiki/Direct_Rendering_Manager</a> <a href="#fnref:40" class="footnote-back-ref">↩</a></p></li> <li id="fn:41"><p>DRM (Direct Rendering Manager) is a component of the Linux kernel. AMDgpu is the Linux kernel module. Support in this table refers to the most current version. <a href="/wiki/Direct_Rendering_Manager" target="_blank">/wiki/Direct_Rendering_Manager</a> <a href="#fnref:41" class="footnote-back-ref">↩</a></p></li> <li id="fn:42"><p>"AMDGPU". Retrieved December 29, 2023. <a href="https://wiki.gentoo.org/wiki/AMDGPU" target="_blank">https://wiki.gentoo.org/wiki/AMDGPU</a> <a href="#fnref:42" class="footnote-back-ref">↩</a></p></li> <li id="fn:43"><p>"AMD Announces the 7th Generation APU: Excavator mk2 in Bristol Ridge and Stoney Ridge for Notebooks". 31 May 2016. Retrieved 3 January 2020. <a href="https://www.anandtech.com/show/10362/amd-7th-generation-apu-bristol-ridge-stoney-ridge-for-notebooks" target="_blank">https://www.anandtech.com/show/10362/amd-7th-generation-apu-bristol-ridge-stoney-ridge-for-notebooks</a> <a href="#fnref:43" class="footnote-back-ref">↩</a></p></li> <li id="fn:44"><p>"AMD Mobile "Carrizo" Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015" (Press release). 20 November 2014. Retrieved 16 February 2015. <a href="https://www.amd.com/en-us/press-releases/Pages/amd-mobile-carrizo-2014nov20.aspx" target="_blank">https://www.amd.com/en-us/press-releases/Pages/amd-mobile-carrizo-2014nov20.aspx</a> <a href="#fnref:44" class="footnote-back-ref">↩</a></p></li> <li id="fn:45"><p>For FM2+ Excavator models: A8-7680, A6-7480 & Athlon X4 845. <a href="#fnref:45" class="footnote-back-ref">↩</a></p></li> <li id="fn:46"><p>"The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List". TechARP.com. Retrieved 13 December 2017. <a href="https://www.techarp.com/guides/mobile-cpu-comparison-guide/5/" target="_blank">https://www.techarp.com/guides/mobile-cpu-comparison-guide/5/</a> <a href="#fnref:46" class="footnote-back-ref">↩</a></p></li> <li id="fn:47"><p>A PC would be one node. <a href="#fnref:47" class="footnote-back-ref">↩</a></p></li> <li id="fn:48"><p>An APU combines a CPU and a GPU. Both have cores. <a href="#fnref:48" class="footnote-back-ref">↩</a></p></li> <li id="fn:49"><p>Requires firmware support. <a href="#fnref:49" class="footnote-back-ref">↩</a></p></li> <li id="fn:50"><p>Requires firmware support. <a href="#fnref:50" class="footnote-back-ref">↩</a></p></li> <li id="fn:51"><p>Requires firmware support. <a href="#fnref:51" class="footnote-back-ref">↩</a></p></li> <li id="fn:52"><p>No SSE4. No SSSE3. <a href="#fnref:52" class="footnote-back-ref">↩</a></p></li> <li id="fn:53"><p>"AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver". VideoCardz.com. Retrieved 6 June 2017. <a href="http://videocardz.com/62250/amd-vega10-and-vega11-gpus-spotted-in-opencl-driver/" target="_blank">http://videocardz.com/62250/amd-vega10-and-vega11-gpus-spotted-in-opencl-driver/</a> <a href="#fnref:53" class="footnote-back-ref">↩</a></p></li> <li id="fn:54"><p>"AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver". VideoCardz.com. Retrieved 6 June 2017. <a href="http://videocardz.com/62250/amd-vega10-and-vega11-gpus-spotted-in-opencl-driver/" target="_blank">http://videocardz.com/62250/amd-vega10-and-vega11-gpus-spotted-in-opencl-driver/</a> <a href="#fnref:54" class="footnote-back-ref">↩</a></p></li> <li id="fn:55"><p>Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation. <a href="/wiki/Single-precision_floating-point_format" target="_blank">/wiki/Single-precision_floating-point_format</a> <a href="#fnref:55" class="footnote-back-ref">↩</a></p></li> <li id="fn:56"><p>Unified shaders : texture mapping units : render output units <a href="/wiki/Unified_shader_model" target="_blank">/wiki/Unified_shader_model</a> <a href="#fnref:56" class="footnote-back-ref">↩</a></p></li> <li id="fn:57"><p>Cutress, Ian (1 February 2018). "Zen Cores and Vega: Ryzen APUs for AM4 – AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm". Anandtech. Retrieved 7 February 2018. <a href="https://www.anandtech.com/show/12233/amd-tech-day-at-ces-2018-roadmap-revealed-with-ryzen-apus-zen-on-12nm-vega-on-7nm/3" target="_blank">https://www.anandtech.com/show/12233/amd-tech-day-at-ces-2018-roadmap-revealed-with-ryzen-apus-zen-on-12nm-vega-on-7nm/3</a> <a href="#fnref:57" class="footnote-back-ref">↩</a></p></li> <li id="fn:58"><p>Larabel, Michael (17 November 2017). "Radeon VCN Encode Support Lands in Mesa 17.4 Git". Phoronix. Retrieved 20 November 2017. <a href="https://www.phoronix.com/scan.php?page=news_item&px=Radeon-VCN-Encode-Lands" target="_blank">https://www.phoronix.com/scan.php?page=news_item&px=Radeon-VCN-Encode-Lands</a> <a href="#fnref:58" class="footnote-back-ref">↩</a></p></li> <li id="fn:59"><p>"AMD Ryzen 5000G 'Cezanne' APU Gets First High-Res Die Shots, 10.7 Billion Transistors In A 180mm2 Package". wccftech. Aug 12, 2021. Retrieved August 25, 2021. <a href="https://wccftech.com/amd-ryzen-5000g-cezanne-apu-first-high-res-die-shots-10-7-billion-transistors/" target="_blank">https://wccftech.com/amd-ryzen-5000g-cezanne-apu-first-high-res-die-shots-10-7-billion-transistors/</a> <a href="#fnref:59" class="footnote-back-ref">↩</a></p></li> <li id="fn:60"><p>"AMD Ryzen 5000G 'Cezanne' APU Gets First High-Res Die Shots, 10.7 Billion Transistors In A 180mm2 Package". wccftech. Aug 12, 2021. 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